1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/pci/pci.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qemu/error-report.h" 29 #include "hw/audio/soundhw.h" 30 #include "intel-hda.h" 31 #include "migration/vmstate.h" 32 #include "intel-hda-defs.h" 33 #include "sysemu/dma.h" 34 #include "qapi/error.h" 35 #include "qom/object.h" 36 37 /* --------------------------------------------------------------------- */ 38 /* hda bus */ 39 40 static Property hda_props[] = { 41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 42 DEFINE_PROP_END_OF_LIST() 43 }; 44 45 static const TypeInfo hda_codec_bus_info = { 46 .name = TYPE_HDA_BUS, 47 .parent = TYPE_BUS, 48 .instance_size = sizeof(HDACodecBus), 49 }; 50 51 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 52 hda_codec_response_func response, 53 hda_codec_xfer_func xfer) 54 { 55 qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 56 bus->response = response; 57 bus->xfer = xfer; 58 } 59 60 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 61 { 62 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 63 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 64 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 65 66 if (dev->cad == -1) { 67 dev->cad = bus->next_cad; 68 } 69 if (dev->cad >= 15) { 70 error_setg(errp, "HDA audio codec address is full"); 71 return; 72 } 73 bus->next_cad = dev->cad + 1; 74 if (cdc->init(dev) != 0) { 75 error_setg(errp, "HDA audio init failed"); 76 } 77 } 78 79 static void hda_codec_dev_unrealize(DeviceState *qdev) 80 { 81 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 82 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 83 84 if (cdc->exit) { 85 cdc->exit(dev); 86 } 87 } 88 89 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 90 { 91 BusChild *kid; 92 HDACodecDevice *cdev; 93 94 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 95 DeviceState *qdev = kid->child; 96 cdev = HDA_CODEC_DEVICE(qdev); 97 if (cdev->cad == cad) { 98 return cdev; 99 } 100 } 101 return NULL; 102 } 103 104 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 105 { 106 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 107 bus->response(dev, solicited, response); 108 } 109 110 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 111 uint8_t *buf, uint32_t len) 112 { 113 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 114 return bus->xfer(dev, stnr, output, buf, len); 115 } 116 117 /* --------------------------------------------------------------------- */ 118 /* intel hda emulation */ 119 120 typedef struct IntelHDAStream IntelHDAStream; 121 typedef struct IntelHDAState IntelHDAState; 122 typedef struct IntelHDAReg IntelHDAReg; 123 124 typedef struct bpl { 125 uint64_t addr; 126 uint32_t len; 127 uint32_t flags; 128 } bpl; 129 130 struct IntelHDAStream { 131 /* registers */ 132 uint32_t ctl; 133 uint32_t lpib; 134 uint32_t cbl; 135 uint32_t lvi; 136 uint32_t fmt; 137 uint32_t bdlp_lbase; 138 uint32_t bdlp_ubase; 139 140 /* state */ 141 bpl *bpl; 142 uint32_t bentries; 143 uint32_t bsize, be, bp; 144 }; 145 146 struct IntelHDAState { 147 PCIDevice pci; 148 const char *name; 149 HDACodecBus codecs; 150 151 /* registers */ 152 uint32_t g_ctl; 153 uint32_t wake_en; 154 uint32_t state_sts; 155 uint32_t int_ctl; 156 uint32_t int_sts; 157 uint32_t wall_clk; 158 159 uint32_t corb_lbase; 160 uint32_t corb_ubase; 161 uint32_t corb_rp; 162 uint32_t corb_wp; 163 uint32_t corb_ctl; 164 uint32_t corb_sts; 165 uint32_t corb_size; 166 167 uint32_t rirb_lbase; 168 uint32_t rirb_ubase; 169 uint32_t rirb_wp; 170 uint32_t rirb_cnt; 171 uint32_t rirb_ctl; 172 uint32_t rirb_sts; 173 uint32_t rirb_size; 174 175 uint32_t dp_lbase; 176 uint32_t dp_ubase; 177 178 uint32_t icw; 179 uint32_t irr; 180 uint32_t ics; 181 182 /* streams */ 183 IntelHDAStream st[8]; 184 185 /* state */ 186 MemoryRegion container; 187 MemoryRegion mmio; 188 MemoryRegion alias; 189 uint32_t rirb_count; 190 int64_t wall_base_ns; 191 192 /* debug logging */ 193 const IntelHDAReg *last_reg; 194 uint32_t last_val; 195 uint32_t last_write; 196 uint32_t last_sec; 197 uint32_t repeat_count; 198 199 /* properties */ 200 uint32_t debug; 201 OnOffAuto msi; 202 bool old_msi_addr; 203 }; 204 205 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 206 207 DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA, 208 TYPE_INTEL_HDA_GENERIC) 209 210 struct IntelHDAReg { 211 const char *name; /* register name */ 212 uint32_t size; /* size in bytes */ 213 uint32_t reset; /* reset value */ 214 uint32_t wmask; /* write mask */ 215 uint32_t wclear; /* write 1 to clear bits */ 216 uint32_t offset; /* location in IntelHDAState */ 217 uint32_t shift; /* byte access entries for dwords */ 218 uint32_t stream; 219 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 220 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 221 }; 222 223 static void intel_hda_reset(DeviceState *dev); 224 225 /* --------------------------------------------------------------------- */ 226 227 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 228 { 229 return ((uint64_t)ubase << 32) | lbase; 230 } 231 232 static void intel_hda_update_int_sts(IntelHDAState *d) 233 { 234 uint32_t sts = 0; 235 uint32_t i; 236 237 /* update controller status */ 238 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 239 sts |= (1 << 30); 240 } 241 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 242 sts |= (1 << 30); 243 } 244 if (d->state_sts & d->wake_en) { 245 sts |= (1 << 30); 246 } 247 248 /* update stream status */ 249 for (i = 0; i < 8; i++) { 250 /* buffer completion interrupt */ 251 if (d->st[i].ctl & (1 << 26)) { 252 sts |= (1 << i); 253 } 254 } 255 256 /* update global status */ 257 if (sts & d->int_ctl) { 258 sts |= (1U << 31); 259 } 260 261 d->int_sts = sts; 262 } 263 264 static void intel_hda_update_irq(IntelHDAState *d) 265 { 266 bool msi = msi_enabled(&d->pci); 267 int level; 268 269 intel_hda_update_int_sts(d); 270 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 271 level = 1; 272 } else { 273 level = 0; 274 } 275 dprint(d, 2, "%s: level %d [%s]\n", __func__, 276 level, msi ? "msi" : "intx"); 277 if (msi) { 278 if (level) { 279 msi_notify(&d->pci, 0); 280 } 281 } else { 282 pci_set_irq(&d->pci, level); 283 } 284 } 285 286 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 287 { 288 uint32_t cad, nid, data; 289 HDACodecDevice *codec; 290 HDACodecDeviceClass *cdc; 291 292 cad = (verb >> 28) & 0x0f; 293 if (verb & (1 << 27)) { 294 /* indirect node addressing, not specified in HDA 1.0 */ 295 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 296 return -1; 297 } 298 nid = (verb >> 20) & 0x7f; 299 data = verb & 0xfffff; 300 301 codec = hda_codec_find(&d->codecs, cad); 302 if (codec == NULL) { 303 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 304 return -1; 305 } 306 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 307 cdc->command(codec, nid, data); 308 return 0; 309 } 310 311 static void intel_hda_corb_run(IntelHDAState *d) 312 { 313 hwaddr addr; 314 uint32_t rp, verb; 315 316 if (d->ics & ICH6_IRS_BUSY) { 317 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 318 intel_hda_send_command(d, d->icw); 319 return; 320 } 321 322 for (;;) { 323 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 324 dprint(d, 2, "%s: !run\n", __func__); 325 return; 326 } 327 if ((d->corb_rp & 0xff) == d->corb_wp) { 328 dprint(d, 2, "%s: corb ring empty\n", __func__); 329 return; 330 } 331 if (d->rirb_count == d->rirb_cnt) { 332 dprint(d, 2, "%s: rirb count reached\n", __func__); 333 return; 334 } 335 336 rp = (d->corb_rp + 1) & 0xff; 337 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 338 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 339 d->corb_rp = rp; 340 341 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 342 intel_hda_send_command(d, verb); 343 } 344 } 345 346 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 347 { 348 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 349 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 350 hwaddr addr; 351 uint32_t wp, ex; 352 353 if (d->ics & ICH6_IRS_BUSY) { 354 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 355 __func__, response, dev->cad); 356 d->irr = response; 357 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 358 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 359 return; 360 } 361 362 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 363 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 364 return; 365 } 366 367 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 368 wp = (d->rirb_wp + 1) & 0xff; 369 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 370 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 371 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 372 d->rirb_wp = wp; 373 374 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 375 __func__, wp, response, ex); 376 377 d->rirb_count++; 378 if (d->rirb_count == d->rirb_cnt) { 379 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 380 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 381 d->rirb_sts |= ICH6_RBSTS_IRQ; 382 intel_hda_update_irq(d); 383 } 384 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 385 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 386 d->rirb_count, d->rirb_cnt); 387 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 388 d->rirb_sts |= ICH6_RBSTS_IRQ; 389 intel_hda_update_irq(d); 390 } 391 } 392 } 393 394 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 395 uint8_t *buf, uint32_t len) 396 { 397 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 398 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 399 hwaddr addr; 400 uint32_t s, copy, left; 401 IntelHDAStream *st; 402 bool irq = false; 403 404 st = output ? d->st + 4 : d->st; 405 for (s = 0; s < 4; s++) { 406 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 407 st = st + s; 408 break; 409 } 410 } 411 if (s == 4) { 412 return false; 413 } 414 if (st->bpl == NULL) { 415 return false; 416 } 417 418 left = len; 419 s = st->bentries; 420 while (left > 0 && s-- > 0) { 421 copy = left; 422 if (copy > st->bsize - st->lpib) 423 copy = st->bsize - st->lpib; 424 if (copy > st->bpl[st->be].len - st->bp) 425 copy = st->bpl[st->be].len - st->bp; 426 427 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 428 st->be, st->bp, st->bpl[st->be].len, copy); 429 430 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); 431 st->lpib += copy; 432 st->bp += copy; 433 buf += copy; 434 left -= copy; 435 436 if (st->bpl[st->be].len == st->bp) { 437 /* bpl entry filled */ 438 if (st->bpl[st->be].flags & 0x01) { 439 irq = true; 440 } 441 st->bp = 0; 442 st->be++; 443 if (st->be == st->bentries) { 444 /* bpl wrap around */ 445 st->be = 0; 446 st->lpib = 0; 447 } 448 } 449 } 450 if (d->dp_lbase & 0x01) { 451 s = st - d->st; 452 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 453 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 454 } 455 dprint(d, 3, "dma: --\n"); 456 457 if (irq) { 458 st->ctl |= (1 << 26); /* buffer completion interrupt */ 459 intel_hda_update_irq(d); 460 } 461 return true; 462 } 463 464 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 465 { 466 hwaddr addr; 467 uint8_t buf[16]; 468 uint32_t i; 469 470 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 471 st->bentries = st->lvi +1; 472 g_free(st->bpl); 473 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 474 for (i = 0; i < st->bentries; i++, addr += 16) { 475 pci_dma_read(&d->pci, addr, buf, 16); 476 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 477 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 478 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 479 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 480 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 481 } 482 483 st->bsize = st->cbl; 484 st->lpib = 0; 485 st->be = 0; 486 st->bp = 0; 487 } 488 489 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 490 { 491 BusChild *kid; 492 HDACodecDevice *cdev; 493 494 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 495 DeviceState *qdev = kid->child; 496 HDACodecDeviceClass *cdc; 497 498 cdev = HDA_CODEC_DEVICE(qdev); 499 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 500 if (cdc->stream) { 501 cdc->stream(cdev, stream, running, output); 502 } 503 } 504 } 505 506 /* --------------------------------------------------------------------- */ 507 508 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 509 { 510 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 511 intel_hda_reset(DEVICE(d)); 512 } 513 } 514 515 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 516 { 517 intel_hda_update_irq(d); 518 } 519 520 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 521 { 522 intel_hda_update_irq(d); 523 } 524 525 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 526 { 527 intel_hda_update_irq(d); 528 } 529 530 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 531 { 532 int64_t ns; 533 534 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 535 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 536 } 537 538 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 539 { 540 intel_hda_corb_run(d); 541 } 542 543 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 544 { 545 intel_hda_corb_run(d); 546 } 547 548 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 549 { 550 if (d->rirb_wp & ICH6_RIRBWP_RST) { 551 d->rirb_wp = 0; 552 } 553 } 554 555 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 556 { 557 intel_hda_update_irq(d); 558 559 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 560 /* cleared ICH6_RBSTS_IRQ */ 561 d->rirb_count = 0; 562 intel_hda_corb_run(d); 563 } 564 } 565 566 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 567 { 568 if (d->ics & ICH6_IRS_BUSY) { 569 intel_hda_corb_run(d); 570 } 571 } 572 573 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 574 { 575 bool output = reg->stream >= 4; 576 IntelHDAStream *st = d->st + reg->stream; 577 578 if (st->ctl & 0x01) { 579 /* reset */ 580 dprint(d, 1, "st #%d: reset\n", reg->stream); 581 st->ctl = SD_STS_FIFO_READY << 24; 582 } 583 if ((st->ctl & 0x02) != (old & 0x02)) { 584 uint32_t stnr = (st->ctl >> 20) & 0x0f; 585 /* run bit flipped */ 586 if (st->ctl & 0x02) { 587 /* start */ 588 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 589 reg->stream, stnr, st->cbl); 590 intel_hda_parse_bdl(d, st); 591 intel_hda_notify_codecs(d, stnr, true, output); 592 } else { 593 /* stop */ 594 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 595 intel_hda_notify_codecs(d, stnr, false, output); 596 } 597 } 598 intel_hda_update_irq(d); 599 } 600 601 /* --------------------------------------------------------------------- */ 602 603 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 604 605 static const struct IntelHDAReg regtab[] = { 606 /* global */ 607 [ ICH6_REG_GCAP ] = { 608 .name = "GCAP", 609 .size = 2, 610 .reset = 0x4401, 611 }, 612 [ ICH6_REG_VMIN ] = { 613 .name = "VMIN", 614 .size = 1, 615 }, 616 [ ICH6_REG_VMAJ ] = { 617 .name = "VMAJ", 618 .size = 1, 619 .reset = 1, 620 }, 621 [ ICH6_REG_OUTPAY ] = { 622 .name = "OUTPAY", 623 .size = 2, 624 .reset = 0x3c, 625 }, 626 [ ICH6_REG_INPAY ] = { 627 .name = "INPAY", 628 .size = 2, 629 .reset = 0x1d, 630 }, 631 [ ICH6_REG_GCTL ] = { 632 .name = "GCTL", 633 .size = 4, 634 .wmask = 0x0103, 635 .offset = offsetof(IntelHDAState, g_ctl), 636 .whandler = intel_hda_set_g_ctl, 637 }, 638 [ ICH6_REG_WAKEEN ] = { 639 .name = "WAKEEN", 640 .size = 2, 641 .wmask = 0x7fff, 642 .offset = offsetof(IntelHDAState, wake_en), 643 .whandler = intel_hda_set_wake_en, 644 }, 645 [ ICH6_REG_STATESTS ] = { 646 .name = "STATESTS", 647 .size = 2, 648 .wmask = 0x7fff, 649 .wclear = 0x7fff, 650 .offset = offsetof(IntelHDAState, state_sts), 651 .whandler = intel_hda_set_state_sts, 652 }, 653 654 /* interrupts */ 655 [ ICH6_REG_INTCTL ] = { 656 .name = "INTCTL", 657 .size = 4, 658 .wmask = 0xc00000ff, 659 .offset = offsetof(IntelHDAState, int_ctl), 660 .whandler = intel_hda_set_int_ctl, 661 }, 662 [ ICH6_REG_INTSTS ] = { 663 .name = "INTSTS", 664 .size = 4, 665 .wmask = 0xc00000ff, 666 .wclear = 0xc00000ff, 667 .offset = offsetof(IntelHDAState, int_sts), 668 }, 669 670 /* misc */ 671 [ ICH6_REG_WALLCLK ] = { 672 .name = "WALLCLK", 673 .size = 4, 674 .offset = offsetof(IntelHDAState, wall_clk), 675 .rhandler = intel_hda_get_wall_clk, 676 }, 677 678 /* dma engine */ 679 [ ICH6_REG_CORBLBASE ] = { 680 .name = "CORBLBASE", 681 .size = 4, 682 .wmask = 0xffffff80, 683 .offset = offsetof(IntelHDAState, corb_lbase), 684 }, 685 [ ICH6_REG_CORBUBASE ] = { 686 .name = "CORBUBASE", 687 .size = 4, 688 .wmask = 0xffffffff, 689 .offset = offsetof(IntelHDAState, corb_ubase), 690 }, 691 [ ICH6_REG_CORBWP ] = { 692 .name = "CORBWP", 693 .size = 2, 694 .wmask = 0xff, 695 .offset = offsetof(IntelHDAState, corb_wp), 696 .whandler = intel_hda_set_corb_wp, 697 }, 698 [ ICH6_REG_CORBRP ] = { 699 .name = "CORBRP", 700 .size = 2, 701 .wmask = 0x80ff, 702 .offset = offsetof(IntelHDAState, corb_rp), 703 }, 704 [ ICH6_REG_CORBCTL ] = { 705 .name = "CORBCTL", 706 .size = 1, 707 .wmask = 0x03, 708 .offset = offsetof(IntelHDAState, corb_ctl), 709 .whandler = intel_hda_set_corb_ctl, 710 }, 711 [ ICH6_REG_CORBSTS ] = { 712 .name = "CORBSTS", 713 .size = 1, 714 .wmask = 0x01, 715 .wclear = 0x01, 716 .offset = offsetof(IntelHDAState, corb_sts), 717 }, 718 [ ICH6_REG_CORBSIZE ] = { 719 .name = "CORBSIZE", 720 .size = 1, 721 .reset = 0x42, 722 .offset = offsetof(IntelHDAState, corb_size), 723 }, 724 [ ICH6_REG_RIRBLBASE ] = { 725 .name = "RIRBLBASE", 726 .size = 4, 727 .wmask = 0xffffff80, 728 .offset = offsetof(IntelHDAState, rirb_lbase), 729 }, 730 [ ICH6_REG_RIRBUBASE ] = { 731 .name = "RIRBUBASE", 732 .size = 4, 733 .wmask = 0xffffffff, 734 .offset = offsetof(IntelHDAState, rirb_ubase), 735 }, 736 [ ICH6_REG_RIRBWP ] = { 737 .name = "RIRBWP", 738 .size = 2, 739 .wmask = 0x8000, 740 .offset = offsetof(IntelHDAState, rirb_wp), 741 .whandler = intel_hda_set_rirb_wp, 742 }, 743 [ ICH6_REG_RINTCNT ] = { 744 .name = "RINTCNT", 745 .size = 2, 746 .wmask = 0xff, 747 .offset = offsetof(IntelHDAState, rirb_cnt), 748 }, 749 [ ICH6_REG_RIRBCTL ] = { 750 .name = "RIRBCTL", 751 .size = 1, 752 .wmask = 0x07, 753 .offset = offsetof(IntelHDAState, rirb_ctl), 754 }, 755 [ ICH6_REG_RIRBSTS ] = { 756 .name = "RIRBSTS", 757 .size = 1, 758 .wmask = 0x05, 759 .wclear = 0x05, 760 .offset = offsetof(IntelHDAState, rirb_sts), 761 .whandler = intel_hda_set_rirb_sts, 762 }, 763 [ ICH6_REG_RIRBSIZE ] = { 764 .name = "RIRBSIZE", 765 .size = 1, 766 .reset = 0x42, 767 .offset = offsetof(IntelHDAState, rirb_size), 768 }, 769 770 [ ICH6_REG_DPLBASE ] = { 771 .name = "DPLBASE", 772 .size = 4, 773 .wmask = 0xffffff81, 774 .offset = offsetof(IntelHDAState, dp_lbase), 775 }, 776 [ ICH6_REG_DPUBASE ] = { 777 .name = "DPUBASE", 778 .size = 4, 779 .wmask = 0xffffffff, 780 .offset = offsetof(IntelHDAState, dp_ubase), 781 }, 782 783 [ ICH6_REG_IC ] = { 784 .name = "ICW", 785 .size = 4, 786 .wmask = 0xffffffff, 787 .offset = offsetof(IntelHDAState, icw), 788 }, 789 [ ICH6_REG_IR ] = { 790 .name = "IRR", 791 .size = 4, 792 .offset = offsetof(IntelHDAState, irr), 793 }, 794 [ ICH6_REG_IRS ] = { 795 .name = "ICS", 796 .size = 2, 797 .wmask = 0x0003, 798 .wclear = 0x0002, 799 .offset = offsetof(IntelHDAState, ics), 800 .whandler = intel_hda_set_ics, 801 }, 802 803 #define HDA_STREAM(_t, _i) \ 804 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 805 .stream = _i, \ 806 .name = _t stringify(_i) " CTL", \ 807 .size = 4, \ 808 .wmask = 0x1cff001f, \ 809 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 810 .whandler = intel_hda_set_st_ctl, \ 811 }, \ 812 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 813 .stream = _i, \ 814 .name = _t stringify(_i) " CTL(stnr)", \ 815 .size = 1, \ 816 .shift = 16, \ 817 .wmask = 0x00ff0000, \ 818 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 819 .whandler = intel_hda_set_st_ctl, \ 820 }, \ 821 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 822 .stream = _i, \ 823 .name = _t stringify(_i) " CTL(sts)", \ 824 .size = 1, \ 825 .shift = 24, \ 826 .wmask = 0x1c000000, \ 827 .wclear = 0x1c000000, \ 828 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 829 .whandler = intel_hda_set_st_ctl, \ 830 .reset = SD_STS_FIFO_READY << 24 \ 831 }, \ 832 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 833 .stream = _i, \ 834 .name = _t stringify(_i) " LPIB", \ 835 .size = 4, \ 836 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 837 }, \ 838 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 839 .stream = _i, \ 840 .name = _t stringify(_i) " CBL", \ 841 .size = 4, \ 842 .wmask = 0xffffffff, \ 843 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 844 }, \ 845 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 846 .stream = _i, \ 847 .name = _t stringify(_i) " LVI", \ 848 .size = 2, \ 849 .wmask = 0x00ff, \ 850 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 851 }, \ 852 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 853 .stream = _i, \ 854 .name = _t stringify(_i) " FIFOS", \ 855 .size = 2, \ 856 .reset = HDA_BUFFER_SIZE, \ 857 }, \ 858 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 859 .stream = _i, \ 860 .name = _t stringify(_i) " FMT", \ 861 .size = 2, \ 862 .wmask = 0x7f7f, \ 863 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 864 }, \ 865 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 866 .stream = _i, \ 867 .name = _t stringify(_i) " BDLPL", \ 868 .size = 4, \ 869 .wmask = 0xffffff80, \ 870 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 871 }, \ 872 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 873 .stream = _i, \ 874 .name = _t stringify(_i) " BDLPU", \ 875 .size = 4, \ 876 .wmask = 0xffffffff, \ 877 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 878 }, \ 879 880 HDA_STREAM("IN", 0) 881 HDA_STREAM("IN", 1) 882 HDA_STREAM("IN", 2) 883 HDA_STREAM("IN", 3) 884 885 HDA_STREAM("OUT", 4) 886 HDA_STREAM("OUT", 5) 887 HDA_STREAM("OUT", 6) 888 HDA_STREAM("OUT", 7) 889 890 }; 891 892 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 893 { 894 const IntelHDAReg *reg; 895 896 if (addr >= ARRAY_SIZE(regtab)) { 897 goto noreg; 898 } 899 reg = regtab+addr; 900 if (reg->name == NULL) { 901 goto noreg; 902 } 903 return reg; 904 905 noreg: 906 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 907 return NULL; 908 } 909 910 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 911 { 912 uint8_t *addr = (void*)d; 913 914 addr += reg->offset; 915 return (uint32_t*)addr; 916 } 917 918 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 919 uint32_t wmask) 920 { 921 uint32_t *addr; 922 uint32_t old; 923 924 if (!reg) { 925 return; 926 } 927 if (!reg->wmask) { 928 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 929 reg->name); 930 return; 931 } 932 933 if (d->debug) { 934 time_t now = time(NULL); 935 if (d->last_write && d->last_reg == reg && d->last_val == val) { 936 d->repeat_count++; 937 if (d->last_sec != now) { 938 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 939 d->last_sec = now; 940 d->repeat_count = 0; 941 } 942 } else { 943 if (d->repeat_count) { 944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 945 } 946 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 947 d->last_write = 1; 948 d->last_reg = reg; 949 d->last_val = val; 950 d->last_sec = now; 951 d->repeat_count = 0; 952 } 953 } 954 assert(reg->offset != 0); 955 956 addr = intel_hda_reg_addr(d, reg); 957 old = *addr; 958 959 if (reg->shift) { 960 val <<= reg->shift; 961 wmask <<= reg->shift; 962 } 963 wmask &= reg->wmask; 964 *addr &= ~wmask; 965 *addr |= wmask & val; 966 *addr &= ~(val & reg->wclear); 967 968 if (reg->whandler) { 969 reg->whandler(d, reg, old); 970 } 971 } 972 973 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 974 uint32_t rmask) 975 { 976 uint32_t *addr, ret; 977 978 if (!reg) { 979 return 0; 980 } 981 982 if (reg->rhandler) { 983 reg->rhandler(d, reg); 984 } 985 986 if (reg->offset == 0) { 987 /* constant read-only register */ 988 ret = reg->reset; 989 } else { 990 addr = intel_hda_reg_addr(d, reg); 991 ret = *addr; 992 if (reg->shift) { 993 ret >>= reg->shift; 994 } 995 ret &= rmask; 996 } 997 if (d->debug) { 998 time_t now = time(NULL); 999 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1000 d->repeat_count++; 1001 if (d->last_sec != now) { 1002 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1003 d->last_sec = now; 1004 d->repeat_count = 0; 1005 } 1006 } else { 1007 if (d->repeat_count) { 1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1009 } 1010 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1011 d->last_write = 0; 1012 d->last_reg = reg; 1013 d->last_val = ret; 1014 d->last_sec = now; 1015 d->repeat_count = 0; 1016 } 1017 } 1018 return ret; 1019 } 1020 1021 static void intel_hda_regs_reset(IntelHDAState *d) 1022 { 1023 uint32_t *addr; 1024 int i; 1025 1026 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1027 if (regtab[i].name == NULL) { 1028 continue; 1029 } 1030 if (regtab[i].offset == 0) { 1031 continue; 1032 } 1033 addr = intel_hda_reg_addr(d, regtab + i); 1034 *addr = regtab[i].reset; 1035 } 1036 } 1037 1038 /* --------------------------------------------------------------------- */ 1039 1040 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1041 unsigned size) 1042 { 1043 IntelHDAState *d = opaque; 1044 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1045 1046 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1047 } 1048 1049 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1050 { 1051 IntelHDAState *d = opaque; 1052 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1053 1054 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1055 } 1056 1057 static const MemoryRegionOps intel_hda_mmio_ops = { 1058 .read = intel_hda_mmio_read, 1059 .write = intel_hda_mmio_write, 1060 .impl = { 1061 .min_access_size = 1, 1062 .max_access_size = 4, 1063 }, 1064 .endianness = DEVICE_NATIVE_ENDIAN, 1065 }; 1066 1067 /* --------------------------------------------------------------------- */ 1068 1069 static void intel_hda_reset(DeviceState *dev) 1070 { 1071 BusChild *kid; 1072 IntelHDAState *d = INTEL_HDA(dev); 1073 HDACodecDevice *cdev; 1074 1075 intel_hda_regs_reset(d); 1076 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1077 1078 /* reset codecs */ 1079 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1080 DeviceState *qdev = kid->child; 1081 cdev = HDA_CODEC_DEVICE(qdev); 1082 device_legacy_reset(DEVICE(cdev)); 1083 d->state_sts |= (1 << cdev->cad); 1084 } 1085 intel_hda_update_irq(d); 1086 } 1087 1088 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1089 { 1090 IntelHDAState *d = INTEL_HDA(pci); 1091 uint8_t *conf = d->pci.config; 1092 Error *err = NULL; 1093 int ret; 1094 1095 d->name = object_get_typename(OBJECT(d)); 1096 1097 pci_config_set_interrupt_pin(conf, 1); 1098 1099 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1100 conf[0x40] = 0x01; 1101 1102 if (d->msi != ON_OFF_AUTO_OFF) { 1103 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1104 1, true, false, &err); 1105 /* Any error other than -ENOTSUP(board's MSI support is broken) 1106 * is a programming error */ 1107 assert(!ret || ret == -ENOTSUP); 1108 if (ret && d->msi == ON_OFF_AUTO_ON) { 1109 /* Can't satisfy user's explicit msi=on request, fail */ 1110 error_append_hint(&err, "You have to use msi=auto (default) or " 1111 "msi=off with this machine type.\n"); 1112 error_propagate(errp, err); 1113 return; 1114 } 1115 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1116 /* With msi=auto, we fall back to MSI off silently */ 1117 error_free(err); 1118 } 1119 1120 memory_region_init(&d->container, OBJECT(d), 1121 "intel-hda-container", 0x4000); 1122 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1123 "intel-hda", 0x2000); 1124 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); 1125 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", 1126 &d->mmio, 0, 0x2000); 1127 memory_region_add_subregion(&d->container, 0x2000, &d->alias); 1128 pci_register_bar(&d->pci, 0, 0, &d->container); 1129 1130 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1131 intel_hda_response, intel_hda_xfer); 1132 } 1133 1134 static void intel_hda_exit(PCIDevice *pci) 1135 { 1136 IntelHDAState *d = INTEL_HDA(pci); 1137 1138 msi_uninit(&d->pci); 1139 } 1140 1141 static int intel_hda_post_load(void *opaque, int version) 1142 { 1143 IntelHDAState* d = opaque; 1144 int i; 1145 1146 dprint(d, 1, "%s\n", __func__); 1147 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1148 if (d->st[i].ctl & 0x02) { 1149 intel_hda_parse_bdl(d, &d->st[i]); 1150 } 1151 } 1152 intel_hda_update_irq(d); 1153 return 0; 1154 } 1155 1156 static const VMStateDescription vmstate_intel_hda_stream = { 1157 .name = "intel-hda-stream", 1158 .version_id = 1, 1159 .fields = (VMStateField[]) { 1160 VMSTATE_UINT32(ctl, IntelHDAStream), 1161 VMSTATE_UINT32(lpib, IntelHDAStream), 1162 VMSTATE_UINT32(cbl, IntelHDAStream), 1163 VMSTATE_UINT32(lvi, IntelHDAStream), 1164 VMSTATE_UINT32(fmt, IntelHDAStream), 1165 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1166 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1167 VMSTATE_END_OF_LIST() 1168 } 1169 }; 1170 1171 static const VMStateDescription vmstate_intel_hda = { 1172 .name = "intel-hda", 1173 .version_id = 1, 1174 .post_load = intel_hda_post_load, 1175 .fields = (VMStateField[]) { 1176 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1177 1178 /* registers */ 1179 VMSTATE_UINT32(g_ctl, IntelHDAState), 1180 VMSTATE_UINT32(wake_en, IntelHDAState), 1181 VMSTATE_UINT32(state_sts, IntelHDAState), 1182 VMSTATE_UINT32(int_ctl, IntelHDAState), 1183 VMSTATE_UINT32(int_sts, IntelHDAState), 1184 VMSTATE_UINT32(wall_clk, IntelHDAState), 1185 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1186 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1187 VMSTATE_UINT32(corb_rp, IntelHDAState), 1188 VMSTATE_UINT32(corb_wp, IntelHDAState), 1189 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1190 VMSTATE_UINT32(corb_sts, IntelHDAState), 1191 VMSTATE_UINT32(corb_size, IntelHDAState), 1192 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1193 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1194 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1195 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1196 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1197 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1198 VMSTATE_UINT32(rirb_size, IntelHDAState), 1199 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1200 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1201 VMSTATE_UINT32(icw, IntelHDAState), 1202 VMSTATE_UINT32(irr, IntelHDAState), 1203 VMSTATE_UINT32(ics, IntelHDAState), 1204 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1205 vmstate_intel_hda_stream, 1206 IntelHDAStream), 1207 1208 /* additional state info */ 1209 VMSTATE_UINT32(rirb_count, IntelHDAState), 1210 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1211 1212 VMSTATE_END_OF_LIST() 1213 } 1214 }; 1215 1216 static Property intel_hda_properties[] = { 1217 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1218 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1219 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1220 DEFINE_PROP_END_OF_LIST(), 1221 }; 1222 1223 static void intel_hda_class_init(ObjectClass *klass, void *data) 1224 { 1225 DeviceClass *dc = DEVICE_CLASS(klass); 1226 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1227 1228 k->realize = intel_hda_realize; 1229 k->exit = intel_hda_exit; 1230 k->vendor_id = PCI_VENDOR_ID_INTEL; 1231 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1232 dc->reset = intel_hda_reset; 1233 dc->vmsd = &vmstate_intel_hda; 1234 device_class_set_props(dc, intel_hda_properties); 1235 } 1236 1237 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1238 { 1239 DeviceClass *dc = DEVICE_CLASS(klass); 1240 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1241 1242 k->device_id = 0x2668; 1243 k->revision = 1; 1244 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1245 dc->desc = "Intel HD Audio Controller (ich6)"; 1246 } 1247 1248 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1249 { 1250 DeviceClass *dc = DEVICE_CLASS(klass); 1251 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1252 1253 k->device_id = 0x293e; 1254 k->revision = 3; 1255 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1256 dc->desc = "Intel HD Audio Controller (ich9)"; 1257 } 1258 1259 static const TypeInfo intel_hda_info = { 1260 .name = TYPE_INTEL_HDA_GENERIC, 1261 .parent = TYPE_PCI_DEVICE, 1262 .instance_size = sizeof(IntelHDAState), 1263 .class_init = intel_hda_class_init, 1264 .abstract = true, 1265 .interfaces = (InterfaceInfo[]) { 1266 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1267 { }, 1268 }, 1269 }; 1270 1271 static const TypeInfo intel_hda_info_ich6 = { 1272 .name = "intel-hda", 1273 .parent = TYPE_INTEL_HDA_GENERIC, 1274 .class_init = intel_hda_class_init_ich6, 1275 }; 1276 1277 static const TypeInfo intel_hda_info_ich9 = { 1278 .name = "ich9-intel-hda", 1279 .parent = TYPE_INTEL_HDA_GENERIC, 1280 .class_init = intel_hda_class_init_ich9, 1281 }; 1282 1283 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1284 { 1285 DeviceClass *k = DEVICE_CLASS(klass); 1286 k->realize = hda_codec_dev_realize; 1287 k->unrealize = hda_codec_dev_unrealize; 1288 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1289 k->bus_type = TYPE_HDA_BUS; 1290 device_class_set_props(k, hda_props); 1291 } 1292 1293 static const TypeInfo hda_codec_device_type_info = { 1294 .name = TYPE_HDA_CODEC_DEVICE, 1295 .parent = TYPE_DEVICE, 1296 .instance_size = sizeof(HDACodecDevice), 1297 .abstract = true, 1298 .class_size = sizeof(HDACodecDeviceClass), 1299 .class_init = hda_codec_device_class_init, 1300 }; 1301 1302 /* 1303 * create intel hda controller with codec attached to it, 1304 * so '-soundhw hda' works. 1305 */ 1306 static int intel_hda_and_codec_init(PCIBus *bus) 1307 { 1308 DeviceState *controller; 1309 BusState *hdabus; 1310 DeviceState *codec; 1311 1312 warn_report("'-soundhw hda' is deprecated, " 1313 "please use '-device intel-hda -device hda-duplex' instead"); 1314 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1315 hdabus = QLIST_FIRST(&controller->child_bus); 1316 codec = qdev_new("hda-duplex"); 1317 qdev_realize_and_unref(codec, hdabus, &error_fatal); 1318 return 0; 1319 } 1320 1321 static void intel_hda_register_types(void) 1322 { 1323 type_register_static(&hda_codec_bus_info); 1324 type_register_static(&intel_hda_info); 1325 type_register_static(&intel_hda_info_ich6); 1326 type_register_static(&intel_hda_info_ich9); 1327 type_register_static(&hda_codec_device_type_info); 1328 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1329 } 1330 1331 type_init(intel_hda_register_types) 1332