1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "hw/pci/pci.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "hw/audio/soundhw.h" 28 #include "intel-hda.h" 29 #include "intel-hda-defs.h" 30 #include "sysemu/dma.h" 31 #include "qapi/error.h" 32 33 /* --------------------------------------------------------------------- */ 34 /* hda bus */ 35 36 static Property hda_props[] = { 37 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 38 DEFINE_PROP_END_OF_LIST() 39 }; 40 41 static const TypeInfo hda_codec_bus_info = { 42 .name = TYPE_HDA_BUS, 43 .parent = TYPE_BUS, 44 .instance_size = sizeof(HDACodecBus), 45 }; 46 47 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 48 hda_codec_response_func response, 49 hda_codec_xfer_func xfer) 50 { 51 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 52 bus->response = response; 53 bus->xfer = xfer; 54 } 55 56 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 57 { 58 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 59 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 60 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 61 62 if (dev->cad == -1) { 63 dev->cad = bus->next_cad; 64 } 65 if (dev->cad >= 15) { 66 error_setg(errp, "HDA audio codec address is full"); 67 return; 68 } 69 bus->next_cad = dev->cad + 1; 70 if (cdc->init(dev) != 0) { 71 error_setg(errp, "HDA audio init failed"); 72 } 73 } 74 75 static void hda_codec_dev_unrealize(DeviceState *qdev, Error **errp) 76 { 77 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 78 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 79 80 if (cdc->exit) { 81 cdc->exit(dev); 82 } 83 } 84 85 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 86 { 87 BusChild *kid; 88 HDACodecDevice *cdev; 89 90 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 91 DeviceState *qdev = kid->child; 92 cdev = HDA_CODEC_DEVICE(qdev); 93 if (cdev->cad == cad) { 94 return cdev; 95 } 96 } 97 return NULL; 98 } 99 100 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 101 { 102 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 103 bus->response(dev, solicited, response); 104 } 105 106 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 107 uint8_t *buf, uint32_t len) 108 { 109 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 110 return bus->xfer(dev, stnr, output, buf, len); 111 } 112 113 /* --------------------------------------------------------------------- */ 114 /* intel hda emulation */ 115 116 typedef struct IntelHDAStream IntelHDAStream; 117 typedef struct IntelHDAState IntelHDAState; 118 typedef struct IntelHDAReg IntelHDAReg; 119 120 typedef struct bpl { 121 uint64_t addr; 122 uint32_t len; 123 uint32_t flags; 124 } bpl; 125 126 struct IntelHDAStream { 127 /* registers */ 128 uint32_t ctl; 129 uint32_t lpib; 130 uint32_t cbl; 131 uint32_t lvi; 132 uint32_t fmt; 133 uint32_t bdlp_lbase; 134 uint32_t bdlp_ubase; 135 136 /* state */ 137 bpl *bpl; 138 uint32_t bentries; 139 uint32_t bsize, be, bp; 140 }; 141 142 struct IntelHDAState { 143 PCIDevice pci; 144 const char *name; 145 HDACodecBus codecs; 146 147 /* registers */ 148 uint32_t g_ctl; 149 uint32_t wake_en; 150 uint32_t state_sts; 151 uint32_t int_ctl; 152 uint32_t int_sts; 153 uint32_t wall_clk; 154 155 uint32_t corb_lbase; 156 uint32_t corb_ubase; 157 uint32_t corb_rp; 158 uint32_t corb_wp; 159 uint32_t corb_ctl; 160 uint32_t corb_sts; 161 uint32_t corb_size; 162 163 uint32_t rirb_lbase; 164 uint32_t rirb_ubase; 165 uint32_t rirb_wp; 166 uint32_t rirb_cnt; 167 uint32_t rirb_ctl; 168 uint32_t rirb_sts; 169 uint32_t rirb_size; 170 171 uint32_t dp_lbase; 172 uint32_t dp_ubase; 173 174 uint32_t icw; 175 uint32_t irr; 176 uint32_t ics; 177 178 /* streams */ 179 IntelHDAStream st[8]; 180 181 /* state */ 182 MemoryRegion mmio; 183 uint32_t rirb_count; 184 int64_t wall_base_ns; 185 186 /* debug logging */ 187 const IntelHDAReg *last_reg; 188 uint32_t last_val; 189 uint32_t last_write; 190 uint32_t last_sec; 191 uint32_t repeat_count; 192 193 /* properties */ 194 uint32_t debug; 195 OnOffAuto msi; 196 bool old_msi_addr; 197 }; 198 199 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 200 201 #define INTEL_HDA(obj) \ 202 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC) 203 204 struct IntelHDAReg { 205 const char *name; /* register name */ 206 uint32_t size; /* size in bytes */ 207 uint32_t reset; /* reset value */ 208 uint32_t wmask; /* write mask */ 209 uint32_t wclear; /* write 1 to clear bits */ 210 uint32_t offset; /* location in IntelHDAState */ 211 uint32_t shift; /* byte access entries for dwords */ 212 uint32_t stream; 213 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 214 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 215 }; 216 217 static void intel_hda_reset(DeviceState *dev); 218 219 /* --------------------------------------------------------------------- */ 220 221 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 222 { 223 return ((uint64_t)ubase << 32) | lbase; 224 } 225 226 static void intel_hda_update_int_sts(IntelHDAState *d) 227 { 228 uint32_t sts = 0; 229 uint32_t i; 230 231 /* update controller status */ 232 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 233 sts |= (1 << 30); 234 } 235 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 236 sts |= (1 << 30); 237 } 238 if (d->state_sts & d->wake_en) { 239 sts |= (1 << 30); 240 } 241 242 /* update stream status */ 243 for (i = 0; i < 8; i++) { 244 /* buffer completion interrupt */ 245 if (d->st[i].ctl & (1 << 26)) { 246 sts |= (1 << i); 247 } 248 } 249 250 /* update global status */ 251 if (sts & d->int_ctl) { 252 sts |= (1U << 31); 253 } 254 255 d->int_sts = sts; 256 } 257 258 static void intel_hda_update_irq(IntelHDAState *d) 259 { 260 bool msi = msi_enabled(&d->pci); 261 int level; 262 263 intel_hda_update_int_sts(d); 264 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 265 level = 1; 266 } else { 267 level = 0; 268 } 269 dprint(d, 2, "%s: level %d [%s]\n", __func__, 270 level, msi ? "msi" : "intx"); 271 if (msi) { 272 if (level) { 273 msi_notify(&d->pci, 0); 274 } 275 } else { 276 pci_set_irq(&d->pci, level); 277 } 278 } 279 280 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 281 { 282 uint32_t cad, nid, data; 283 HDACodecDevice *codec; 284 HDACodecDeviceClass *cdc; 285 286 cad = (verb >> 28) & 0x0f; 287 if (verb & (1 << 27)) { 288 /* indirect node addressing, not specified in HDA 1.0 */ 289 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 290 return -1; 291 } 292 nid = (verb >> 20) & 0x7f; 293 data = verb & 0xfffff; 294 295 codec = hda_codec_find(&d->codecs, cad); 296 if (codec == NULL) { 297 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 298 return -1; 299 } 300 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 301 cdc->command(codec, nid, data); 302 return 0; 303 } 304 305 static void intel_hda_corb_run(IntelHDAState *d) 306 { 307 hwaddr addr; 308 uint32_t rp, verb; 309 310 if (d->ics & ICH6_IRS_BUSY) { 311 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 312 intel_hda_send_command(d, d->icw); 313 return; 314 } 315 316 for (;;) { 317 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 318 dprint(d, 2, "%s: !run\n", __func__); 319 return; 320 } 321 if ((d->corb_rp & 0xff) == d->corb_wp) { 322 dprint(d, 2, "%s: corb ring empty\n", __func__); 323 return; 324 } 325 if (d->rirb_count == d->rirb_cnt) { 326 dprint(d, 2, "%s: rirb count reached\n", __func__); 327 return; 328 } 329 330 rp = (d->corb_rp + 1) & 0xff; 331 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 332 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 333 d->corb_rp = rp; 334 335 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 336 intel_hda_send_command(d, verb); 337 } 338 } 339 340 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 341 { 342 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 343 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 344 hwaddr addr; 345 uint32_t wp, ex; 346 347 if (d->ics & ICH6_IRS_BUSY) { 348 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 349 __func__, response, dev->cad); 350 d->irr = response; 351 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 352 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 353 return; 354 } 355 356 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 357 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 358 return; 359 } 360 361 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 362 wp = (d->rirb_wp + 1) & 0xff; 363 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 364 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 365 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 366 d->rirb_wp = wp; 367 368 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 369 __func__, wp, response, ex); 370 371 d->rirb_count++; 372 if (d->rirb_count == d->rirb_cnt) { 373 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 374 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 375 d->rirb_sts |= ICH6_RBSTS_IRQ; 376 intel_hda_update_irq(d); 377 } 378 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 379 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 380 d->rirb_count, d->rirb_cnt); 381 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 382 d->rirb_sts |= ICH6_RBSTS_IRQ; 383 intel_hda_update_irq(d); 384 } 385 } 386 } 387 388 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 389 uint8_t *buf, uint32_t len) 390 { 391 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 392 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 393 hwaddr addr; 394 uint32_t s, copy, left; 395 IntelHDAStream *st; 396 bool irq = false; 397 398 st = output ? d->st + 4 : d->st; 399 for (s = 0; s < 4; s++) { 400 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 401 st = st + s; 402 break; 403 } 404 } 405 if (s == 4) { 406 return false; 407 } 408 if (st->bpl == NULL) { 409 return false; 410 } 411 412 left = len; 413 s = st->bentries; 414 while (left > 0 && s-- > 0) { 415 copy = left; 416 if (copy > st->bsize - st->lpib) 417 copy = st->bsize - st->lpib; 418 if (copy > st->bpl[st->be].len - st->bp) 419 copy = st->bpl[st->be].len - st->bp; 420 421 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 422 st->be, st->bp, st->bpl[st->be].len, copy); 423 424 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); 425 st->lpib += copy; 426 st->bp += copy; 427 buf += copy; 428 left -= copy; 429 430 if (st->bpl[st->be].len == st->bp) { 431 /* bpl entry filled */ 432 if (st->bpl[st->be].flags & 0x01) { 433 irq = true; 434 } 435 st->bp = 0; 436 st->be++; 437 if (st->be == st->bentries) { 438 /* bpl wrap around */ 439 st->be = 0; 440 st->lpib = 0; 441 } 442 } 443 } 444 if (d->dp_lbase & 0x01) { 445 s = st - d->st; 446 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 447 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 448 } 449 dprint(d, 3, "dma: --\n"); 450 451 if (irq) { 452 st->ctl |= (1 << 26); /* buffer completion interrupt */ 453 intel_hda_update_irq(d); 454 } 455 return true; 456 } 457 458 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 459 { 460 hwaddr addr; 461 uint8_t buf[16]; 462 uint32_t i; 463 464 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 465 st->bentries = st->lvi +1; 466 g_free(st->bpl); 467 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 468 for (i = 0; i < st->bentries; i++, addr += 16) { 469 pci_dma_read(&d->pci, addr, buf, 16); 470 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 471 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 472 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 473 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 474 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 475 } 476 477 st->bsize = st->cbl; 478 st->lpib = 0; 479 st->be = 0; 480 st->bp = 0; 481 } 482 483 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 484 { 485 BusChild *kid; 486 HDACodecDevice *cdev; 487 488 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 489 DeviceState *qdev = kid->child; 490 HDACodecDeviceClass *cdc; 491 492 cdev = HDA_CODEC_DEVICE(qdev); 493 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 494 if (cdc->stream) { 495 cdc->stream(cdev, stream, running, output); 496 } 497 } 498 } 499 500 /* --------------------------------------------------------------------- */ 501 502 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 503 { 504 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 505 intel_hda_reset(DEVICE(d)); 506 } 507 } 508 509 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 510 { 511 intel_hda_update_irq(d); 512 } 513 514 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 515 { 516 intel_hda_update_irq(d); 517 } 518 519 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 520 { 521 intel_hda_update_irq(d); 522 } 523 524 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 525 { 526 int64_t ns; 527 528 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 529 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 530 } 531 532 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 533 { 534 intel_hda_corb_run(d); 535 } 536 537 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 538 { 539 intel_hda_corb_run(d); 540 } 541 542 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 543 { 544 if (d->rirb_wp & ICH6_RIRBWP_RST) { 545 d->rirb_wp = 0; 546 } 547 } 548 549 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 550 { 551 intel_hda_update_irq(d); 552 553 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 554 /* cleared ICH6_RBSTS_IRQ */ 555 d->rirb_count = 0; 556 intel_hda_corb_run(d); 557 } 558 } 559 560 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 561 { 562 if (d->ics & ICH6_IRS_BUSY) { 563 intel_hda_corb_run(d); 564 } 565 } 566 567 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 568 { 569 bool output = reg->stream >= 4; 570 IntelHDAStream *st = d->st + reg->stream; 571 572 if (st->ctl & 0x01) { 573 /* reset */ 574 dprint(d, 1, "st #%d: reset\n", reg->stream); 575 st->ctl = SD_STS_FIFO_READY << 24; 576 } 577 if ((st->ctl & 0x02) != (old & 0x02)) { 578 uint32_t stnr = (st->ctl >> 20) & 0x0f; 579 /* run bit flipped */ 580 if (st->ctl & 0x02) { 581 /* start */ 582 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 583 reg->stream, stnr, st->cbl); 584 intel_hda_parse_bdl(d, st); 585 intel_hda_notify_codecs(d, stnr, true, output); 586 } else { 587 /* stop */ 588 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 589 intel_hda_notify_codecs(d, stnr, false, output); 590 } 591 } 592 intel_hda_update_irq(d); 593 } 594 595 /* --------------------------------------------------------------------- */ 596 597 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 598 599 static const struct IntelHDAReg regtab[] = { 600 /* global */ 601 [ ICH6_REG_GCAP ] = { 602 .name = "GCAP", 603 .size = 2, 604 .reset = 0x4401, 605 }, 606 [ ICH6_REG_VMIN ] = { 607 .name = "VMIN", 608 .size = 1, 609 }, 610 [ ICH6_REG_VMAJ ] = { 611 .name = "VMAJ", 612 .size = 1, 613 .reset = 1, 614 }, 615 [ ICH6_REG_OUTPAY ] = { 616 .name = "OUTPAY", 617 .size = 2, 618 .reset = 0x3c, 619 }, 620 [ ICH6_REG_INPAY ] = { 621 .name = "INPAY", 622 .size = 2, 623 .reset = 0x1d, 624 }, 625 [ ICH6_REG_GCTL ] = { 626 .name = "GCTL", 627 .size = 4, 628 .wmask = 0x0103, 629 .offset = offsetof(IntelHDAState, g_ctl), 630 .whandler = intel_hda_set_g_ctl, 631 }, 632 [ ICH6_REG_WAKEEN ] = { 633 .name = "WAKEEN", 634 .size = 2, 635 .wmask = 0x7fff, 636 .offset = offsetof(IntelHDAState, wake_en), 637 .whandler = intel_hda_set_wake_en, 638 }, 639 [ ICH6_REG_STATESTS ] = { 640 .name = "STATESTS", 641 .size = 2, 642 .wmask = 0x7fff, 643 .wclear = 0x7fff, 644 .offset = offsetof(IntelHDAState, state_sts), 645 .whandler = intel_hda_set_state_sts, 646 }, 647 648 /* interrupts */ 649 [ ICH6_REG_INTCTL ] = { 650 .name = "INTCTL", 651 .size = 4, 652 .wmask = 0xc00000ff, 653 .offset = offsetof(IntelHDAState, int_ctl), 654 .whandler = intel_hda_set_int_ctl, 655 }, 656 [ ICH6_REG_INTSTS ] = { 657 .name = "INTSTS", 658 .size = 4, 659 .wmask = 0xc00000ff, 660 .wclear = 0xc00000ff, 661 .offset = offsetof(IntelHDAState, int_sts), 662 }, 663 664 /* misc */ 665 [ ICH6_REG_WALLCLK ] = { 666 .name = "WALLCLK", 667 .size = 4, 668 .offset = offsetof(IntelHDAState, wall_clk), 669 .rhandler = intel_hda_get_wall_clk, 670 }, 671 [ ICH6_REG_WALLCLK + 0x2000 ] = { 672 .name = "WALLCLK(alias)", 673 .size = 4, 674 .offset = offsetof(IntelHDAState, wall_clk), 675 .rhandler = intel_hda_get_wall_clk, 676 }, 677 678 /* dma engine */ 679 [ ICH6_REG_CORBLBASE ] = { 680 .name = "CORBLBASE", 681 .size = 4, 682 .wmask = 0xffffff80, 683 .offset = offsetof(IntelHDAState, corb_lbase), 684 }, 685 [ ICH6_REG_CORBUBASE ] = { 686 .name = "CORBUBASE", 687 .size = 4, 688 .wmask = 0xffffffff, 689 .offset = offsetof(IntelHDAState, corb_ubase), 690 }, 691 [ ICH6_REG_CORBWP ] = { 692 .name = "CORBWP", 693 .size = 2, 694 .wmask = 0xff, 695 .offset = offsetof(IntelHDAState, corb_wp), 696 .whandler = intel_hda_set_corb_wp, 697 }, 698 [ ICH6_REG_CORBRP ] = { 699 .name = "CORBRP", 700 .size = 2, 701 .wmask = 0x80ff, 702 .offset = offsetof(IntelHDAState, corb_rp), 703 }, 704 [ ICH6_REG_CORBCTL ] = { 705 .name = "CORBCTL", 706 .size = 1, 707 .wmask = 0x03, 708 .offset = offsetof(IntelHDAState, corb_ctl), 709 .whandler = intel_hda_set_corb_ctl, 710 }, 711 [ ICH6_REG_CORBSTS ] = { 712 .name = "CORBSTS", 713 .size = 1, 714 .wmask = 0x01, 715 .wclear = 0x01, 716 .offset = offsetof(IntelHDAState, corb_sts), 717 }, 718 [ ICH6_REG_CORBSIZE ] = { 719 .name = "CORBSIZE", 720 .size = 1, 721 .reset = 0x42, 722 .offset = offsetof(IntelHDAState, corb_size), 723 }, 724 [ ICH6_REG_RIRBLBASE ] = { 725 .name = "RIRBLBASE", 726 .size = 4, 727 .wmask = 0xffffff80, 728 .offset = offsetof(IntelHDAState, rirb_lbase), 729 }, 730 [ ICH6_REG_RIRBUBASE ] = { 731 .name = "RIRBUBASE", 732 .size = 4, 733 .wmask = 0xffffffff, 734 .offset = offsetof(IntelHDAState, rirb_ubase), 735 }, 736 [ ICH6_REG_RIRBWP ] = { 737 .name = "RIRBWP", 738 .size = 2, 739 .wmask = 0x8000, 740 .offset = offsetof(IntelHDAState, rirb_wp), 741 .whandler = intel_hda_set_rirb_wp, 742 }, 743 [ ICH6_REG_RINTCNT ] = { 744 .name = "RINTCNT", 745 .size = 2, 746 .wmask = 0xff, 747 .offset = offsetof(IntelHDAState, rirb_cnt), 748 }, 749 [ ICH6_REG_RIRBCTL ] = { 750 .name = "RIRBCTL", 751 .size = 1, 752 .wmask = 0x07, 753 .offset = offsetof(IntelHDAState, rirb_ctl), 754 }, 755 [ ICH6_REG_RIRBSTS ] = { 756 .name = "RIRBSTS", 757 .size = 1, 758 .wmask = 0x05, 759 .wclear = 0x05, 760 .offset = offsetof(IntelHDAState, rirb_sts), 761 .whandler = intel_hda_set_rirb_sts, 762 }, 763 [ ICH6_REG_RIRBSIZE ] = { 764 .name = "RIRBSIZE", 765 .size = 1, 766 .reset = 0x42, 767 .offset = offsetof(IntelHDAState, rirb_size), 768 }, 769 770 [ ICH6_REG_DPLBASE ] = { 771 .name = "DPLBASE", 772 .size = 4, 773 .wmask = 0xffffff81, 774 .offset = offsetof(IntelHDAState, dp_lbase), 775 }, 776 [ ICH6_REG_DPUBASE ] = { 777 .name = "DPUBASE", 778 .size = 4, 779 .wmask = 0xffffffff, 780 .offset = offsetof(IntelHDAState, dp_ubase), 781 }, 782 783 [ ICH6_REG_IC ] = { 784 .name = "ICW", 785 .size = 4, 786 .wmask = 0xffffffff, 787 .offset = offsetof(IntelHDAState, icw), 788 }, 789 [ ICH6_REG_IR ] = { 790 .name = "IRR", 791 .size = 4, 792 .offset = offsetof(IntelHDAState, irr), 793 }, 794 [ ICH6_REG_IRS ] = { 795 .name = "ICS", 796 .size = 2, 797 .wmask = 0x0003, 798 .wclear = 0x0002, 799 .offset = offsetof(IntelHDAState, ics), 800 .whandler = intel_hda_set_ics, 801 }, 802 803 #define HDA_STREAM(_t, _i) \ 804 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 805 .stream = _i, \ 806 .name = _t stringify(_i) " CTL", \ 807 .size = 4, \ 808 .wmask = 0x1cff001f, \ 809 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 810 .whandler = intel_hda_set_st_ctl, \ 811 }, \ 812 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 813 .stream = _i, \ 814 .name = _t stringify(_i) " CTL(stnr)", \ 815 .size = 1, \ 816 .shift = 16, \ 817 .wmask = 0x00ff0000, \ 818 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 819 .whandler = intel_hda_set_st_ctl, \ 820 }, \ 821 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 822 .stream = _i, \ 823 .name = _t stringify(_i) " CTL(sts)", \ 824 .size = 1, \ 825 .shift = 24, \ 826 .wmask = 0x1c000000, \ 827 .wclear = 0x1c000000, \ 828 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 829 .whandler = intel_hda_set_st_ctl, \ 830 .reset = SD_STS_FIFO_READY << 24 \ 831 }, \ 832 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 833 .stream = _i, \ 834 .name = _t stringify(_i) " LPIB", \ 835 .size = 4, \ 836 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 837 }, \ 838 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \ 839 .stream = _i, \ 840 .name = _t stringify(_i) " LPIB(alias)", \ 841 .size = 4, \ 842 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 843 }, \ 844 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 845 .stream = _i, \ 846 .name = _t stringify(_i) " CBL", \ 847 .size = 4, \ 848 .wmask = 0xffffffff, \ 849 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 850 }, \ 851 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 852 .stream = _i, \ 853 .name = _t stringify(_i) " LVI", \ 854 .size = 2, \ 855 .wmask = 0x00ff, \ 856 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 857 }, \ 858 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 859 .stream = _i, \ 860 .name = _t stringify(_i) " FIFOS", \ 861 .size = 2, \ 862 .reset = HDA_BUFFER_SIZE, \ 863 }, \ 864 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 865 .stream = _i, \ 866 .name = _t stringify(_i) " FMT", \ 867 .size = 2, \ 868 .wmask = 0x7f7f, \ 869 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 870 }, \ 871 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 872 .stream = _i, \ 873 .name = _t stringify(_i) " BDLPL", \ 874 .size = 4, \ 875 .wmask = 0xffffff80, \ 876 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 877 }, \ 878 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 879 .stream = _i, \ 880 .name = _t stringify(_i) " BDLPU", \ 881 .size = 4, \ 882 .wmask = 0xffffffff, \ 883 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 884 }, \ 885 886 HDA_STREAM("IN", 0) 887 HDA_STREAM("IN", 1) 888 HDA_STREAM("IN", 2) 889 HDA_STREAM("IN", 3) 890 891 HDA_STREAM("OUT", 4) 892 HDA_STREAM("OUT", 5) 893 HDA_STREAM("OUT", 6) 894 HDA_STREAM("OUT", 7) 895 896 }; 897 898 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 899 { 900 const IntelHDAReg *reg; 901 902 if (addr >= ARRAY_SIZE(regtab)) { 903 goto noreg; 904 } 905 reg = regtab+addr; 906 if (reg->name == NULL) { 907 goto noreg; 908 } 909 return reg; 910 911 noreg: 912 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 913 return NULL; 914 } 915 916 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 917 { 918 uint8_t *addr = (void*)d; 919 920 addr += reg->offset; 921 return (uint32_t*)addr; 922 } 923 924 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 925 uint32_t wmask) 926 { 927 uint32_t *addr; 928 uint32_t old; 929 930 if (!reg) { 931 return; 932 } 933 if (!reg->wmask) { 934 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 935 reg->name); 936 return; 937 } 938 939 if (d->debug) { 940 time_t now = time(NULL); 941 if (d->last_write && d->last_reg == reg && d->last_val == val) { 942 d->repeat_count++; 943 if (d->last_sec != now) { 944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 945 d->last_sec = now; 946 d->repeat_count = 0; 947 } 948 } else { 949 if (d->repeat_count) { 950 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 951 } 952 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 953 d->last_write = 1; 954 d->last_reg = reg; 955 d->last_val = val; 956 d->last_sec = now; 957 d->repeat_count = 0; 958 } 959 } 960 assert(reg->offset != 0); 961 962 addr = intel_hda_reg_addr(d, reg); 963 old = *addr; 964 965 if (reg->shift) { 966 val <<= reg->shift; 967 wmask <<= reg->shift; 968 } 969 wmask &= reg->wmask; 970 *addr &= ~wmask; 971 *addr |= wmask & val; 972 *addr &= ~(val & reg->wclear); 973 974 if (reg->whandler) { 975 reg->whandler(d, reg, old); 976 } 977 } 978 979 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 980 uint32_t rmask) 981 { 982 uint32_t *addr, ret; 983 984 if (!reg) { 985 return 0; 986 } 987 988 if (reg->rhandler) { 989 reg->rhandler(d, reg); 990 } 991 992 if (reg->offset == 0) { 993 /* constant read-only register */ 994 ret = reg->reset; 995 } else { 996 addr = intel_hda_reg_addr(d, reg); 997 ret = *addr; 998 if (reg->shift) { 999 ret >>= reg->shift; 1000 } 1001 ret &= rmask; 1002 } 1003 if (d->debug) { 1004 time_t now = time(NULL); 1005 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1006 d->repeat_count++; 1007 if (d->last_sec != now) { 1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1009 d->last_sec = now; 1010 d->repeat_count = 0; 1011 } 1012 } else { 1013 if (d->repeat_count) { 1014 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1015 } 1016 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1017 d->last_write = 0; 1018 d->last_reg = reg; 1019 d->last_val = ret; 1020 d->last_sec = now; 1021 d->repeat_count = 0; 1022 } 1023 } 1024 return ret; 1025 } 1026 1027 static void intel_hda_regs_reset(IntelHDAState *d) 1028 { 1029 uint32_t *addr; 1030 int i; 1031 1032 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1033 if (regtab[i].name == NULL) { 1034 continue; 1035 } 1036 if (regtab[i].offset == 0) { 1037 continue; 1038 } 1039 addr = intel_hda_reg_addr(d, regtab + i); 1040 *addr = regtab[i].reset; 1041 } 1042 } 1043 1044 /* --------------------------------------------------------------------- */ 1045 1046 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1047 unsigned size) 1048 { 1049 IntelHDAState *d = opaque; 1050 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1051 1052 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1053 } 1054 1055 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1056 { 1057 IntelHDAState *d = opaque; 1058 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1059 1060 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1061 } 1062 1063 static const MemoryRegionOps intel_hda_mmio_ops = { 1064 .read = intel_hda_mmio_read, 1065 .write = intel_hda_mmio_write, 1066 .impl = { 1067 .min_access_size = 1, 1068 .max_access_size = 4, 1069 }, 1070 .endianness = DEVICE_NATIVE_ENDIAN, 1071 }; 1072 1073 /* --------------------------------------------------------------------- */ 1074 1075 static void intel_hda_reset(DeviceState *dev) 1076 { 1077 BusChild *kid; 1078 IntelHDAState *d = INTEL_HDA(dev); 1079 HDACodecDevice *cdev; 1080 1081 intel_hda_regs_reset(d); 1082 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1083 1084 /* reset codecs */ 1085 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1086 DeviceState *qdev = kid->child; 1087 cdev = HDA_CODEC_DEVICE(qdev); 1088 device_reset(DEVICE(cdev)); 1089 d->state_sts |= (1 << cdev->cad); 1090 } 1091 intel_hda_update_irq(d); 1092 } 1093 1094 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1095 { 1096 IntelHDAState *d = INTEL_HDA(pci); 1097 uint8_t *conf = d->pci.config; 1098 Error *err = NULL; 1099 int ret; 1100 1101 d->name = object_get_typename(OBJECT(d)); 1102 1103 pci_config_set_interrupt_pin(conf, 1); 1104 1105 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1106 conf[0x40] = 0x01; 1107 1108 if (d->msi != ON_OFF_AUTO_OFF) { 1109 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1110 1, true, false, &err); 1111 /* Any error other than -ENOTSUP(board's MSI support is broken) 1112 * is a programming error */ 1113 assert(!ret || ret == -ENOTSUP); 1114 if (ret && d->msi == ON_OFF_AUTO_ON) { 1115 /* Can't satisfy user's explicit msi=on request, fail */ 1116 error_append_hint(&err, "You have to use msi=auto (default) or " 1117 "msi=off with this machine type.\n"); 1118 error_propagate(errp, err); 1119 return; 1120 } 1121 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1122 /* With msi=auto, we fall back to MSI off silently */ 1123 error_free(err); 1124 } 1125 1126 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1127 "intel-hda", 0x4000); 1128 pci_register_bar(&d->pci, 0, 0, &d->mmio); 1129 1130 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1131 intel_hda_response, intel_hda_xfer); 1132 } 1133 1134 static void intel_hda_exit(PCIDevice *pci) 1135 { 1136 IntelHDAState *d = INTEL_HDA(pci); 1137 1138 msi_uninit(&d->pci); 1139 } 1140 1141 static int intel_hda_post_load(void *opaque, int version) 1142 { 1143 IntelHDAState* d = opaque; 1144 int i; 1145 1146 dprint(d, 1, "%s\n", __func__); 1147 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1148 if (d->st[i].ctl & 0x02) { 1149 intel_hda_parse_bdl(d, &d->st[i]); 1150 } 1151 } 1152 intel_hda_update_irq(d); 1153 return 0; 1154 } 1155 1156 static const VMStateDescription vmstate_intel_hda_stream = { 1157 .name = "intel-hda-stream", 1158 .version_id = 1, 1159 .fields = (VMStateField[]) { 1160 VMSTATE_UINT32(ctl, IntelHDAStream), 1161 VMSTATE_UINT32(lpib, IntelHDAStream), 1162 VMSTATE_UINT32(cbl, IntelHDAStream), 1163 VMSTATE_UINT32(lvi, IntelHDAStream), 1164 VMSTATE_UINT32(fmt, IntelHDAStream), 1165 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1166 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1167 VMSTATE_END_OF_LIST() 1168 } 1169 }; 1170 1171 static const VMStateDescription vmstate_intel_hda = { 1172 .name = "intel-hda", 1173 .version_id = 1, 1174 .post_load = intel_hda_post_load, 1175 .fields = (VMStateField[]) { 1176 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1177 1178 /* registers */ 1179 VMSTATE_UINT32(g_ctl, IntelHDAState), 1180 VMSTATE_UINT32(wake_en, IntelHDAState), 1181 VMSTATE_UINT32(state_sts, IntelHDAState), 1182 VMSTATE_UINT32(int_ctl, IntelHDAState), 1183 VMSTATE_UINT32(int_sts, IntelHDAState), 1184 VMSTATE_UINT32(wall_clk, IntelHDAState), 1185 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1186 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1187 VMSTATE_UINT32(corb_rp, IntelHDAState), 1188 VMSTATE_UINT32(corb_wp, IntelHDAState), 1189 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1190 VMSTATE_UINT32(corb_sts, IntelHDAState), 1191 VMSTATE_UINT32(corb_size, IntelHDAState), 1192 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1193 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1194 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1195 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1196 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1197 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1198 VMSTATE_UINT32(rirb_size, IntelHDAState), 1199 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1200 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1201 VMSTATE_UINT32(icw, IntelHDAState), 1202 VMSTATE_UINT32(irr, IntelHDAState), 1203 VMSTATE_UINT32(ics, IntelHDAState), 1204 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1205 vmstate_intel_hda_stream, 1206 IntelHDAStream), 1207 1208 /* additional state info */ 1209 VMSTATE_UINT32(rirb_count, IntelHDAState), 1210 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1211 1212 VMSTATE_END_OF_LIST() 1213 } 1214 }; 1215 1216 static Property intel_hda_properties[] = { 1217 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1218 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1219 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1220 DEFINE_PROP_END_OF_LIST(), 1221 }; 1222 1223 static void intel_hda_class_init(ObjectClass *klass, void *data) 1224 { 1225 DeviceClass *dc = DEVICE_CLASS(klass); 1226 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1227 1228 k->realize = intel_hda_realize; 1229 k->exit = intel_hda_exit; 1230 k->vendor_id = PCI_VENDOR_ID_INTEL; 1231 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1232 dc->reset = intel_hda_reset; 1233 dc->vmsd = &vmstate_intel_hda; 1234 dc->props = intel_hda_properties; 1235 } 1236 1237 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1238 { 1239 DeviceClass *dc = DEVICE_CLASS(klass); 1240 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1241 1242 k->device_id = 0x2668; 1243 k->revision = 1; 1244 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1245 dc->desc = "Intel HD Audio Controller (ich6)"; 1246 } 1247 1248 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1249 { 1250 DeviceClass *dc = DEVICE_CLASS(klass); 1251 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1252 1253 k->device_id = 0x293e; 1254 k->revision = 3; 1255 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1256 dc->desc = "Intel HD Audio Controller (ich9)"; 1257 } 1258 1259 static const TypeInfo intel_hda_info = { 1260 .name = TYPE_INTEL_HDA_GENERIC, 1261 .parent = TYPE_PCI_DEVICE, 1262 .instance_size = sizeof(IntelHDAState), 1263 .class_init = intel_hda_class_init, 1264 .abstract = true, 1265 .interfaces = (InterfaceInfo[]) { 1266 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1267 { }, 1268 }, 1269 }; 1270 1271 static const TypeInfo intel_hda_info_ich6 = { 1272 .name = "intel-hda", 1273 .parent = TYPE_INTEL_HDA_GENERIC, 1274 .class_init = intel_hda_class_init_ich6, 1275 }; 1276 1277 static const TypeInfo intel_hda_info_ich9 = { 1278 .name = "ich9-intel-hda", 1279 .parent = TYPE_INTEL_HDA_GENERIC, 1280 .class_init = intel_hda_class_init_ich9, 1281 }; 1282 1283 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1284 { 1285 DeviceClass *k = DEVICE_CLASS(klass); 1286 k->realize = hda_codec_dev_realize; 1287 k->unrealize = hda_codec_dev_unrealize; 1288 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1289 k->bus_type = TYPE_HDA_BUS; 1290 k->props = hda_props; 1291 } 1292 1293 static const TypeInfo hda_codec_device_type_info = { 1294 .name = TYPE_HDA_CODEC_DEVICE, 1295 .parent = TYPE_DEVICE, 1296 .instance_size = sizeof(HDACodecDevice), 1297 .abstract = true, 1298 .class_size = sizeof(HDACodecDeviceClass), 1299 .class_init = hda_codec_device_class_init, 1300 }; 1301 1302 /* 1303 * create intel hda controller with codec attached to it, 1304 * so '-soundhw hda' works. 1305 */ 1306 static int intel_hda_and_codec_init(PCIBus *bus) 1307 { 1308 DeviceState *controller; 1309 BusState *hdabus; 1310 DeviceState *codec; 1311 1312 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1313 hdabus = QLIST_FIRST(&controller->child_bus); 1314 codec = qdev_create(hdabus, "hda-duplex"); 1315 qdev_init_nofail(codec); 1316 return 0; 1317 } 1318 1319 static void intel_hda_register_types(void) 1320 { 1321 type_register_static(&hda_codec_bus_info); 1322 type_register_static(&intel_hda_info); 1323 type_register_static(&intel_hda_info_ich6); 1324 type_register_static(&intel_hda_info_ich9); 1325 type_register_static(&hda_codec_device_type_info); 1326 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1327 } 1328 1329 type_init(intel_hda_register_types) 1330