1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/pci/pci.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qemu/error-report.h" 29 #include "hw/audio/soundhw.h" 30 #include "intel-hda.h" 31 #include "migration/vmstate.h" 32 #include "intel-hda-defs.h" 33 #include "sysemu/dma.h" 34 #include "qapi/error.h" 35 #include "qom/object.h" 36 37 /* --------------------------------------------------------------------- */ 38 /* hda bus */ 39 40 static Property hda_props[] = { 41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 42 DEFINE_PROP_END_OF_LIST() 43 }; 44 45 static const TypeInfo hda_codec_bus_info = { 46 .name = TYPE_HDA_BUS, 47 .parent = TYPE_BUS, 48 .instance_size = sizeof(HDACodecBus), 49 }; 50 51 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 52 hda_codec_response_func response, 53 hda_codec_xfer_func xfer) 54 { 55 qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 56 bus->response = response; 57 bus->xfer = xfer; 58 } 59 60 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 61 { 62 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 63 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 64 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 65 66 if (dev->cad == -1) { 67 dev->cad = bus->next_cad; 68 } 69 if (dev->cad >= 15) { 70 error_setg(errp, "HDA audio codec address is full"); 71 return; 72 } 73 bus->next_cad = dev->cad + 1; 74 if (cdc->init(dev) != 0) { 75 error_setg(errp, "HDA audio init failed"); 76 } 77 } 78 79 static void hda_codec_dev_unrealize(DeviceState *qdev) 80 { 81 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 82 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 83 84 if (cdc->exit) { 85 cdc->exit(dev); 86 } 87 } 88 89 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 90 { 91 BusChild *kid; 92 HDACodecDevice *cdev; 93 94 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 95 DeviceState *qdev = kid->child; 96 cdev = HDA_CODEC_DEVICE(qdev); 97 if (cdev->cad == cad) { 98 return cdev; 99 } 100 } 101 return NULL; 102 } 103 104 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 105 { 106 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 107 bus->response(dev, solicited, response); 108 } 109 110 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 111 uint8_t *buf, uint32_t len) 112 { 113 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 114 return bus->xfer(dev, stnr, output, buf, len); 115 } 116 117 /* --------------------------------------------------------------------- */ 118 /* intel hda emulation */ 119 120 typedef struct IntelHDAStream IntelHDAStream; 121 typedef struct IntelHDAState IntelHDAState; 122 typedef struct IntelHDAReg IntelHDAReg; 123 124 typedef struct bpl { 125 uint64_t addr; 126 uint32_t len; 127 uint32_t flags; 128 } bpl; 129 130 struct IntelHDAStream { 131 /* registers */ 132 uint32_t ctl; 133 uint32_t lpib; 134 uint32_t cbl; 135 uint32_t lvi; 136 uint32_t fmt; 137 uint32_t bdlp_lbase; 138 uint32_t bdlp_ubase; 139 140 /* state */ 141 bpl *bpl; 142 uint32_t bentries; 143 uint32_t bsize, be, bp; 144 }; 145 146 struct IntelHDAState { 147 PCIDevice pci; 148 const char *name; 149 HDACodecBus codecs; 150 151 /* registers */ 152 uint32_t g_ctl; 153 uint32_t wake_en; 154 uint32_t state_sts; 155 uint32_t int_ctl; 156 uint32_t int_sts; 157 uint32_t wall_clk; 158 159 uint32_t corb_lbase; 160 uint32_t corb_ubase; 161 uint32_t corb_rp; 162 uint32_t corb_wp; 163 uint32_t corb_ctl; 164 uint32_t corb_sts; 165 uint32_t corb_size; 166 167 uint32_t rirb_lbase; 168 uint32_t rirb_ubase; 169 uint32_t rirb_wp; 170 uint32_t rirb_cnt; 171 uint32_t rirb_ctl; 172 uint32_t rirb_sts; 173 uint32_t rirb_size; 174 175 uint32_t dp_lbase; 176 uint32_t dp_ubase; 177 178 uint32_t icw; 179 uint32_t irr; 180 uint32_t ics; 181 182 /* streams */ 183 IntelHDAStream st[8]; 184 185 /* state */ 186 MemoryRegion container; 187 MemoryRegion mmio; 188 MemoryRegion alias; 189 uint32_t rirb_count; 190 int64_t wall_base_ns; 191 192 /* debug logging */ 193 const IntelHDAReg *last_reg; 194 uint32_t last_val; 195 uint32_t last_write; 196 uint32_t last_sec; 197 uint32_t repeat_count; 198 199 /* properties */ 200 uint32_t debug; 201 OnOffAuto msi; 202 bool old_msi_addr; 203 }; 204 205 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 206 207 DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA, 208 TYPE_INTEL_HDA_GENERIC) 209 210 struct IntelHDAReg { 211 const char *name; /* register name */ 212 uint32_t size; /* size in bytes */ 213 uint32_t reset; /* reset value */ 214 uint32_t wmask; /* write mask */ 215 uint32_t wclear; /* write 1 to clear bits */ 216 uint32_t offset; /* location in IntelHDAState */ 217 uint32_t shift; /* byte access entries for dwords */ 218 uint32_t stream; 219 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 220 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 221 }; 222 223 static void intel_hda_reset(DeviceState *dev); 224 225 /* --------------------------------------------------------------------- */ 226 227 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 228 { 229 return ((uint64_t)ubase << 32) | lbase; 230 } 231 232 static void intel_hda_update_int_sts(IntelHDAState *d) 233 { 234 uint32_t sts = 0; 235 uint32_t i; 236 237 /* update controller status */ 238 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 239 sts |= (1 << 30); 240 } 241 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 242 sts |= (1 << 30); 243 } 244 if (d->state_sts & d->wake_en) { 245 sts |= (1 << 30); 246 } 247 248 /* update stream status */ 249 for (i = 0; i < 8; i++) { 250 /* buffer completion interrupt */ 251 if (d->st[i].ctl & (1 << 26)) { 252 sts |= (1 << i); 253 } 254 } 255 256 /* update global status */ 257 if (sts & d->int_ctl) { 258 sts |= (1U << 31); 259 } 260 261 d->int_sts = sts; 262 } 263 264 static void intel_hda_update_irq(IntelHDAState *d) 265 { 266 bool msi = msi_enabled(&d->pci); 267 int level; 268 269 intel_hda_update_int_sts(d); 270 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 271 level = 1; 272 } else { 273 level = 0; 274 } 275 dprint(d, 2, "%s: level %d [%s]\n", __func__, 276 level, msi ? "msi" : "intx"); 277 if (msi) { 278 if (level) { 279 msi_notify(&d->pci, 0); 280 } 281 } else { 282 pci_set_irq(&d->pci, level); 283 } 284 } 285 286 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 287 { 288 uint32_t cad, nid, data; 289 HDACodecDevice *codec; 290 HDACodecDeviceClass *cdc; 291 292 cad = (verb >> 28) & 0x0f; 293 if (verb & (1 << 27)) { 294 /* indirect node addressing, not specified in HDA 1.0 */ 295 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 296 return -1; 297 } 298 nid = (verb >> 20) & 0x7f; 299 data = verb & 0xfffff; 300 301 codec = hda_codec_find(&d->codecs, cad); 302 if (codec == NULL) { 303 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 304 return -1; 305 } 306 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 307 cdc->command(codec, nid, data); 308 return 0; 309 } 310 311 static void intel_hda_corb_run(IntelHDAState *d) 312 { 313 hwaddr addr; 314 uint32_t rp, verb; 315 316 if (d->ics & ICH6_IRS_BUSY) { 317 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 318 intel_hda_send_command(d, d->icw); 319 return; 320 } 321 322 for (;;) { 323 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 324 dprint(d, 2, "%s: !run\n", __func__); 325 return; 326 } 327 if ((d->corb_rp & 0xff) == d->corb_wp) { 328 dprint(d, 2, "%s: corb ring empty\n", __func__); 329 return; 330 } 331 if (d->rirb_count == d->rirb_cnt) { 332 dprint(d, 2, "%s: rirb count reached\n", __func__); 333 return; 334 } 335 336 rp = (d->corb_rp + 1) & 0xff; 337 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 338 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 339 d->corb_rp = rp; 340 341 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 342 intel_hda_send_command(d, verb); 343 } 344 } 345 346 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 347 { 348 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 349 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 350 hwaddr addr; 351 uint32_t wp, ex; 352 353 if (d->ics & ICH6_IRS_BUSY) { 354 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 355 __func__, response, dev->cad); 356 d->irr = response; 357 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 358 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 359 return; 360 } 361 362 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 363 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 364 return; 365 } 366 367 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 368 wp = (d->rirb_wp + 1) & 0xff; 369 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 370 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 371 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 372 d->rirb_wp = wp; 373 374 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 375 __func__, wp, response, ex); 376 377 d->rirb_count++; 378 if (d->rirb_count == d->rirb_cnt) { 379 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 380 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 381 d->rirb_sts |= ICH6_RBSTS_IRQ; 382 intel_hda_update_irq(d); 383 } 384 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 385 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 386 d->rirb_count, d->rirb_cnt); 387 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 388 d->rirb_sts |= ICH6_RBSTS_IRQ; 389 intel_hda_update_irq(d); 390 } 391 } 392 } 393 394 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 395 uint8_t *buf, uint32_t len) 396 { 397 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 398 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 399 hwaddr addr; 400 uint32_t s, copy, left; 401 IntelHDAStream *st; 402 bool irq = false; 403 404 st = output ? d->st + 4 : d->st; 405 for (s = 0; s < 4; s++) { 406 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 407 st = st + s; 408 break; 409 } 410 } 411 if (s == 4) { 412 return false; 413 } 414 if (st->bpl == NULL) { 415 return false; 416 } 417 418 left = len; 419 s = st->bentries; 420 while (left > 0 && s-- > 0) { 421 copy = left; 422 if (copy > st->bsize - st->lpib) 423 copy = st->bsize - st->lpib; 424 if (copy > st->bpl[st->be].len - st->bp) 425 copy = st->bpl[st->be].len - st->bp; 426 427 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 428 st->be, st->bp, st->bpl[st->be].len, copy); 429 430 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output, 431 MEMTXATTRS_UNSPECIFIED); 432 st->lpib += copy; 433 st->bp += copy; 434 buf += copy; 435 left -= copy; 436 437 if (st->bpl[st->be].len == st->bp) { 438 /* bpl entry filled */ 439 if (st->bpl[st->be].flags & 0x01) { 440 irq = true; 441 } 442 st->bp = 0; 443 st->be++; 444 if (st->be == st->bentries) { 445 /* bpl wrap around */ 446 st->be = 0; 447 st->lpib = 0; 448 } 449 } 450 } 451 if (d->dp_lbase & 0x01) { 452 s = st - d->st; 453 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 454 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 455 } 456 dprint(d, 3, "dma: --\n"); 457 458 if (irq) { 459 st->ctl |= (1 << 26); /* buffer completion interrupt */ 460 intel_hda_update_irq(d); 461 } 462 return true; 463 } 464 465 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 466 { 467 hwaddr addr; 468 uint8_t buf[16]; 469 uint32_t i; 470 471 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 472 st->bentries = st->lvi +1; 473 g_free(st->bpl); 474 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 475 for (i = 0; i < st->bentries; i++, addr += 16) { 476 pci_dma_read(&d->pci, addr, buf, 16); 477 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 478 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 479 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 480 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 481 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 482 } 483 484 st->bsize = st->cbl; 485 st->lpib = 0; 486 st->be = 0; 487 st->bp = 0; 488 } 489 490 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 491 { 492 BusChild *kid; 493 HDACodecDevice *cdev; 494 495 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 496 DeviceState *qdev = kid->child; 497 HDACodecDeviceClass *cdc; 498 499 cdev = HDA_CODEC_DEVICE(qdev); 500 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 501 if (cdc->stream) { 502 cdc->stream(cdev, stream, running, output); 503 } 504 } 505 } 506 507 /* --------------------------------------------------------------------- */ 508 509 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 510 { 511 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 512 intel_hda_reset(DEVICE(d)); 513 } 514 } 515 516 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 517 { 518 intel_hda_update_irq(d); 519 } 520 521 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 522 { 523 intel_hda_update_irq(d); 524 } 525 526 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 527 { 528 intel_hda_update_irq(d); 529 } 530 531 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 532 { 533 int64_t ns; 534 535 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 536 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 537 } 538 539 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 540 { 541 intel_hda_corb_run(d); 542 } 543 544 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 545 { 546 intel_hda_corb_run(d); 547 } 548 549 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 550 { 551 if (d->rirb_wp & ICH6_RIRBWP_RST) { 552 d->rirb_wp = 0; 553 } 554 } 555 556 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 557 { 558 intel_hda_update_irq(d); 559 560 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 561 /* cleared ICH6_RBSTS_IRQ */ 562 d->rirb_count = 0; 563 intel_hda_corb_run(d); 564 } 565 } 566 567 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 568 { 569 if (d->ics & ICH6_IRS_BUSY) { 570 intel_hda_corb_run(d); 571 } 572 } 573 574 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 575 { 576 bool output = reg->stream >= 4; 577 IntelHDAStream *st = d->st + reg->stream; 578 579 if (st->ctl & 0x01) { 580 /* reset */ 581 dprint(d, 1, "st #%d: reset\n", reg->stream); 582 st->ctl = SD_STS_FIFO_READY << 24; 583 } 584 if ((st->ctl & 0x02) != (old & 0x02)) { 585 uint32_t stnr = (st->ctl >> 20) & 0x0f; 586 /* run bit flipped */ 587 if (st->ctl & 0x02) { 588 /* start */ 589 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 590 reg->stream, stnr, st->cbl); 591 intel_hda_parse_bdl(d, st); 592 intel_hda_notify_codecs(d, stnr, true, output); 593 } else { 594 /* stop */ 595 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 596 intel_hda_notify_codecs(d, stnr, false, output); 597 } 598 } 599 intel_hda_update_irq(d); 600 } 601 602 /* --------------------------------------------------------------------- */ 603 604 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 605 606 static const struct IntelHDAReg regtab[] = { 607 /* global */ 608 [ ICH6_REG_GCAP ] = { 609 .name = "GCAP", 610 .size = 2, 611 .reset = 0x4401, 612 }, 613 [ ICH6_REG_VMIN ] = { 614 .name = "VMIN", 615 .size = 1, 616 }, 617 [ ICH6_REG_VMAJ ] = { 618 .name = "VMAJ", 619 .size = 1, 620 .reset = 1, 621 }, 622 [ ICH6_REG_OUTPAY ] = { 623 .name = "OUTPAY", 624 .size = 2, 625 .reset = 0x3c, 626 }, 627 [ ICH6_REG_INPAY ] = { 628 .name = "INPAY", 629 .size = 2, 630 .reset = 0x1d, 631 }, 632 [ ICH6_REG_GCTL ] = { 633 .name = "GCTL", 634 .size = 4, 635 .wmask = 0x0103, 636 .offset = offsetof(IntelHDAState, g_ctl), 637 .whandler = intel_hda_set_g_ctl, 638 }, 639 [ ICH6_REG_WAKEEN ] = { 640 .name = "WAKEEN", 641 .size = 2, 642 .wmask = 0x7fff, 643 .offset = offsetof(IntelHDAState, wake_en), 644 .whandler = intel_hda_set_wake_en, 645 }, 646 [ ICH6_REG_STATESTS ] = { 647 .name = "STATESTS", 648 .size = 2, 649 .wmask = 0x7fff, 650 .wclear = 0x7fff, 651 .offset = offsetof(IntelHDAState, state_sts), 652 .whandler = intel_hda_set_state_sts, 653 }, 654 655 /* interrupts */ 656 [ ICH6_REG_INTCTL ] = { 657 .name = "INTCTL", 658 .size = 4, 659 .wmask = 0xc00000ff, 660 .offset = offsetof(IntelHDAState, int_ctl), 661 .whandler = intel_hda_set_int_ctl, 662 }, 663 [ ICH6_REG_INTSTS ] = { 664 .name = "INTSTS", 665 .size = 4, 666 .wmask = 0xc00000ff, 667 .wclear = 0xc00000ff, 668 .offset = offsetof(IntelHDAState, int_sts), 669 }, 670 671 /* misc */ 672 [ ICH6_REG_WALLCLK ] = { 673 .name = "WALLCLK", 674 .size = 4, 675 .offset = offsetof(IntelHDAState, wall_clk), 676 .rhandler = intel_hda_get_wall_clk, 677 }, 678 679 /* dma engine */ 680 [ ICH6_REG_CORBLBASE ] = { 681 .name = "CORBLBASE", 682 .size = 4, 683 .wmask = 0xffffff80, 684 .offset = offsetof(IntelHDAState, corb_lbase), 685 }, 686 [ ICH6_REG_CORBUBASE ] = { 687 .name = "CORBUBASE", 688 .size = 4, 689 .wmask = 0xffffffff, 690 .offset = offsetof(IntelHDAState, corb_ubase), 691 }, 692 [ ICH6_REG_CORBWP ] = { 693 .name = "CORBWP", 694 .size = 2, 695 .wmask = 0xff, 696 .offset = offsetof(IntelHDAState, corb_wp), 697 .whandler = intel_hda_set_corb_wp, 698 }, 699 [ ICH6_REG_CORBRP ] = { 700 .name = "CORBRP", 701 .size = 2, 702 .wmask = 0x80ff, 703 .offset = offsetof(IntelHDAState, corb_rp), 704 }, 705 [ ICH6_REG_CORBCTL ] = { 706 .name = "CORBCTL", 707 .size = 1, 708 .wmask = 0x03, 709 .offset = offsetof(IntelHDAState, corb_ctl), 710 .whandler = intel_hda_set_corb_ctl, 711 }, 712 [ ICH6_REG_CORBSTS ] = { 713 .name = "CORBSTS", 714 .size = 1, 715 .wmask = 0x01, 716 .wclear = 0x01, 717 .offset = offsetof(IntelHDAState, corb_sts), 718 }, 719 [ ICH6_REG_CORBSIZE ] = { 720 .name = "CORBSIZE", 721 .size = 1, 722 .reset = 0x42, 723 .offset = offsetof(IntelHDAState, corb_size), 724 }, 725 [ ICH6_REG_RIRBLBASE ] = { 726 .name = "RIRBLBASE", 727 .size = 4, 728 .wmask = 0xffffff80, 729 .offset = offsetof(IntelHDAState, rirb_lbase), 730 }, 731 [ ICH6_REG_RIRBUBASE ] = { 732 .name = "RIRBUBASE", 733 .size = 4, 734 .wmask = 0xffffffff, 735 .offset = offsetof(IntelHDAState, rirb_ubase), 736 }, 737 [ ICH6_REG_RIRBWP ] = { 738 .name = "RIRBWP", 739 .size = 2, 740 .wmask = 0x8000, 741 .offset = offsetof(IntelHDAState, rirb_wp), 742 .whandler = intel_hda_set_rirb_wp, 743 }, 744 [ ICH6_REG_RINTCNT ] = { 745 .name = "RINTCNT", 746 .size = 2, 747 .wmask = 0xff, 748 .offset = offsetof(IntelHDAState, rirb_cnt), 749 }, 750 [ ICH6_REG_RIRBCTL ] = { 751 .name = "RIRBCTL", 752 .size = 1, 753 .wmask = 0x07, 754 .offset = offsetof(IntelHDAState, rirb_ctl), 755 }, 756 [ ICH6_REG_RIRBSTS ] = { 757 .name = "RIRBSTS", 758 .size = 1, 759 .wmask = 0x05, 760 .wclear = 0x05, 761 .offset = offsetof(IntelHDAState, rirb_sts), 762 .whandler = intel_hda_set_rirb_sts, 763 }, 764 [ ICH6_REG_RIRBSIZE ] = { 765 .name = "RIRBSIZE", 766 .size = 1, 767 .reset = 0x42, 768 .offset = offsetof(IntelHDAState, rirb_size), 769 }, 770 771 [ ICH6_REG_DPLBASE ] = { 772 .name = "DPLBASE", 773 .size = 4, 774 .wmask = 0xffffff81, 775 .offset = offsetof(IntelHDAState, dp_lbase), 776 }, 777 [ ICH6_REG_DPUBASE ] = { 778 .name = "DPUBASE", 779 .size = 4, 780 .wmask = 0xffffffff, 781 .offset = offsetof(IntelHDAState, dp_ubase), 782 }, 783 784 [ ICH6_REG_IC ] = { 785 .name = "ICW", 786 .size = 4, 787 .wmask = 0xffffffff, 788 .offset = offsetof(IntelHDAState, icw), 789 }, 790 [ ICH6_REG_IR ] = { 791 .name = "IRR", 792 .size = 4, 793 .offset = offsetof(IntelHDAState, irr), 794 }, 795 [ ICH6_REG_IRS ] = { 796 .name = "ICS", 797 .size = 2, 798 .wmask = 0x0003, 799 .wclear = 0x0002, 800 .offset = offsetof(IntelHDAState, ics), 801 .whandler = intel_hda_set_ics, 802 }, 803 804 #define HDA_STREAM(_t, _i) \ 805 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 806 .stream = _i, \ 807 .name = _t stringify(_i) " CTL", \ 808 .size = 4, \ 809 .wmask = 0x1cff001f, \ 810 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 811 .whandler = intel_hda_set_st_ctl, \ 812 }, \ 813 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 814 .stream = _i, \ 815 .name = _t stringify(_i) " CTL(stnr)", \ 816 .size = 1, \ 817 .shift = 16, \ 818 .wmask = 0x00ff0000, \ 819 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 820 .whandler = intel_hda_set_st_ctl, \ 821 }, \ 822 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 823 .stream = _i, \ 824 .name = _t stringify(_i) " CTL(sts)", \ 825 .size = 1, \ 826 .shift = 24, \ 827 .wmask = 0x1c000000, \ 828 .wclear = 0x1c000000, \ 829 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 830 .whandler = intel_hda_set_st_ctl, \ 831 .reset = SD_STS_FIFO_READY << 24 \ 832 }, \ 833 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 834 .stream = _i, \ 835 .name = _t stringify(_i) " LPIB", \ 836 .size = 4, \ 837 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 838 }, \ 839 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 840 .stream = _i, \ 841 .name = _t stringify(_i) " CBL", \ 842 .size = 4, \ 843 .wmask = 0xffffffff, \ 844 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 845 }, \ 846 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 847 .stream = _i, \ 848 .name = _t stringify(_i) " LVI", \ 849 .size = 2, \ 850 .wmask = 0x00ff, \ 851 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 852 }, \ 853 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 854 .stream = _i, \ 855 .name = _t stringify(_i) " FIFOS", \ 856 .size = 2, \ 857 .reset = HDA_BUFFER_SIZE, \ 858 }, \ 859 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 860 .stream = _i, \ 861 .name = _t stringify(_i) " FMT", \ 862 .size = 2, \ 863 .wmask = 0x7f7f, \ 864 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 865 }, \ 866 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 867 .stream = _i, \ 868 .name = _t stringify(_i) " BDLPL", \ 869 .size = 4, \ 870 .wmask = 0xffffff80, \ 871 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 872 }, \ 873 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 874 .stream = _i, \ 875 .name = _t stringify(_i) " BDLPU", \ 876 .size = 4, \ 877 .wmask = 0xffffffff, \ 878 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 879 }, \ 880 881 HDA_STREAM("IN", 0) 882 HDA_STREAM("IN", 1) 883 HDA_STREAM("IN", 2) 884 HDA_STREAM("IN", 3) 885 886 HDA_STREAM("OUT", 4) 887 HDA_STREAM("OUT", 5) 888 HDA_STREAM("OUT", 6) 889 HDA_STREAM("OUT", 7) 890 891 }; 892 893 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 894 { 895 const IntelHDAReg *reg; 896 897 if (addr >= ARRAY_SIZE(regtab)) { 898 goto noreg; 899 } 900 reg = regtab+addr; 901 if (reg->name == NULL) { 902 goto noreg; 903 } 904 return reg; 905 906 noreg: 907 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 908 return NULL; 909 } 910 911 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 912 { 913 uint8_t *addr = (void*)d; 914 915 addr += reg->offset; 916 return (uint32_t*)addr; 917 } 918 919 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 920 uint32_t wmask) 921 { 922 uint32_t *addr; 923 uint32_t old; 924 925 if (!reg) { 926 return; 927 } 928 if (!reg->wmask) { 929 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 930 reg->name); 931 return; 932 } 933 934 if (d->debug) { 935 time_t now = time(NULL); 936 if (d->last_write && d->last_reg == reg && d->last_val == val) { 937 d->repeat_count++; 938 if (d->last_sec != now) { 939 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 940 d->last_sec = now; 941 d->repeat_count = 0; 942 } 943 } else { 944 if (d->repeat_count) { 945 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 946 } 947 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 948 d->last_write = 1; 949 d->last_reg = reg; 950 d->last_val = val; 951 d->last_sec = now; 952 d->repeat_count = 0; 953 } 954 } 955 assert(reg->offset != 0); 956 957 addr = intel_hda_reg_addr(d, reg); 958 old = *addr; 959 960 if (reg->shift) { 961 val <<= reg->shift; 962 wmask <<= reg->shift; 963 } 964 wmask &= reg->wmask; 965 *addr &= ~wmask; 966 *addr |= wmask & val; 967 *addr &= ~(val & reg->wclear); 968 969 if (reg->whandler) { 970 reg->whandler(d, reg, old); 971 } 972 } 973 974 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 975 uint32_t rmask) 976 { 977 uint32_t *addr, ret; 978 979 if (!reg) { 980 return 0; 981 } 982 983 if (reg->rhandler) { 984 reg->rhandler(d, reg); 985 } 986 987 if (reg->offset == 0) { 988 /* constant read-only register */ 989 ret = reg->reset; 990 } else { 991 addr = intel_hda_reg_addr(d, reg); 992 ret = *addr; 993 if (reg->shift) { 994 ret >>= reg->shift; 995 } 996 ret &= rmask; 997 } 998 if (d->debug) { 999 time_t now = time(NULL); 1000 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1001 d->repeat_count++; 1002 if (d->last_sec != now) { 1003 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1004 d->last_sec = now; 1005 d->repeat_count = 0; 1006 } 1007 } else { 1008 if (d->repeat_count) { 1009 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1010 } 1011 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1012 d->last_write = 0; 1013 d->last_reg = reg; 1014 d->last_val = ret; 1015 d->last_sec = now; 1016 d->repeat_count = 0; 1017 } 1018 } 1019 return ret; 1020 } 1021 1022 static void intel_hda_regs_reset(IntelHDAState *d) 1023 { 1024 uint32_t *addr; 1025 int i; 1026 1027 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1028 if (regtab[i].name == NULL) { 1029 continue; 1030 } 1031 if (regtab[i].offset == 0) { 1032 continue; 1033 } 1034 addr = intel_hda_reg_addr(d, regtab + i); 1035 *addr = regtab[i].reset; 1036 } 1037 } 1038 1039 /* --------------------------------------------------------------------- */ 1040 1041 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1042 unsigned size) 1043 { 1044 IntelHDAState *d = opaque; 1045 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1046 1047 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1048 } 1049 1050 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1051 { 1052 IntelHDAState *d = opaque; 1053 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1054 1055 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1056 } 1057 1058 static const MemoryRegionOps intel_hda_mmio_ops = { 1059 .read = intel_hda_mmio_read, 1060 .write = intel_hda_mmio_write, 1061 .impl = { 1062 .min_access_size = 1, 1063 .max_access_size = 4, 1064 }, 1065 .endianness = DEVICE_NATIVE_ENDIAN, 1066 }; 1067 1068 /* --------------------------------------------------------------------- */ 1069 1070 static void intel_hda_reset(DeviceState *dev) 1071 { 1072 BusChild *kid; 1073 IntelHDAState *d = INTEL_HDA(dev); 1074 HDACodecDevice *cdev; 1075 1076 intel_hda_regs_reset(d); 1077 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1078 1079 /* reset codecs */ 1080 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1081 DeviceState *qdev = kid->child; 1082 cdev = HDA_CODEC_DEVICE(qdev); 1083 device_legacy_reset(DEVICE(cdev)); 1084 d->state_sts |= (1 << cdev->cad); 1085 } 1086 intel_hda_update_irq(d); 1087 } 1088 1089 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1090 { 1091 IntelHDAState *d = INTEL_HDA(pci); 1092 uint8_t *conf = d->pci.config; 1093 Error *err = NULL; 1094 int ret; 1095 1096 d->name = object_get_typename(OBJECT(d)); 1097 1098 pci_config_set_interrupt_pin(conf, 1); 1099 1100 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1101 conf[0x40] = 0x01; 1102 1103 if (d->msi != ON_OFF_AUTO_OFF) { 1104 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1105 1, true, false, &err); 1106 /* Any error other than -ENOTSUP(board's MSI support is broken) 1107 * is a programming error */ 1108 assert(!ret || ret == -ENOTSUP); 1109 if (ret && d->msi == ON_OFF_AUTO_ON) { 1110 /* Can't satisfy user's explicit msi=on request, fail */ 1111 error_append_hint(&err, "You have to use msi=auto (default) or " 1112 "msi=off with this machine type.\n"); 1113 error_propagate(errp, err); 1114 return; 1115 } 1116 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1117 /* With msi=auto, we fall back to MSI off silently */ 1118 error_free(err); 1119 } 1120 1121 memory_region_init(&d->container, OBJECT(d), 1122 "intel-hda-container", 0x4000); 1123 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1124 "intel-hda", 0x2000); 1125 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); 1126 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", 1127 &d->mmio, 0, 0x2000); 1128 memory_region_add_subregion(&d->container, 0x2000, &d->alias); 1129 pci_register_bar(&d->pci, 0, 0, &d->container); 1130 1131 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1132 intel_hda_response, intel_hda_xfer); 1133 } 1134 1135 static void intel_hda_exit(PCIDevice *pci) 1136 { 1137 IntelHDAState *d = INTEL_HDA(pci); 1138 1139 msi_uninit(&d->pci); 1140 } 1141 1142 static int intel_hda_post_load(void *opaque, int version) 1143 { 1144 IntelHDAState* d = opaque; 1145 int i; 1146 1147 dprint(d, 1, "%s\n", __func__); 1148 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1149 if (d->st[i].ctl & 0x02) { 1150 intel_hda_parse_bdl(d, &d->st[i]); 1151 } 1152 } 1153 intel_hda_update_irq(d); 1154 return 0; 1155 } 1156 1157 static const VMStateDescription vmstate_intel_hda_stream = { 1158 .name = "intel-hda-stream", 1159 .version_id = 1, 1160 .fields = (VMStateField[]) { 1161 VMSTATE_UINT32(ctl, IntelHDAStream), 1162 VMSTATE_UINT32(lpib, IntelHDAStream), 1163 VMSTATE_UINT32(cbl, IntelHDAStream), 1164 VMSTATE_UINT32(lvi, IntelHDAStream), 1165 VMSTATE_UINT32(fmt, IntelHDAStream), 1166 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1167 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1168 VMSTATE_END_OF_LIST() 1169 } 1170 }; 1171 1172 static const VMStateDescription vmstate_intel_hda = { 1173 .name = "intel-hda", 1174 .version_id = 1, 1175 .post_load = intel_hda_post_load, 1176 .fields = (VMStateField[]) { 1177 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1178 1179 /* registers */ 1180 VMSTATE_UINT32(g_ctl, IntelHDAState), 1181 VMSTATE_UINT32(wake_en, IntelHDAState), 1182 VMSTATE_UINT32(state_sts, IntelHDAState), 1183 VMSTATE_UINT32(int_ctl, IntelHDAState), 1184 VMSTATE_UINT32(int_sts, IntelHDAState), 1185 VMSTATE_UINT32(wall_clk, IntelHDAState), 1186 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1187 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1188 VMSTATE_UINT32(corb_rp, IntelHDAState), 1189 VMSTATE_UINT32(corb_wp, IntelHDAState), 1190 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1191 VMSTATE_UINT32(corb_sts, IntelHDAState), 1192 VMSTATE_UINT32(corb_size, IntelHDAState), 1193 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1194 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1195 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1196 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1197 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1198 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1199 VMSTATE_UINT32(rirb_size, IntelHDAState), 1200 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1201 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1202 VMSTATE_UINT32(icw, IntelHDAState), 1203 VMSTATE_UINT32(irr, IntelHDAState), 1204 VMSTATE_UINT32(ics, IntelHDAState), 1205 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1206 vmstate_intel_hda_stream, 1207 IntelHDAStream), 1208 1209 /* additional state info */ 1210 VMSTATE_UINT32(rirb_count, IntelHDAState), 1211 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1212 1213 VMSTATE_END_OF_LIST() 1214 } 1215 }; 1216 1217 static Property intel_hda_properties[] = { 1218 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1219 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1220 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1221 DEFINE_PROP_END_OF_LIST(), 1222 }; 1223 1224 static void intel_hda_class_init(ObjectClass *klass, void *data) 1225 { 1226 DeviceClass *dc = DEVICE_CLASS(klass); 1227 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1228 1229 k->realize = intel_hda_realize; 1230 k->exit = intel_hda_exit; 1231 k->vendor_id = PCI_VENDOR_ID_INTEL; 1232 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1233 dc->reset = intel_hda_reset; 1234 dc->vmsd = &vmstate_intel_hda; 1235 device_class_set_props(dc, intel_hda_properties); 1236 } 1237 1238 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1239 { 1240 DeviceClass *dc = DEVICE_CLASS(klass); 1241 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1242 1243 k->device_id = 0x2668; 1244 k->revision = 1; 1245 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1246 dc->desc = "Intel HD Audio Controller (ich6)"; 1247 } 1248 1249 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1250 { 1251 DeviceClass *dc = DEVICE_CLASS(klass); 1252 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1253 1254 k->device_id = 0x293e; 1255 k->revision = 3; 1256 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1257 dc->desc = "Intel HD Audio Controller (ich9)"; 1258 } 1259 1260 static const TypeInfo intel_hda_info = { 1261 .name = TYPE_INTEL_HDA_GENERIC, 1262 .parent = TYPE_PCI_DEVICE, 1263 .instance_size = sizeof(IntelHDAState), 1264 .class_init = intel_hda_class_init, 1265 .abstract = true, 1266 .interfaces = (InterfaceInfo[]) { 1267 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1268 { }, 1269 }, 1270 }; 1271 1272 static const TypeInfo intel_hda_info_ich6 = { 1273 .name = "intel-hda", 1274 .parent = TYPE_INTEL_HDA_GENERIC, 1275 .class_init = intel_hda_class_init_ich6, 1276 }; 1277 1278 static const TypeInfo intel_hda_info_ich9 = { 1279 .name = "ich9-intel-hda", 1280 .parent = TYPE_INTEL_HDA_GENERIC, 1281 .class_init = intel_hda_class_init_ich9, 1282 }; 1283 1284 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1285 { 1286 DeviceClass *k = DEVICE_CLASS(klass); 1287 k->realize = hda_codec_dev_realize; 1288 k->unrealize = hda_codec_dev_unrealize; 1289 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1290 k->bus_type = TYPE_HDA_BUS; 1291 device_class_set_props(k, hda_props); 1292 } 1293 1294 static const TypeInfo hda_codec_device_type_info = { 1295 .name = TYPE_HDA_CODEC_DEVICE, 1296 .parent = TYPE_DEVICE, 1297 .instance_size = sizeof(HDACodecDevice), 1298 .abstract = true, 1299 .class_size = sizeof(HDACodecDeviceClass), 1300 .class_init = hda_codec_device_class_init, 1301 }; 1302 1303 /* 1304 * create intel hda controller with codec attached to it, 1305 * so '-soundhw hda' works. 1306 */ 1307 static int intel_hda_and_codec_init(PCIBus *bus) 1308 { 1309 DeviceState *controller; 1310 BusState *hdabus; 1311 DeviceState *codec; 1312 1313 warn_report("'-soundhw hda' is deprecated, " 1314 "please use '-device intel-hda -device hda-duplex' instead"); 1315 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1316 hdabus = QLIST_FIRST(&controller->child_bus); 1317 codec = qdev_new("hda-duplex"); 1318 qdev_realize_and_unref(codec, hdabus, &error_fatal); 1319 return 0; 1320 } 1321 1322 static void intel_hda_register_types(void) 1323 { 1324 type_register_static(&hda_codec_bus_info); 1325 type_register_static(&intel_hda_info); 1326 type_register_static(&intel_hda_info_ich6); 1327 type_register_static(&intel_hda_info_ich9); 1328 type_register_static(&hda_codec_device_type_info); 1329 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1330 } 1331 1332 type_init(intel_hda_register_types) 1333