1 /* 2 * QEMU ES1370 emulation 3 * 4 * Copyright (c) 2005 Vassili Karpov (malc) 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* #define DEBUG_ES1370 */ 26 /* #define VERBOSE_ES1370 */ 27 #define SILENT_ES1370 28 29 #include "qemu/osdep.h" 30 #include "hw/hw.h" 31 #include "hw/audio/audio.h" 32 #include "audio/audio.h" 33 #include "hw/pci/pci.h" 34 #include "sysemu/dma.h" 35 36 /* Missing stuff: 37 SCTRL_P[12](END|ST)INC 38 SCTRL_P1SCTRLD 39 SCTRL_P2DACSEN 40 CTRL_DAC_SYNC 41 MIDI 42 non looped mode 43 surely more 44 */ 45 46 /* 47 Following macros and samplerate array were copied verbatim from 48 Linux kernel 2.4.30: drivers/sound/es1370.c 49 50 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch) 51 */ 52 53 /* Start blatant GPL violation */ 54 55 #define ES1370_REG_CONTROL 0x00 56 #define ES1370_REG_STATUS 0x04 57 #define ES1370_REG_UART_DATA 0x08 58 #define ES1370_REG_UART_STATUS 0x09 59 #define ES1370_REG_UART_CONTROL 0x09 60 #define ES1370_REG_UART_TEST 0x0a 61 #define ES1370_REG_MEMPAGE 0x0c 62 #define ES1370_REG_CODEC 0x10 63 #define ES1370_REG_SERIAL_CONTROL 0x20 64 #define ES1370_REG_DAC1_SCOUNT 0x24 65 #define ES1370_REG_DAC2_SCOUNT 0x28 66 #define ES1370_REG_ADC_SCOUNT 0x2c 67 68 #define ES1370_REG_DAC1_FRAMEADR 0xc30 69 #define ES1370_REG_DAC1_FRAMECNT 0xc34 70 #define ES1370_REG_DAC2_FRAMEADR 0xc38 71 #define ES1370_REG_DAC2_FRAMECNT 0xc3c 72 #define ES1370_REG_ADC_FRAMEADR 0xd30 73 #define ES1370_REG_ADC_FRAMECNT 0xd34 74 #define ES1370_REG_PHANTOM_FRAMEADR 0xd38 75 #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c 76 77 static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 }; 78 79 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2) 80 #define DAC2_DIVTOSR(x) (1411200/((x)+2)) 81 82 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */ 83 #define CTRL_XCTL1 0x40000000 /* electret mic bias */ 84 #define CTRL_OPEN 0x20000000 /* no function, can be read and written */ 85 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */ 86 #define CTRL_SH_PCLKDIV 16 87 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */ 88 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */ 89 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */ 90 #define CTRL_SH_WTSRSEL 12 91 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */ 92 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */ 93 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */ 94 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */ 95 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */ 96 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */ 97 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */ 98 #define CTRL_ADC_EN 0x00000010 /* enable ADC */ 99 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */ 100 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */ 101 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */ 102 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */ 103 104 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */ 105 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */ 106 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */ 107 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */ 108 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */ 109 #define STAT_SH_VC 5 110 #define STAT_MCCB 0x00000010 /* CCB int pending */ 111 #define STAT_UART 0x00000008 /* UART int pending */ 112 #define STAT_DAC1 0x00000004 /* DAC1 int pending */ 113 #define STAT_DAC2 0x00000002 /* DAC2 int pending */ 114 #define STAT_ADC 0x00000001 /* ADC int pending */ 115 116 #define USTAT_RXINT 0x80 /* UART rx int pending */ 117 #define USTAT_TXINT 0x04 /* UART tx int pending */ 118 #define USTAT_TXRDY 0x02 /* UART tx ready */ 119 #define USTAT_RXRDY 0x01 /* UART rx ready */ 120 121 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */ 122 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */ 123 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */ 124 #define UCTRL_CNTRL 0x03 /* control field */ 125 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */ 126 127 #define SCTRL_P2ENDINC 0x00380000 /* */ 128 #define SCTRL_SH_P2ENDINC 19 129 #define SCTRL_P2STINC 0x00070000 /* */ 130 #define SCTRL_SH_P2STINC 16 131 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */ 132 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */ 133 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */ 134 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */ 135 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */ 136 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */ 137 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */ 138 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */ 139 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */ 140 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */ 141 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */ 142 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */ 143 #define SCTRL_R1FMT 0x00000030 /* format mask */ 144 #define SCTRL_SH_R1FMT 4 145 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */ 146 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */ 147 #define SCTRL_P2FMT 0x0000000c /* format mask */ 148 #define SCTRL_SH_P2FMT 2 149 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */ 150 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */ 151 #define SCTRL_P1FMT 0x00000003 /* format mask */ 152 #define SCTRL_SH_P1FMT 0 153 154 /* End blatant GPL violation */ 155 156 #define NB_CHANNELS 3 157 #define DAC1_CHANNEL 0 158 #define DAC2_CHANNEL 1 159 #define ADC_CHANNEL 2 160 161 static void es1370_dac1_callback (void *opaque, int free); 162 static void es1370_dac2_callback (void *opaque, int free); 163 static void es1370_adc_callback (void *opaque, int avail); 164 165 #ifdef DEBUG_ES1370 166 167 #define ldebug(...) AUD_log ("es1370", __VA_ARGS__) 168 169 static void print_ctl (uint32_t val) 170 { 171 char buf[1024]; 172 173 buf[0] = '\0'; 174 #define a(n) if (val & CTRL_##n) strcat (buf, " "#n) 175 a (ADC_STOP); 176 a (XCTL1); 177 a (OPEN); 178 a (MSFMTSEL); 179 a (M_SBB); 180 a (DAC_SYNC); 181 a (CCB_INTRM); 182 a (M_CB); 183 a (XCTL0); 184 a (BREQ); 185 a (DAC1_EN); 186 a (DAC2_EN); 187 a (ADC_EN); 188 a (UART_EN); 189 a (JYSTK_EN); 190 a (CDC_EN); 191 a (SERR_DIS); 192 #undef a 193 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n", 194 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV, 195 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV), 196 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL], 197 buf); 198 } 199 200 static void print_sctl (uint32_t val) 201 { 202 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"}; 203 char buf[1024]; 204 205 buf[0] = '\0'; 206 207 #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n) 208 #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n) 209 b (R1LOOPSEL); 210 b (P2LOOPSEL); 211 b (P1LOOPSEL); 212 a (P2PAUSE); 213 a (P1PAUSE); 214 a (R1INTEN); 215 a (P2INTEN); 216 a (P1INTEN); 217 a (P1SCTRLD); 218 a (P2DACSEN); 219 if (buf[0]) { 220 strcat (buf, "\n "); 221 } 222 else { 223 buf[0] = ' '; 224 buf[1] = '\0'; 225 } 226 #undef b 227 #undef a 228 AUD_log ("es1370", 229 "%s" 230 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n", 231 buf, 232 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC, 233 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC, 234 fmt_names [(val >> SCTRL_SH_R1FMT) & 3], 235 fmt_names [(val >> SCTRL_SH_P2FMT) & 3], 236 fmt_names [(val >> SCTRL_SH_P1FMT) & 3] 237 ); 238 } 239 #else 240 #define ldebug(...) 241 #define print_ctl(...) 242 #define print_sctl(...) 243 #endif 244 245 #ifdef VERBOSE_ES1370 246 #define dolog(...) AUD_log ("es1370", __VA_ARGS__) 247 #else 248 #define dolog(...) 249 #endif 250 251 #ifndef SILENT_ES1370 252 #define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__) 253 #else 254 #define lwarn(...) 255 #endif 256 257 struct chan { 258 uint32_t shift; 259 uint32_t leftover; 260 uint32_t scount; 261 uint32_t frame_addr; 262 uint32_t frame_cnt; 263 }; 264 265 typedef struct ES1370State { 266 PCIDevice dev; 267 QEMUSoundCard card; 268 MemoryRegion io; 269 struct chan chan[NB_CHANNELS]; 270 SWVoiceOut *dac_voice[2]; 271 SWVoiceIn *adc_voice; 272 273 uint32_t ctl; 274 uint32_t status; 275 uint32_t mempage; 276 uint32_t codec; 277 uint32_t sctl; 278 } ES1370State; 279 280 struct chan_bits { 281 uint32_t ctl_en; 282 uint32_t stat_int; 283 uint32_t sctl_pause; 284 uint32_t sctl_inten; 285 uint32_t sctl_fmt; 286 uint32_t sctl_sh_fmt; 287 uint32_t sctl_loopsel; 288 void (*calc_freq) (ES1370State *s, uint32_t ctl, 289 uint32_t *old_freq, uint32_t *new_freq); 290 }; 291 292 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl, 293 uint32_t *old_freq, uint32_t *new_freq); 294 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl, 295 uint32_t *old_freq, 296 uint32_t *new_freq); 297 298 static const struct chan_bits es1370_chan_bits[] = { 299 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN, 300 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL, 301 es1370_dac1_calc_freq}, 302 303 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN, 304 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL, 305 es1370_dac2_and_adc_calc_freq}, 306 307 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN, 308 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL, 309 es1370_dac2_and_adc_calc_freq} 310 }; 311 312 static void es1370_update_status (ES1370State *s, uint32_t new_status) 313 { 314 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC); 315 316 if (level) { 317 s->status = new_status | STAT_INTR; 318 } 319 else { 320 s->status = new_status & ~STAT_INTR; 321 } 322 pci_set_irq(&s->dev, !!level); 323 } 324 325 static void es1370_reset (ES1370State *s) 326 { 327 size_t i; 328 329 s->ctl = 1; 330 s->status = 0x60; 331 s->mempage = 0; 332 s->codec = 0; 333 s->sctl = 0; 334 335 for (i = 0; i < NB_CHANNELS; ++i) { 336 struct chan *d = &s->chan[i]; 337 d->scount = 0; 338 d->leftover = 0; 339 if (i == ADC_CHANNEL) { 340 AUD_close_in (&s->card, s->adc_voice); 341 s->adc_voice = NULL; 342 } 343 else { 344 AUD_close_out (&s->card, s->dac_voice[i]); 345 s->dac_voice[i] = NULL; 346 } 347 } 348 pci_irq_deassert(&s->dev); 349 } 350 351 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl) 352 { 353 uint32_t new_status = s->status; 354 355 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) { 356 new_status &= ~STAT_DAC1; 357 } 358 359 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) { 360 new_status &= ~STAT_DAC2; 361 } 362 363 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) { 364 new_status &= ~STAT_ADC; 365 } 366 367 if (new_status != s->status) { 368 es1370_update_status (s, new_status); 369 } 370 } 371 372 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl, 373 uint32_t *old_freq, uint32_t *new_freq) 374 375 { 376 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL]; 377 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL]; 378 } 379 380 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl, 381 uint32_t *old_freq, 382 uint32_t *new_freq) 383 384 { 385 uint32_t old_pclkdiv, new_pclkdiv; 386 387 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV; 388 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV; 389 *new_freq = DAC2_DIVTOSR (new_pclkdiv); 390 *old_freq = DAC2_DIVTOSR (old_pclkdiv); 391 } 392 393 static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl) 394 { 395 size_t i; 396 uint32_t old_freq, new_freq, old_fmt, new_fmt; 397 398 for (i = 0; i < NB_CHANNELS; ++i) { 399 struct chan *d = &s->chan[i]; 400 const struct chan_bits *b = &es1370_chan_bits[i]; 401 402 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt; 403 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt; 404 405 b->calc_freq (s, ctl, &old_freq, &new_freq); 406 407 if ((old_fmt != new_fmt) || (old_freq != new_freq)) { 408 d->shift = (new_fmt & 1) + (new_fmt >> 1); 409 ldebug ("channel %zu, freq = %d, nchannels %d, fmt %d, shift %d\n", 410 i, 411 new_freq, 412 1 << (new_fmt & 1), 413 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8, 414 d->shift); 415 if (new_freq) { 416 struct audsettings as; 417 418 as.freq = new_freq; 419 as.nchannels = 1 << (new_fmt & 1); 420 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8; 421 as.endianness = 0; 422 423 if (i == ADC_CHANNEL) { 424 s->adc_voice = 425 AUD_open_in ( 426 &s->card, 427 s->adc_voice, 428 "es1370.adc", 429 s, 430 es1370_adc_callback, 431 &as 432 ); 433 } 434 else { 435 s->dac_voice[i] = 436 AUD_open_out ( 437 &s->card, 438 s->dac_voice[i], 439 i ? "es1370.dac2" : "es1370.dac1", 440 s, 441 i ? es1370_dac2_callback : es1370_dac1_callback, 442 &as 443 ); 444 } 445 } 446 } 447 448 if (((ctl ^ s->ctl) & b->ctl_en) 449 || ((sctl ^ s->sctl) & b->sctl_pause)) { 450 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause); 451 452 if (i == ADC_CHANNEL) { 453 AUD_set_active_in (s->adc_voice, on); 454 } 455 else { 456 AUD_set_active_out (s->dac_voice[i], on); 457 } 458 } 459 } 460 461 s->ctl = ctl; 462 s->sctl = sctl; 463 } 464 465 static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr) 466 { 467 addr &= 0xff; 468 if (addr >= 0x30 && addr <= 0x3f) 469 addr |= s->mempage << 8; 470 return addr; 471 } 472 473 static void es1370_writeb(void *opaque, uint32_t addr, uint32_t val) 474 { 475 ES1370State *s = opaque; 476 uint32_t shift, mask; 477 478 addr = es1370_fixup (s, addr); 479 480 switch (addr) { 481 case ES1370_REG_CONTROL: 482 case ES1370_REG_CONTROL + 1: 483 case ES1370_REG_CONTROL + 2: 484 case ES1370_REG_CONTROL + 3: 485 shift = (addr - ES1370_REG_CONTROL) << 3; 486 mask = 0xff << shift; 487 val = (s->ctl & ~mask) | ((val & 0xff) << shift); 488 es1370_update_voices (s, val, s->sctl); 489 print_ctl (val); 490 break; 491 case ES1370_REG_MEMPAGE: 492 s->mempage = val; 493 break; 494 case ES1370_REG_SERIAL_CONTROL: 495 case ES1370_REG_SERIAL_CONTROL + 1: 496 case ES1370_REG_SERIAL_CONTROL + 2: 497 case ES1370_REG_SERIAL_CONTROL + 3: 498 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3; 499 mask = 0xff << shift; 500 val = (s->sctl & ~mask) | ((val & 0xff) << shift); 501 es1370_maybe_lower_irq (s, val); 502 es1370_update_voices (s, s->ctl, val); 503 print_sctl (val); 504 break; 505 default: 506 lwarn ("writeb %#x <- %#x\n", addr, val); 507 break; 508 } 509 } 510 511 static void es1370_writew(void *opaque, uint32_t addr, uint32_t val) 512 { 513 ES1370State *s = opaque; 514 addr = es1370_fixup (s, addr); 515 uint32_t shift, mask; 516 struct chan *d = &s->chan[0]; 517 518 switch (addr) { 519 case ES1370_REG_CODEC: 520 dolog ("ignored codec write address %#x, data %#x\n", 521 (val >> 8) & 0xff, val & 0xff); 522 s->codec = val; 523 break; 524 525 case ES1370_REG_CONTROL: 526 case ES1370_REG_CONTROL + 2: 527 shift = (addr != ES1370_REG_CONTROL) << 4; 528 mask = 0xffff << shift; 529 val = (s->ctl & ~mask) | ((val & 0xffff) << shift); 530 es1370_update_voices (s, val, s->sctl); 531 print_ctl (val); 532 break; 533 534 case ES1370_REG_ADC_SCOUNT: 535 d++; 536 case ES1370_REG_DAC2_SCOUNT: 537 d++; 538 case ES1370_REG_DAC1_SCOUNT: 539 d->scount = (d->scount & ~0xffff) | (val & 0xffff); 540 break; 541 542 default: 543 lwarn ("writew %#x <- %#x\n", addr, val); 544 break; 545 } 546 } 547 548 static void es1370_writel(void *opaque, uint32_t addr, uint32_t val) 549 { 550 ES1370State *s = opaque; 551 struct chan *d = &s->chan[0]; 552 553 addr = es1370_fixup (s, addr); 554 555 switch (addr) { 556 case ES1370_REG_CONTROL: 557 es1370_update_voices (s, val, s->sctl); 558 print_ctl (val); 559 break; 560 561 case ES1370_REG_MEMPAGE: 562 s->mempage = val & 0xf; 563 break; 564 565 case ES1370_REG_SERIAL_CONTROL: 566 es1370_maybe_lower_irq (s, val); 567 es1370_update_voices (s, s->ctl, val); 568 print_sctl (val); 569 break; 570 571 case ES1370_REG_ADC_SCOUNT: 572 d++; 573 case ES1370_REG_DAC2_SCOUNT: 574 d++; 575 case ES1370_REG_DAC1_SCOUNT: 576 d->scount = (val & 0xffff) | (d->scount & ~0xffff); 577 ldebug ("chan %td CURR_SAMP_CT %d, SAMP_CT %d\n", 578 d - &s->chan[0], val >> 16, (val & 0xffff)); 579 break; 580 581 case ES1370_REG_ADC_FRAMEADR: 582 d++; 583 case ES1370_REG_DAC2_FRAMEADR: 584 d++; 585 case ES1370_REG_DAC1_FRAMEADR: 586 d->frame_addr = val; 587 ldebug ("chan %td frame address %#x\n", d - &s->chan[0], val); 588 break; 589 590 case ES1370_REG_PHANTOM_FRAMECNT: 591 lwarn ("writing to phantom frame count %#x\n", val); 592 break; 593 case ES1370_REG_PHANTOM_FRAMEADR: 594 lwarn ("writing to phantom frame address %#x\n", val); 595 break; 596 597 case ES1370_REG_ADC_FRAMECNT: 598 d++; 599 case ES1370_REG_DAC2_FRAMECNT: 600 d++; 601 case ES1370_REG_DAC1_FRAMECNT: 602 d->frame_cnt = val; 603 d->leftover = 0; 604 ldebug ("chan %td frame count %d, buffer size %d\n", 605 d - &s->chan[0], val >> 16, val & 0xffff); 606 break; 607 608 default: 609 lwarn ("writel %#x <- %#x\n", addr, val); 610 break; 611 } 612 } 613 614 static uint32_t es1370_readb(void *opaque, uint32_t addr) 615 { 616 ES1370State *s = opaque; 617 uint32_t val; 618 619 addr = es1370_fixup (s, addr); 620 621 switch (addr) { 622 case 0x1b: /* Legacy */ 623 lwarn ("Attempt to read from legacy register\n"); 624 val = 5; 625 break; 626 case ES1370_REG_MEMPAGE: 627 val = s->mempage; 628 break; 629 case ES1370_REG_CONTROL + 0: 630 case ES1370_REG_CONTROL + 1: 631 case ES1370_REG_CONTROL + 2: 632 case ES1370_REG_CONTROL + 3: 633 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3); 634 break; 635 case ES1370_REG_STATUS + 0: 636 case ES1370_REG_STATUS + 1: 637 case ES1370_REG_STATUS + 2: 638 case ES1370_REG_STATUS + 3: 639 val = s->status >> ((addr - ES1370_REG_STATUS) << 3); 640 break; 641 default: 642 val = ~0; 643 lwarn ("readb %#x -> %#x\n", addr, val); 644 break; 645 } 646 return val; 647 } 648 649 static uint32_t es1370_readw(void *opaque, uint32_t addr) 650 { 651 ES1370State *s = opaque; 652 struct chan *d = &s->chan[0]; 653 uint32_t val; 654 655 addr = es1370_fixup (s, addr); 656 657 switch (addr) { 658 case ES1370_REG_ADC_SCOUNT + 2: 659 d++; 660 case ES1370_REG_DAC2_SCOUNT + 2: 661 d++; 662 case ES1370_REG_DAC1_SCOUNT + 2: 663 val = d->scount >> 16; 664 break; 665 666 case ES1370_REG_ADC_FRAMECNT: 667 d++; 668 case ES1370_REG_DAC2_FRAMECNT: 669 d++; 670 case ES1370_REG_DAC1_FRAMECNT: 671 val = d->frame_cnt & 0xffff; 672 break; 673 674 case ES1370_REG_ADC_FRAMECNT + 2: 675 d++; 676 case ES1370_REG_DAC2_FRAMECNT + 2: 677 d++; 678 case ES1370_REG_DAC1_FRAMECNT + 2: 679 val = d->frame_cnt >> 16; 680 break; 681 682 default: 683 val = ~0; 684 lwarn ("readw %#x -> %#x\n", addr, val); 685 break; 686 } 687 688 return val; 689 } 690 691 static uint32_t es1370_readl(void *opaque, uint32_t addr) 692 { 693 ES1370State *s = opaque; 694 uint32_t val; 695 struct chan *d = &s->chan[0]; 696 697 addr = es1370_fixup (s, addr); 698 699 switch (addr) { 700 case ES1370_REG_CONTROL: 701 val = s->ctl; 702 break; 703 case ES1370_REG_STATUS: 704 val = s->status; 705 break; 706 case ES1370_REG_MEMPAGE: 707 val = s->mempage; 708 break; 709 case ES1370_REG_CODEC: 710 val = s->codec; 711 break; 712 case ES1370_REG_SERIAL_CONTROL: 713 val = s->sctl; 714 break; 715 716 case ES1370_REG_ADC_SCOUNT: 717 d++; 718 case ES1370_REG_DAC2_SCOUNT: 719 d++; 720 case ES1370_REG_DAC1_SCOUNT: 721 val = d->scount; 722 #ifdef DEBUG_ES1370 723 { 724 uint32_t curr_count = d->scount >> 16; 725 uint32_t count = d->scount & 0xffff; 726 727 curr_count <<= d->shift; 728 count <<= d->shift; 729 dolog ("read scount curr %d, total %d\n", curr_count, count); 730 } 731 #endif 732 break; 733 734 case ES1370_REG_ADC_FRAMECNT: 735 d++; 736 case ES1370_REG_DAC2_FRAMECNT: 737 d++; 738 case ES1370_REG_DAC1_FRAMECNT: 739 val = d->frame_cnt; 740 #ifdef DEBUG_ES1370 741 { 742 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2; 743 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2; 744 if (curr > size) { 745 dolog ("read framecnt curr %d, size %d %d\n", curr, size, 746 curr > size); 747 } 748 } 749 #endif 750 break; 751 752 case ES1370_REG_ADC_FRAMEADR: 753 d++; 754 case ES1370_REG_DAC2_FRAMEADR: 755 d++; 756 case ES1370_REG_DAC1_FRAMEADR: 757 val = d->frame_addr; 758 break; 759 760 case ES1370_REG_PHANTOM_FRAMECNT: 761 val = ~0U; 762 lwarn ("reading from phantom frame count\n"); 763 break; 764 case ES1370_REG_PHANTOM_FRAMEADR: 765 val = ~0U; 766 lwarn ("reading from phantom frame address\n"); 767 break; 768 769 default: 770 val = ~0U; 771 lwarn ("readl %#x -> %#x\n", addr, val); 772 break; 773 } 774 return val; 775 } 776 777 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel, 778 int max, int *irq) 779 { 780 uint8_t tmpbuf[4096]; 781 uint32_t addr = d->frame_addr; 782 int sc = d->scount & 0xffff; 783 int csc = d->scount >> 16; 784 int csc_bytes = (csc + 1) << d->shift; 785 int cnt = d->frame_cnt >> 16; 786 int size = d->frame_cnt & 0xffff; 787 int left = ((size - cnt + 1) << 2) + d->leftover; 788 int transferred = 0; 789 int temp = audio_MIN (max, audio_MIN (left, csc_bytes)); 790 int index = d - &s->chan[0]; 791 792 addr += (cnt << 2) + d->leftover; 793 794 if (index == ADC_CHANNEL) { 795 while (temp) { 796 int acquired, to_copy; 797 798 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf)); 799 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy); 800 if (!acquired) 801 break; 802 803 pci_dma_write (&s->dev, addr, tmpbuf, acquired); 804 805 temp -= acquired; 806 addr += acquired; 807 transferred += acquired; 808 } 809 } 810 else { 811 SWVoiceOut *voice = s->dac_voice[index]; 812 813 while (temp) { 814 int copied, to_copy; 815 816 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf)); 817 pci_dma_read (&s->dev, addr, tmpbuf, to_copy); 818 copied = AUD_write (voice, tmpbuf, to_copy); 819 if (!copied) 820 break; 821 temp -= copied; 822 addr += copied; 823 transferred += copied; 824 } 825 } 826 827 if (csc_bytes == transferred) { 828 *irq = 1; 829 d->scount = sc | (sc << 16); 830 ldebug ("sc = %d, rate = %f\n", 831 (sc + 1) << d->shift, 832 (sc + 1) / (double) 44100); 833 } 834 else { 835 *irq = 0; 836 d->scount = sc | (((csc_bytes - transferred - 1) >> d->shift) << 16); 837 } 838 839 cnt += (transferred + d->leftover) >> 2; 840 841 if (s->sctl & loop_sel) { 842 /* Bah, how stupid is that having a 0 represent true value? 843 i just spent few hours on this shit */ 844 AUD_log ("es1370: warning", "non looping mode\n"); 845 } 846 else { 847 d->frame_cnt = size; 848 849 if ((uint32_t) cnt <= d->frame_cnt) 850 d->frame_cnt |= cnt << 16; 851 } 852 853 d->leftover = (transferred + d->leftover) & 3; 854 } 855 856 static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail) 857 { 858 uint32_t new_status = s->status; 859 int max_bytes, irq; 860 struct chan *d = &s->chan[chan]; 861 const struct chan_bits *b = &es1370_chan_bits[chan]; 862 863 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) { 864 return; 865 } 866 867 max_bytes = free_or_avail; 868 max_bytes &= ~((1 << d->shift) - 1); 869 if (!max_bytes) { 870 return; 871 } 872 873 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq); 874 875 if (irq) { 876 if (s->sctl & b->sctl_inten) { 877 new_status |= b->stat_int; 878 } 879 } 880 881 if (new_status != s->status) { 882 es1370_update_status (s, new_status); 883 } 884 } 885 886 static void es1370_dac1_callback (void *opaque, int free) 887 { 888 ES1370State *s = opaque; 889 890 es1370_run_channel (s, DAC1_CHANNEL, free); 891 } 892 893 static void es1370_dac2_callback (void *opaque, int free) 894 { 895 ES1370State *s = opaque; 896 897 es1370_run_channel (s, DAC2_CHANNEL, free); 898 } 899 900 static void es1370_adc_callback (void *opaque, int avail) 901 { 902 ES1370State *s = opaque; 903 904 es1370_run_channel (s, ADC_CHANNEL, avail); 905 } 906 907 static uint64_t es1370_read(void *opaque, hwaddr addr, 908 unsigned size) 909 { 910 switch (size) { 911 case 1: 912 return es1370_readb(opaque, addr); 913 case 2: 914 return es1370_readw(opaque, addr); 915 case 4: 916 return es1370_readl(opaque, addr); 917 default: 918 return -1; 919 } 920 } 921 922 static void es1370_write(void *opaque, hwaddr addr, uint64_t val, 923 unsigned size) 924 { 925 switch (size) { 926 case 1: 927 es1370_writeb(opaque, addr, val); 928 break; 929 case 2: 930 es1370_writew(opaque, addr, val); 931 break; 932 case 4: 933 es1370_writel(opaque, addr, val); 934 break; 935 } 936 } 937 938 static const MemoryRegionOps es1370_io_ops = { 939 .read = es1370_read, 940 .write = es1370_write, 941 .impl = { 942 .min_access_size = 1, 943 .max_access_size = 4, 944 }, 945 .endianness = DEVICE_LITTLE_ENDIAN, 946 }; 947 948 static const VMStateDescription vmstate_es1370_channel = { 949 .name = "es1370_channel", 950 .version_id = 2, 951 .minimum_version_id = 2, 952 .fields = (VMStateField[]) { 953 VMSTATE_UINT32 (shift, struct chan), 954 VMSTATE_UINT32 (leftover, struct chan), 955 VMSTATE_UINT32 (scount, struct chan), 956 VMSTATE_UINT32 (frame_addr, struct chan), 957 VMSTATE_UINT32 (frame_cnt, struct chan), 958 VMSTATE_END_OF_LIST () 959 } 960 }; 961 962 static int es1370_post_load (void *opaque, int version_id) 963 { 964 uint32_t ctl, sctl; 965 ES1370State *s = opaque; 966 size_t i; 967 968 for (i = 0; i < NB_CHANNELS; ++i) { 969 if (i == ADC_CHANNEL) { 970 if (s->adc_voice) { 971 AUD_close_in (&s->card, s->adc_voice); 972 s->adc_voice = NULL; 973 } 974 } 975 else { 976 if (s->dac_voice[i]) { 977 AUD_close_out (&s->card, s->dac_voice[i]); 978 s->dac_voice[i] = NULL; 979 } 980 } 981 } 982 983 ctl = s->ctl; 984 sctl = s->sctl; 985 s->ctl = 0; 986 s->sctl = 0; 987 es1370_update_voices (s, ctl, sctl); 988 return 0; 989 } 990 991 static const VMStateDescription vmstate_es1370 = { 992 .name = "es1370", 993 .version_id = 2, 994 .minimum_version_id = 2, 995 .post_load = es1370_post_load, 996 .fields = (VMStateField[]) { 997 VMSTATE_PCI_DEVICE (dev, ES1370State), 998 VMSTATE_STRUCT_ARRAY (chan, ES1370State, NB_CHANNELS, 2, 999 vmstate_es1370_channel, struct chan), 1000 VMSTATE_UINT32 (ctl, ES1370State), 1001 VMSTATE_UINT32 (status, ES1370State), 1002 VMSTATE_UINT32 (mempage, ES1370State), 1003 VMSTATE_UINT32 (codec, ES1370State), 1004 VMSTATE_UINT32 (sctl, ES1370State), 1005 VMSTATE_END_OF_LIST () 1006 } 1007 }; 1008 1009 static void es1370_on_reset (void *opaque) 1010 { 1011 ES1370State *s = opaque; 1012 es1370_reset (s); 1013 } 1014 1015 static void es1370_realize(PCIDevice *dev, Error **errp) 1016 { 1017 ES1370State *s = DO_UPCAST (ES1370State, dev, dev); 1018 uint8_t *c = s->dev.config; 1019 1020 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_SLOW >> 8; 1021 1022 #if 0 1023 c[PCI_CAPABILITY_LIST] = 0xdc; 1024 c[PCI_INTERRUPT_LINE] = 10; 1025 c[0xdc] = 0x00; 1026 #endif 1027 1028 c[PCI_INTERRUPT_PIN] = 1; 1029 c[PCI_MIN_GNT] = 0x0c; 1030 c[PCI_MAX_LAT] = 0x80; 1031 1032 memory_region_init_io (&s->io, OBJECT(s), &es1370_io_ops, s, "es1370", 256); 1033 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 1034 qemu_register_reset (es1370_on_reset, s); 1035 1036 AUD_register_card ("es1370", &s->card); 1037 es1370_reset (s); 1038 } 1039 1040 static int es1370_init (PCIBus *bus) 1041 { 1042 pci_create_simple (bus, -1, "ES1370"); 1043 return 0; 1044 } 1045 1046 static void es1370_class_init (ObjectClass *klass, void *data) 1047 { 1048 DeviceClass *dc = DEVICE_CLASS (klass); 1049 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass); 1050 1051 k->realize = es1370_realize; 1052 k->vendor_id = PCI_VENDOR_ID_ENSONIQ; 1053 k->device_id = PCI_DEVICE_ID_ENSONIQ_ES1370; 1054 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 1055 k->subsystem_vendor_id = 0x4942; 1056 k->subsystem_id = 0x4c4c; 1057 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1058 dc->desc = "ENSONIQ AudioPCI ES1370"; 1059 dc->vmsd = &vmstate_es1370; 1060 } 1061 1062 static const TypeInfo es1370_info = { 1063 .name = "ES1370", 1064 .parent = TYPE_PCI_DEVICE, 1065 .instance_size = sizeof (ES1370State), 1066 .class_init = es1370_class_init, 1067 }; 1068 1069 static void es1370_register_types (void) 1070 { 1071 type_register_static (&es1370_info); 1072 pci_register_soundhw("es1370", "ENSONIQ AudioPCI ES1370", es1370_init); 1073 } 1074 1075 type_init (es1370_register_types) 1076 1077