1 /* 2 * QEMU ES1370 emulation 3 * 4 * Copyright (c) 2005 Vassili Karpov (malc) 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* #define DEBUG_ES1370 */ 26 /* #define VERBOSE_ES1370 */ 27 #define SILENT_ES1370 28 29 #include "hw/hw.h" 30 #include "hw/audio/audio.h" 31 #include "audio/audio.h" 32 #include "hw/pci/pci.h" 33 #include "sysemu/dma.h" 34 35 /* Missing stuff: 36 SCTRL_P[12](END|ST)INC 37 SCTRL_P1SCTRLD 38 SCTRL_P2DACSEN 39 CTRL_DAC_SYNC 40 MIDI 41 non looped mode 42 surely more 43 */ 44 45 /* 46 Following macros and samplerate array were copied verbatim from 47 Linux kernel 2.4.30: drivers/sound/es1370.c 48 49 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch) 50 */ 51 52 /* Start blatant GPL violation */ 53 54 #define ES1370_REG_CONTROL 0x00 55 #define ES1370_REG_STATUS 0x04 56 #define ES1370_REG_UART_DATA 0x08 57 #define ES1370_REG_UART_STATUS 0x09 58 #define ES1370_REG_UART_CONTROL 0x09 59 #define ES1370_REG_UART_TEST 0x0a 60 #define ES1370_REG_MEMPAGE 0x0c 61 #define ES1370_REG_CODEC 0x10 62 #define ES1370_REG_SERIAL_CONTROL 0x20 63 #define ES1370_REG_DAC1_SCOUNT 0x24 64 #define ES1370_REG_DAC2_SCOUNT 0x28 65 #define ES1370_REG_ADC_SCOUNT 0x2c 66 67 #define ES1370_REG_DAC1_FRAMEADR 0xc30 68 #define ES1370_REG_DAC1_FRAMECNT 0xc34 69 #define ES1370_REG_DAC2_FRAMEADR 0xc38 70 #define ES1370_REG_DAC2_FRAMECNT 0xc3c 71 #define ES1370_REG_ADC_FRAMEADR 0xd30 72 #define ES1370_REG_ADC_FRAMECNT 0xd34 73 #define ES1370_REG_PHANTOM_FRAMEADR 0xd38 74 #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c 75 76 static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 }; 77 78 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2) 79 #define DAC2_DIVTOSR(x) (1411200/((x)+2)) 80 81 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */ 82 #define CTRL_XCTL1 0x40000000 /* electret mic bias */ 83 #define CTRL_OPEN 0x20000000 /* no function, can be read and written */ 84 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */ 85 #define CTRL_SH_PCLKDIV 16 86 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */ 87 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */ 88 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */ 89 #define CTRL_SH_WTSRSEL 12 90 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */ 91 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */ 92 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */ 93 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */ 94 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */ 95 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */ 96 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */ 97 #define CTRL_ADC_EN 0x00000010 /* enable ADC */ 98 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */ 99 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */ 100 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */ 101 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */ 102 103 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */ 104 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */ 105 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */ 106 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */ 107 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */ 108 #define STAT_SH_VC 5 109 #define STAT_MCCB 0x00000010 /* CCB int pending */ 110 #define STAT_UART 0x00000008 /* UART int pending */ 111 #define STAT_DAC1 0x00000004 /* DAC1 int pending */ 112 #define STAT_DAC2 0x00000002 /* DAC2 int pending */ 113 #define STAT_ADC 0x00000001 /* ADC int pending */ 114 115 #define USTAT_RXINT 0x80 /* UART rx int pending */ 116 #define USTAT_TXINT 0x04 /* UART tx int pending */ 117 #define USTAT_TXRDY 0x02 /* UART tx ready */ 118 #define USTAT_RXRDY 0x01 /* UART rx ready */ 119 120 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */ 121 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */ 122 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */ 123 #define UCTRL_CNTRL 0x03 /* control field */ 124 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */ 125 126 #define SCTRL_P2ENDINC 0x00380000 /* */ 127 #define SCTRL_SH_P2ENDINC 19 128 #define SCTRL_P2STINC 0x00070000 /* */ 129 #define SCTRL_SH_P2STINC 16 130 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */ 131 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */ 132 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */ 133 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */ 134 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */ 135 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */ 136 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */ 137 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */ 138 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */ 139 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */ 140 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */ 141 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */ 142 #define SCTRL_R1FMT 0x00000030 /* format mask */ 143 #define SCTRL_SH_R1FMT 4 144 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */ 145 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */ 146 #define SCTRL_P2FMT 0x0000000c /* format mask */ 147 #define SCTRL_SH_P2FMT 2 148 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */ 149 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */ 150 #define SCTRL_P1FMT 0x00000003 /* format mask */ 151 #define SCTRL_SH_P1FMT 0 152 153 /* End blatant GPL violation */ 154 155 #define NB_CHANNELS 3 156 #define DAC1_CHANNEL 0 157 #define DAC2_CHANNEL 1 158 #define ADC_CHANNEL 2 159 160 static void es1370_dac1_callback (void *opaque, int free); 161 static void es1370_dac2_callback (void *opaque, int free); 162 static void es1370_adc_callback (void *opaque, int avail); 163 164 #ifdef DEBUG_ES1370 165 166 #define ldebug(...) AUD_log ("es1370", __VA_ARGS__) 167 168 static void print_ctl (uint32_t val) 169 { 170 char buf[1024]; 171 172 buf[0] = '\0'; 173 #define a(n) if (val & CTRL_##n) strcat (buf, " "#n) 174 a (ADC_STOP); 175 a (XCTL1); 176 a (OPEN); 177 a (MSFMTSEL); 178 a (M_SBB); 179 a (DAC_SYNC); 180 a (CCB_INTRM); 181 a (M_CB); 182 a (XCTL0); 183 a (BREQ); 184 a (DAC1_EN); 185 a (DAC2_EN); 186 a (ADC_EN); 187 a (UART_EN); 188 a (JYSTK_EN); 189 a (CDC_EN); 190 a (SERR_DIS); 191 #undef a 192 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n", 193 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV, 194 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV), 195 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL], 196 buf); 197 } 198 199 static void print_sctl (uint32_t val) 200 { 201 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"}; 202 char buf[1024]; 203 204 buf[0] = '\0'; 205 206 #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n) 207 #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n) 208 b (R1LOOPSEL); 209 b (P2LOOPSEL); 210 b (P1LOOPSEL); 211 a (P2PAUSE); 212 a (P1PAUSE); 213 a (R1INTEN); 214 a (P2INTEN); 215 a (P1INTEN); 216 a (P1SCTRLD); 217 a (P2DACSEN); 218 if (buf[0]) { 219 strcat (buf, "\n "); 220 } 221 else { 222 buf[0] = ' '; 223 buf[1] = '\0'; 224 } 225 #undef b 226 #undef a 227 AUD_log ("es1370", 228 "%s" 229 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n", 230 buf, 231 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC, 232 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC, 233 fmt_names [(val >> SCTRL_SH_R1FMT) & 3], 234 fmt_names [(val >> SCTRL_SH_P2FMT) & 3], 235 fmt_names [(val >> SCTRL_SH_P1FMT) & 3] 236 ); 237 } 238 #else 239 #define ldebug(...) 240 #define print_ctl(...) 241 #define print_sctl(...) 242 #endif 243 244 #ifdef VERBOSE_ES1370 245 #define dolog(...) AUD_log ("es1370", __VA_ARGS__) 246 #else 247 #define dolog(...) 248 #endif 249 250 #ifndef SILENT_ES1370 251 #define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__) 252 #else 253 #define lwarn(...) 254 #endif 255 256 struct chan { 257 uint32_t shift; 258 uint32_t leftover; 259 uint32_t scount; 260 uint32_t frame_addr; 261 uint32_t frame_cnt; 262 }; 263 264 typedef struct ES1370State { 265 PCIDevice dev; 266 QEMUSoundCard card; 267 MemoryRegion io; 268 struct chan chan[NB_CHANNELS]; 269 SWVoiceOut *dac_voice[2]; 270 SWVoiceIn *adc_voice; 271 272 uint32_t ctl; 273 uint32_t status; 274 uint32_t mempage; 275 uint32_t codec; 276 uint32_t sctl; 277 } ES1370State; 278 279 struct chan_bits { 280 uint32_t ctl_en; 281 uint32_t stat_int; 282 uint32_t sctl_pause; 283 uint32_t sctl_inten; 284 uint32_t sctl_fmt; 285 uint32_t sctl_sh_fmt; 286 uint32_t sctl_loopsel; 287 void (*calc_freq) (ES1370State *s, uint32_t ctl, 288 uint32_t *old_freq, uint32_t *new_freq); 289 }; 290 291 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl, 292 uint32_t *old_freq, uint32_t *new_freq); 293 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl, 294 uint32_t *old_freq, 295 uint32_t *new_freq); 296 297 static const struct chan_bits es1370_chan_bits[] = { 298 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN, 299 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL, 300 es1370_dac1_calc_freq}, 301 302 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN, 303 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL, 304 es1370_dac2_and_adc_calc_freq}, 305 306 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN, 307 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL, 308 es1370_dac2_and_adc_calc_freq} 309 }; 310 311 static void es1370_update_status (ES1370State *s, uint32_t new_status) 312 { 313 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC); 314 315 if (level) { 316 s->status = new_status | STAT_INTR; 317 } 318 else { 319 s->status = new_status & ~STAT_INTR; 320 } 321 pci_set_irq(&s->dev, !!level); 322 } 323 324 static void es1370_reset (ES1370State *s) 325 { 326 size_t i; 327 328 s->ctl = 1; 329 s->status = 0x60; 330 s->mempage = 0; 331 s->codec = 0; 332 s->sctl = 0; 333 334 for (i = 0; i < NB_CHANNELS; ++i) { 335 struct chan *d = &s->chan[i]; 336 d->scount = 0; 337 d->leftover = 0; 338 if (i == ADC_CHANNEL) { 339 AUD_close_in (&s->card, s->adc_voice); 340 s->adc_voice = NULL; 341 } 342 else { 343 AUD_close_out (&s->card, s->dac_voice[i]); 344 s->dac_voice[i] = NULL; 345 } 346 } 347 pci_irq_deassert(&s->dev); 348 } 349 350 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl) 351 { 352 uint32_t new_status = s->status; 353 354 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) { 355 new_status &= ~STAT_DAC1; 356 } 357 358 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) { 359 new_status &= ~STAT_DAC2; 360 } 361 362 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) { 363 new_status &= ~STAT_ADC; 364 } 365 366 if (new_status != s->status) { 367 es1370_update_status (s, new_status); 368 } 369 } 370 371 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl, 372 uint32_t *old_freq, uint32_t *new_freq) 373 374 { 375 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL]; 376 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL]; 377 } 378 379 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl, 380 uint32_t *old_freq, 381 uint32_t *new_freq) 382 383 { 384 uint32_t old_pclkdiv, new_pclkdiv; 385 386 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV; 387 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV; 388 *new_freq = DAC2_DIVTOSR (new_pclkdiv); 389 *old_freq = DAC2_DIVTOSR (old_pclkdiv); 390 } 391 392 static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl) 393 { 394 size_t i; 395 uint32_t old_freq, new_freq, old_fmt, new_fmt; 396 397 for (i = 0; i < NB_CHANNELS; ++i) { 398 struct chan *d = &s->chan[i]; 399 const struct chan_bits *b = &es1370_chan_bits[i]; 400 401 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt; 402 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt; 403 404 b->calc_freq (s, ctl, &old_freq, &new_freq); 405 406 if ((old_fmt != new_fmt) || (old_freq != new_freq)) { 407 d->shift = (new_fmt & 1) + (new_fmt >> 1); 408 ldebug ("channel %zu, freq = %d, nchannels %d, fmt %d, shift %d\n", 409 i, 410 new_freq, 411 1 << (new_fmt & 1), 412 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8, 413 d->shift); 414 if (new_freq) { 415 struct audsettings as; 416 417 as.freq = new_freq; 418 as.nchannels = 1 << (new_fmt & 1); 419 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8; 420 as.endianness = 0; 421 422 if (i == ADC_CHANNEL) { 423 s->adc_voice = 424 AUD_open_in ( 425 &s->card, 426 s->adc_voice, 427 "es1370.adc", 428 s, 429 es1370_adc_callback, 430 &as 431 ); 432 } 433 else { 434 s->dac_voice[i] = 435 AUD_open_out ( 436 &s->card, 437 s->dac_voice[i], 438 i ? "es1370.dac2" : "es1370.dac1", 439 s, 440 i ? es1370_dac2_callback : es1370_dac1_callback, 441 &as 442 ); 443 } 444 } 445 } 446 447 if (((ctl ^ s->ctl) & b->ctl_en) 448 || ((sctl ^ s->sctl) & b->sctl_pause)) { 449 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause); 450 451 if (i == ADC_CHANNEL) { 452 AUD_set_active_in (s->adc_voice, on); 453 } 454 else { 455 AUD_set_active_out (s->dac_voice[i], on); 456 } 457 } 458 } 459 460 s->ctl = ctl; 461 s->sctl = sctl; 462 } 463 464 static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr) 465 { 466 addr &= 0xff; 467 if (addr >= 0x30 && addr <= 0x3f) 468 addr |= s->mempage << 8; 469 return addr; 470 } 471 472 static void es1370_writeb(void *opaque, uint32_t addr, uint32_t val) 473 { 474 ES1370State *s = opaque; 475 uint32_t shift, mask; 476 477 addr = es1370_fixup (s, addr); 478 479 switch (addr) { 480 case ES1370_REG_CONTROL: 481 case ES1370_REG_CONTROL + 1: 482 case ES1370_REG_CONTROL + 2: 483 case ES1370_REG_CONTROL + 3: 484 shift = (addr - ES1370_REG_CONTROL) << 3; 485 mask = 0xff << shift; 486 val = (s->ctl & ~mask) | ((val & 0xff) << shift); 487 es1370_update_voices (s, val, s->sctl); 488 print_ctl (val); 489 break; 490 case ES1370_REG_MEMPAGE: 491 s->mempage = val; 492 break; 493 case ES1370_REG_SERIAL_CONTROL: 494 case ES1370_REG_SERIAL_CONTROL + 1: 495 case ES1370_REG_SERIAL_CONTROL + 2: 496 case ES1370_REG_SERIAL_CONTROL + 3: 497 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3; 498 mask = 0xff << shift; 499 val = (s->sctl & ~mask) | ((val & 0xff) << shift); 500 es1370_maybe_lower_irq (s, val); 501 es1370_update_voices (s, s->ctl, val); 502 print_sctl (val); 503 break; 504 default: 505 lwarn ("writeb %#x <- %#x\n", addr, val); 506 break; 507 } 508 } 509 510 static void es1370_writew(void *opaque, uint32_t addr, uint32_t val) 511 { 512 ES1370State *s = opaque; 513 addr = es1370_fixup (s, addr); 514 uint32_t shift, mask; 515 struct chan *d = &s->chan[0]; 516 517 switch (addr) { 518 case ES1370_REG_CODEC: 519 dolog ("ignored codec write address %#x, data %#x\n", 520 (val >> 8) & 0xff, val & 0xff); 521 s->codec = val; 522 break; 523 524 case ES1370_REG_CONTROL: 525 case ES1370_REG_CONTROL + 2: 526 shift = (addr != ES1370_REG_CONTROL) << 4; 527 mask = 0xffff << shift; 528 val = (s->ctl & ~mask) | ((val & 0xffff) << shift); 529 es1370_update_voices (s, val, s->sctl); 530 print_ctl (val); 531 break; 532 533 case ES1370_REG_ADC_SCOUNT: 534 d++; 535 case ES1370_REG_DAC2_SCOUNT: 536 d++; 537 case ES1370_REG_DAC1_SCOUNT: 538 d->scount = (d->scount & ~0xffff) | (val & 0xffff); 539 break; 540 541 default: 542 lwarn ("writew %#x <- %#x\n", addr, val); 543 break; 544 } 545 } 546 547 static void es1370_writel(void *opaque, uint32_t addr, uint32_t val) 548 { 549 ES1370State *s = opaque; 550 struct chan *d = &s->chan[0]; 551 552 addr = es1370_fixup (s, addr); 553 554 switch (addr) { 555 case ES1370_REG_CONTROL: 556 es1370_update_voices (s, val, s->sctl); 557 print_ctl (val); 558 break; 559 560 case ES1370_REG_MEMPAGE: 561 s->mempage = val & 0xf; 562 break; 563 564 case ES1370_REG_SERIAL_CONTROL: 565 es1370_maybe_lower_irq (s, val); 566 es1370_update_voices (s, s->ctl, val); 567 print_sctl (val); 568 break; 569 570 case ES1370_REG_ADC_SCOUNT: 571 d++; 572 case ES1370_REG_DAC2_SCOUNT: 573 d++; 574 case ES1370_REG_DAC1_SCOUNT: 575 d->scount = (val & 0xffff) | (d->scount & ~0xffff); 576 ldebug ("chan %td CURR_SAMP_CT %d, SAMP_CT %d\n", 577 d - &s->chan[0], val >> 16, (val & 0xffff)); 578 break; 579 580 case ES1370_REG_ADC_FRAMEADR: 581 d++; 582 case ES1370_REG_DAC2_FRAMEADR: 583 d++; 584 case ES1370_REG_DAC1_FRAMEADR: 585 d->frame_addr = val; 586 ldebug ("chan %td frame address %#x\n", d - &s->chan[0], val); 587 break; 588 589 case ES1370_REG_PHANTOM_FRAMECNT: 590 lwarn ("writing to phantom frame count %#x\n", val); 591 break; 592 case ES1370_REG_PHANTOM_FRAMEADR: 593 lwarn ("writing to phantom frame address %#x\n", val); 594 break; 595 596 case ES1370_REG_ADC_FRAMECNT: 597 d++; 598 case ES1370_REG_DAC2_FRAMECNT: 599 d++; 600 case ES1370_REG_DAC1_FRAMECNT: 601 d->frame_cnt = val; 602 d->leftover = 0; 603 ldebug ("chan %td frame count %d, buffer size %d\n", 604 d - &s->chan[0], val >> 16, val & 0xffff); 605 break; 606 607 default: 608 lwarn ("writel %#x <- %#x\n", addr, val); 609 break; 610 } 611 } 612 613 static uint32_t es1370_readb(void *opaque, uint32_t addr) 614 { 615 ES1370State *s = opaque; 616 uint32_t val; 617 618 addr = es1370_fixup (s, addr); 619 620 switch (addr) { 621 case 0x1b: /* Legacy */ 622 lwarn ("Attempt to read from legacy register\n"); 623 val = 5; 624 break; 625 case ES1370_REG_MEMPAGE: 626 val = s->mempage; 627 break; 628 case ES1370_REG_CONTROL + 0: 629 case ES1370_REG_CONTROL + 1: 630 case ES1370_REG_CONTROL + 2: 631 case ES1370_REG_CONTROL + 3: 632 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3); 633 break; 634 case ES1370_REG_STATUS + 0: 635 case ES1370_REG_STATUS + 1: 636 case ES1370_REG_STATUS + 2: 637 case ES1370_REG_STATUS + 3: 638 val = s->status >> ((addr - ES1370_REG_STATUS) << 3); 639 break; 640 default: 641 val = ~0; 642 lwarn ("readb %#x -> %#x\n", addr, val); 643 break; 644 } 645 return val; 646 } 647 648 static uint32_t es1370_readw(void *opaque, uint32_t addr) 649 { 650 ES1370State *s = opaque; 651 struct chan *d = &s->chan[0]; 652 uint32_t val; 653 654 addr = es1370_fixup (s, addr); 655 656 switch (addr) { 657 case ES1370_REG_ADC_SCOUNT + 2: 658 d++; 659 case ES1370_REG_DAC2_SCOUNT + 2: 660 d++; 661 case ES1370_REG_DAC1_SCOUNT + 2: 662 val = d->scount >> 16; 663 break; 664 665 case ES1370_REG_ADC_FRAMECNT: 666 d++; 667 case ES1370_REG_DAC2_FRAMECNT: 668 d++; 669 case ES1370_REG_DAC1_FRAMECNT: 670 val = d->frame_cnt & 0xffff; 671 break; 672 673 case ES1370_REG_ADC_FRAMECNT + 2: 674 d++; 675 case ES1370_REG_DAC2_FRAMECNT + 2: 676 d++; 677 case ES1370_REG_DAC1_FRAMECNT + 2: 678 val = d->frame_cnt >> 16; 679 break; 680 681 default: 682 val = ~0; 683 lwarn ("readw %#x -> %#x\n", addr, val); 684 break; 685 } 686 687 return val; 688 } 689 690 static uint32_t es1370_readl(void *opaque, uint32_t addr) 691 { 692 ES1370State *s = opaque; 693 uint32_t val; 694 struct chan *d = &s->chan[0]; 695 696 addr = es1370_fixup (s, addr); 697 698 switch (addr) { 699 case ES1370_REG_CONTROL: 700 val = s->ctl; 701 break; 702 case ES1370_REG_STATUS: 703 val = s->status; 704 break; 705 case ES1370_REG_MEMPAGE: 706 val = s->mempage; 707 break; 708 case ES1370_REG_CODEC: 709 val = s->codec; 710 break; 711 case ES1370_REG_SERIAL_CONTROL: 712 val = s->sctl; 713 break; 714 715 case ES1370_REG_ADC_SCOUNT: 716 d++; 717 case ES1370_REG_DAC2_SCOUNT: 718 d++; 719 case ES1370_REG_DAC1_SCOUNT: 720 val = d->scount; 721 #ifdef DEBUG_ES1370 722 { 723 uint32_t curr_count = d->scount >> 16; 724 uint32_t count = d->scount & 0xffff; 725 726 curr_count <<= d->shift; 727 count <<= d->shift; 728 dolog ("read scount curr %d, total %d\n", curr_count, count); 729 } 730 #endif 731 break; 732 733 case ES1370_REG_ADC_FRAMECNT: 734 d++; 735 case ES1370_REG_DAC2_FRAMECNT: 736 d++; 737 case ES1370_REG_DAC1_FRAMECNT: 738 val = d->frame_cnt; 739 #ifdef DEBUG_ES1370 740 { 741 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2; 742 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2; 743 if (curr > size) { 744 dolog ("read framecnt curr %d, size %d %d\n", curr, size, 745 curr > size); 746 } 747 } 748 #endif 749 break; 750 751 case ES1370_REG_ADC_FRAMEADR: 752 d++; 753 case ES1370_REG_DAC2_FRAMEADR: 754 d++; 755 case ES1370_REG_DAC1_FRAMEADR: 756 val = d->frame_addr; 757 break; 758 759 case ES1370_REG_PHANTOM_FRAMECNT: 760 val = ~0U; 761 lwarn ("reading from phantom frame count\n"); 762 break; 763 case ES1370_REG_PHANTOM_FRAMEADR: 764 val = ~0U; 765 lwarn ("reading from phantom frame address\n"); 766 break; 767 768 default: 769 val = ~0U; 770 lwarn ("readl %#x -> %#x\n", addr, val); 771 break; 772 } 773 return val; 774 } 775 776 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel, 777 int max, int *irq) 778 { 779 uint8_t tmpbuf[4096]; 780 uint32_t addr = d->frame_addr; 781 int sc = d->scount & 0xffff; 782 int csc = d->scount >> 16; 783 int csc_bytes = (csc + 1) << d->shift; 784 int cnt = d->frame_cnt >> 16; 785 int size = d->frame_cnt & 0xffff; 786 int left = ((size - cnt + 1) << 2) + d->leftover; 787 int transferred = 0; 788 int temp = audio_MIN (max, audio_MIN (left, csc_bytes)); 789 int index = d - &s->chan[0]; 790 791 addr += (cnt << 2) + d->leftover; 792 793 if (index == ADC_CHANNEL) { 794 while (temp) { 795 int acquired, to_copy; 796 797 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf)); 798 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy); 799 if (!acquired) 800 break; 801 802 pci_dma_write (&s->dev, addr, tmpbuf, acquired); 803 804 temp -= acquired; 805 addr += acquired; 806 transferred += acquired; 807 } 808 } 809 else { 810 SWVoiceOut *voice = s->dac_voice[index]; 811 812 while (temp) { 813 int copied, to_copy; 814 815 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf)); 816 pci_dma_read (&s->dev, addr, tmpbuf, to_copy); 817 copied = AUD_write (voice, tmpbuf, to_copy); 818 if (!copied) 819 break; 820 temp -= copied; 821 addr += copied; 822 transferred += copied; 823 } 824 } 825 826 if (csc_bytes == transferred) { 827 *irq = 1; 828 d->scount = sc | (sc << 16); 829 ldebug ("sc = %d, rate = %f\n", 830 (sc + 1) << d->shift, 831 (sc + 1) / (double) 44100); 832 } 833 else { 834 *irq = 0; 835 d->scount = sc | (((csc_bytes - transferred - 1) >> d->shift) << 16); 836 } 837 838 cnt += (transferred + d->leftover) >> 2; 839 840 if (s->sctl & loop_sel) { 841 /* Bah, how stupid is that having a 0 represent true value? 842 i just spent few hours on this shit */ 843 AUD_log ("es1370: warning", "non looping mode\n"); 844 } 845 else { 846 d->frame_cnt = size; 847 848 if ((uint32_t) cnt <= d->frame_cnt) 849 d->frame_cnt |= cnt << 16; 850 } 851 852 d->leftover = (transferred + d->leftover) & 3; 853 } 854 855 static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail) 856 { 857 uint32_t new_status = s->status; 858 int max_bytes, irq; 859 struct chan *d = &s->chan[chan]; 860 const struct chan_bits *b = &es1370_chan_bits[chan]; 861 862 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) { 863 return; 864 } 865 866 max_bytes = free_or_avail; 867 max_bytes &= ~((1 << d->shift) - 1); 868 if (!max_bytes) { 869 return; 870 } 871 872 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq); 873 874 if (irq) { 875 if (s->sctl & b->sctl_inten) { 876 new_status |= b->stat_int; 877 } 878 } 879 880 if (new_status != s->status) { 881 es1370_update_status (s, new_status); 882 } 883 } 884 885 static void es1370_dac1_callback (void *opaque, int free) 886 { 887 ES1370State *s = opaque; 888 889 es1370_run_channel (s, DAC1_CHANNEL, free); 890 } 891 892 static void es1370_dac2_callback (void *opaque, int free) 893 { 894 ES1370State *s = opaque; 895 896 es1370_run_channel (s, DAC2_CHANNEL, free); 897 } 898 899 static void es1370_adc_callback (void *opaque, int avail) 900 { 901 ES1370State *s = opaque; 902 903 es1370_run_channel (s, ADC_CHANNEL, avail); 904 } 905 906 static uint64_t es1370_read(void *opaque, hwaddr addr, 907 unsigned size) 908 { 909 switch (size) { 910 case 1: 911 return es1370_readb(opaque, addr); 912 case 2: 913 return es1370_readw(opaque, addr); 914 case 4: 915 return es1370_readl(opaque, addr); 916 default: 917 return -1; 918 } 919 } 920 921 static void es1370_write(void *opaque, hwaddr addr, uint64_t val, 922 unsigned size) 923 { 924 switch (size) { 925 case 1: 926 es1370_writeb(opaque, addr, val); 927 break; 928 case 2: 929 es1370_writew(opaque, addr, val); 930 break; 931 case 4: 932 es1370_writel(opaque, addr, val); 933 break; 934 } 935 } 936 937 static const MemoryRegionOps es1370_io_ops = { 938 .read = es1370_read, 939 .write = es1370_write, 940 .impl = { 941 .min_access_size = 1, 942 .max_access_size = 4, 943 }, 944 .endianness = DEVICE_LITTLE_ENDIAN, 945 }; 946 947 static const VMStateDescription vmstate_es1370_channel = { 948 .name = "es1370_channel", 949 .version_id = 2, 950 .minimum_version_id = 2, 951 .fields = (VMStateField[]) { 952 VMSTATE_UINT32 (shift, struct chan), 953 VMSTATE_UINT32 (leftover, struct chan), 954 VMSTATE_UINT32 (scount, struct chan), 955 VMSTATE_UINT32 (frame_addr, struct chan), 956 VMSTATE_UINT32 (frame_cnt, struct chan), 957 VMSTATE_END_OF_LIST () 958 } 959 }; 960 961 static int es1370_post_load (void *opaque, int version_id) 962 { 963 uint32_t ctl, sctl; 964 ES1370State *s = opaque; 965 size_t i; 966 967 for (i = 0; i < NB_CHANNELS; ++i) { 968 if (i == ADC_CHANNEL) { 969 if (s->adc_voice) { 970 AUD_close_in (&s->card, s->adc_voice); 971 s->adc_voice = NULL; 972 } 973 } 974 else { 975 if (s->dac_voice[i]) { 976 AUD_close_out (&s->card, s->dac_voice[i]); 977 s->dac_voice[i] = NULL; 978 } 979 } 980 } 981 982 ctl = s->ctl; 983 sctl = s->sctl; 984 s->ctl = 0; 985 s->sctl = 0; 986 es1370_update_voices (s, ctl, sctl); 987 return 0; 988 } 989 990 static const VMStateDescription vmstate_es1370 = { 991 .name = "es1370", 992 .version_id = 2, 993 .minimum_version_id = 2, 994 .post_load = es1370_post_load, 995 .fields = (VMStateField[]) { 996 VMSTATE_PCI_DEVICE (dev, ES1370State), 997 VMSTATE_STRUCT_ARRAY (chan, ES1370State, NB_CHANNELS, 2, 998 vmstate_es1370_channel, struct chan), 999 VMSTATE_UINT32 (ctl, ES1370State), 1000 VMSTATE_UINT32 (status, ES1370State), 1001 VMSTATE_UINT32 (mempage, ES1370State), 1002 VMSTATE_UINT32 (codec, ES1370State), 1003 VMSTATE_UINT32 (sctl, ES1370State), 1004 VMSTATE_END_OF_LIST () 1005 } 1006 }; 1007 1008 static void es1370_on_reset (void *opaque) 1009 { 1010 ES1370State *s = opaque; 1011 es1370_reset (s); 1012 } 1013 1014 static void es1370_realize(PCIDevice *dev, Error **errp) 1015 { 1016 ES1370State *s = DO_UPCAST (ES1370State, dev, dev); 1017 uint8_t *c = s->dev.config; 1018 1019 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_SLOW >> 8; 1020 1021 #if 0 1022 c[PCI_CAPABILITY_LIST] = 0xdc; 1023 c[PCI_INTERRUPT_LINE] = 10; 1024 c[0xdc] = 0x00; 1025 #endif 1026 1027 c[PCI_INTERRUPT_PIN] = 1; 1028 c[PCI_MIN_GNT] = 0x0c; 1029 c[PCI_MAX_LAT] = 0x80; 1030 1031 memory_region_init_io (&s->io, OBJECT(s), &es1370_io_ops, s, "es1370", 256); 1032 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 1033 qemu_register_reset (es1370_on_reset, s); 1034 1035 AUD_register_card ("es1370", &s->card); 1036 es1370_reset (s); 1037 } 1038 1039 static int es1370_init (PCIBus *bus) 1040 { 1041 pci_create_simple (bus, -1, "ES1370"); 1042 return 0; 1043 } 1044 1045 static void es1370_class_init (ObjectClass *klass, void *data) 1046 { 1047 DeviceClass *dc = DEVICE_CLASS (klass); 1048 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass); 1049 1050 k->realize = es1370_realize; 1051 k->vendor_id = PCI_VENDOR_ID_ENSONIQ; 1052 k->device_id = PCI_DEVICE_ID_ENSONIQ_ES1370; 1053 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 1054 k->subsystem_vendor_id = 0x4942; 1055 k->subsystem_id = 0x4c4c; 1056 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1057 dc->desc = "ENSONIQ AudioPCI ES1370"; 1058 dc->vmsd = &vmstate_es1370; 1059 } 1060 1061 static const TypeInfo es1370_info = { 1062 .name = "ES1370", 1063 .parent = TYPE_PCI_DEVICE, 1064 .instance_size = sizeof (ES1370State), 1065 .class_init = es1370_class_init, 1066 }; 1067 1068 static void es1370_register_types (void) 1069 { 1070 type_register_static (&es1370_info); 1071 pci_register_soundhw("es1370", "ENSONIQ AudioPCI ES1370", es1370_init); 1072 } 1073 1074 type_init (es1370_register_types) 1075 1076