1 /* 2 * QEMU Crystal CS4231 audio chip emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "trace.h" 28 29 /* 30 * In addition to Crystal CS4231 there is a DMA controller on Sparc. 31 */ 32 #define CS_SIZE 0x40 33 #define CS_REGS 16 34 #define CS_DREGS 32 35 #define CS_MAXDREG (CS_DREGS - 1) 36 37 #define TYPE_CS4231 "SUNW,CS4231" 38 #define CS4231(obj) \ 39 OBJECT_CHECK(CSState, (obj), TYPE_CS4231) 40 41 typedef struct CSState { 42 SysBusDevice parent_obj; 43 44 MemoryRegion iomem; 45 qemu_irq irq; 46 uint32_t regs[CS_REGS]; 47 uint8_t dregs[CS_DREGS]; 48 } CSState; 49 50 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) 51 #define CS_VER 0xa0 52 #define CS_CDC_VER 0x8a 53 54 static void cs_reset(DeviceState *d) 55 { 56 CSState *s = CS4231(d); 57 58 memset(s->regs, 0, CS_REGS * 4); 59 memset(s->dregs, 0, CS_DREGS); 60 s->dregs[12] = CS_CDC_VER; 61 s->dregs[25] = CS_VER; 62 } 63 64 static uint64_t cs_mem_read(void *opaque, hwaddr addr, 65 unsigned size) 66 { 67 CSState *s = opaque; 68 uint32_t saddr, ret; 69 70 saddr = addr >> 2; 71 switch (saddr) { 72 case 1: 73 switch (CS_RAP(s)) { 74 case 3: // Write only 75 ret = 0; 76 break; 77 default: 78 ret = s->dregs[CS_RAP(s)]; 79 break; 80 } 81 trace_cs4231_mem_readl_dreg(CS_RAP(s), ret); 82 break; 83 default: 84 ret = s->regs[saddr]; 85 trace_cs4231_mem_readl_reg(saddr, ret); 86 break; 87 } 88 return ret; 89 } 90 91 static void cs_mem_write(void *opaque, hwaddr addr, 92 uint64_t val, unsigned size) 93 { 94 CSState *s = opaque; 95 uint32_t saddr; 96 97 saddr = addr >> 2; 98 trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val); 99 switch (saddr) { 100 case 1: 101 trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val); 102 switch(CS_RAP(s)) { 103 case 11: 104 case 25: // Read only 105 break; 106 case 12: 107 val &= 0x40; 108 val |= CS_CDC_VER; // Codec version 109 s->dregs[CS_RAP(s)] = val; 110 break; 111 default: 112 s->dregs[CS_RAP(s)] = val; 113 break; 114 } 115 break; 116 case 2: // Read only 117 break; 118 case 4: 119 if (val & 1) { 120 cs_reset(DEVICE(s)); 121 } 122 val &= 0x7f; 123 s->regs[saddr] = val; 124 break; 125 default: 126 s->regs[saddr] = val; 127 break; 128 } 129 } 130 131 static const MemoryRegionOps cs_mem_ops = { 132 .read = cs_mem_read, 133 .write = cs_mem_write, 134 .endianness = DEVICE_NATIVE_ENDIAN, 135 }; 136 137 static const VMStateDescription vmstate_cs4231 = { 138 .name ="cs4231", 139 .version_id = 1, 140 .minimum_version_id = 1, 141 .fields = (VMStateField[]) { 142 VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS), 143 VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS), 144 VMSTATE_END_OF_LIST() 145 } 146 }; 147 148 static void cs4231_init(Object *obj) 149 { 150 CSState *s = CS4231(obj); 151 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 152 153 memory_region_init_io(&s->iomem, obj, &cs_mem_ops, s, "cs4321", 154 CS_SIZE); 155 sysbus_init_mmio(dev, &s->iomem); 156 sysbus_init_irq(dev, &s->irq); 157 } 158 159 static Property cs4231_properties[] = { 160 {.name = NULL}, 161 }; 162 163 static void cs4231_class_init(ObjectClass *klass, void *data) 164 { 165 DeviceClass *dc = DEVICE_CLASS(klass); 166 167 dc->reset = cs_reset; 168 dc->vmsd = &vmstate_cs4231; 169 dc->props = cs4231_properties; 170 } 171 172 static const TypeInfo cs4231_info = { 173 .name = TYPE_CS4231, 174 .parent = TYPE_SYS_BUS_DEVICE, 175 .instance_size = sizeof(CSState), 176 .instance_init = cs4231_init, 177 .class_init = cs4231_class_init, 178 }; 179 180 static void cs4231_register_types(void) 181 { 182 type_register_static(&cs4231_info); 183 } 184 185 type_init(cs4231_register_types) 186