1 /* 2 * Copyright (C) 2006 InnoTek Systemberatung GmbH 3 * 4 * This file is part of VirtualBox Open Source Edition (OSE), as 5 * available from http://www.virtualbox.org. This file is free software; 6 * you can redistribute it and/or modify it under the terms of the GNU 7 * General Public License as published by the Free Software Foundation, 8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE 9 * distribution. VirtualBox OSE is distributed in the hope that it will 10 * be useful, but WITHOUT ANY WARRANTY of any kind. 11 * 12 * If you received this file as part of a commercial VirtualBox 13 * distribution, then only the terms of your commercial VirtualBox 14 * license agreement apply instead of the previous paragraph. 15 * 16 * Contributions after 2012-01-13 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/audio/soundhw.h" 22 #include "audio/audio.h" 23 #include "hw/pci/pci.h" 24 #include "hw/qdev-properties.h" 25 #include "migration/vmstate.h" 26 #include "qemu/module.h" 27 #include "sysemu/dma.h" 28 29 enum { 30 AC97_Reset = 0x00, 31 AC97_Master_Volume_Mute = 0x02, 32 AC97_Headphone_Volume_Mute = 0x04, 33 AC97_Master_Volume_Mono_Mute = 0x06, 34 AC97_Master_Tone_RL = 0x08, 35 AC97_PC_BEEP_Volume_Mute = 0x0A, 36 AC97_Phone_Volume_Mute = 0x0C, 37 AC97_Mic_Volume_Mute = 0x0E, 38 AC97_Line_In_Volume_Mute = 0x10, 39 AC97_CD_Volume_Mute = 0x12, 40 AC97_Video_Volume_Mute = 0x14, 41 AC97_Aux_Volume_Mute = 0x16, 42 AC97_PCM_Out_Volume_Mute = 0x18, 43 AC97_Record_Select = 0x1A, 44 AC97_Record_Gain_Mute = 0x1C, 45 AC97_Record_Gain_Mic_Mute = 0x1E, 46 AC97_General_Purpose = 0x20, 47 AC97_3D_Control = 0x22, 48 AC97_AC_97_RESERVED = 0x24, 49 AC97_Powerdown_Ctrl_Stat = 0x26, 50 AC97_Extended_Audio_ID = 0x28, 51 AC97_Extended_Audio_Ctrl_Stat = 0x2A, 52 AC97_PCM_Front_DAC_Rate = 0x2C, 53 AC97_PCM_Surround_DAC_Rate = 0x2E, 54 AC97_PCM_LFE_DAC_Rate = 0x30, 55 AC97_PCM_LR_ADC_Rate = 0x32, 56 AC97_MIC_ADC_Rate = 0x34, 57 AC97_6Ch_Vol_C_LFE_Mute = 0x36, 58 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38, 59 AC97_Vendor_Reserved = 0x58, 60 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */ 61 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */ 62 AC97_Vendor_ID1 = 0x7c, 63 AC97_Vendor_ID2 = 0x7e 64 }; 65 66 #define SOFT_VOLUME 67 #define SR_FIFOE 16 /* rwc */ 68 #define SR_BCIS 8 /* rwc */ 69 #define SR_LVBCI 4 /* rwc */ 70 #define SR_CELV 2 /* ro */ 71 #define SR_DCH 1 /* ro */ 72 #define SR_VALID_MASK ((1 << 5) - 1) 73 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 74 #define SR_RO_MASK (SR_DCH | SR_CELV) 75 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 76 77 #define CR_IOCE 16 /* rw */ 78 #define CR_FEIE 8 /* rw */ 79 #define CR_LVBIE 4 /* rw */ 80 #define CR_RR 2 /* rw */ 81 #define CR_RPBM 1 /* rw */ 82 #define CR_VALID_MASK ((1 << 5) - 1) 83 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) 84 85 #define GC_WR 4 /* rw */ 86 #define GC_CR 2 /* rw */ 87 #define GC_VALID_MASK ((1 << 6) - 1) 88 89 #define GS_MD3 (1<<17) /* rw */ 90 #define GS_AD3 (1<<16) /* rw */ 91 #define GS_RCS (1<<15) /* rwc */ 92 #define GS_B3S12 (1<<14) /* ro */ 93 #define GS_B2S12 (1<<13) /* ro */ 94 #define GS_B1S12 (1<<12) /* ro */ 95 #define GS_S1R1 (1<<11) /* rwc */ 96 #define GS_S0R1 (1<<10) /* rwc */ 97 #define GS_S1CR (1<<9) /* ro */ 98 #define GS_S0CR (1<<8) /* ro */ 99 #define GS_MINT (1<<7) /* ro */ 100 #define GS_POINT (1<<6) /* ro */ 101 #define GS_PIINT (1<<5) /* ro */ 102 #define GS_RSRVD ((1<<4)|(1<<3)) 103 #define GS_MOINT (1<<2) /* ro */ 104 #define GS_MIINT (1<<1) /* ro */ 105 #define GS_GSCI 1 /* rwc */ 106 #define GS_RO_MASK (GS_B3S12| \ 107 GS_B2S12| \ 108 GS_B1S12| \ 109 GS_S1CR| \ 110 GS_S0CR| \ 111 GS_MINT| \ 112 GS_POINT| \ 113 GS_PIINT| \ 114 GS_RSRVD| \ 115 GS_MOINT| \ 116 GS_MIINT) 117 #define GS_VALID_MASK ((1 << 18) - 1) 118 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI) 119 120 #define BD_IOC (1<<31) 121 #define BD_BUP (1<<30) 122 123 #define EACS_VRA 1 124 #define EACS_VRM 8 125 126 #define MUTE_SHIFT 15 127 128 #define TYPE_AC97 "AC97" 129 #define AC97(obj) \ 130 OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97) 131 132 #define REC_MASK 7 133 enum { 134 REC_MIC = 0, 135 REC_CD, 136 REC_VIDEO, 137 REC_AUX, 138 REC_LINE_IN, 139 REC_STEREO_MIX, 140 REC_MONO_MIX, 141 REC_PHONE 142 }; 143 144 typedef struct BD { 145 uint32_t addr; 146 uint32_t ctl_len; 147 } BD; 148 149 typedef struct AC97BusMasterRegs { 150 uint32_t bdbar; /* rw 0 */ 151 uint8_t civ; /* ro 0 */ 152 uint8_t lvi; /* rw 0 */ 153 uint16_t sr; /* rw 1 */ 154 uint16_t picb; /* ro 0 */ 155 uint8_t piv; /* ro 0 */ 156 uint8_t cr; /* rw 0 */ 157 unsigned int bd_valid; 158 BD bd; 159 } AC97BusMasterRegs; 160 161 typedef struct AC97LinkState { 162 PCIDevice dev; 163 QEMUSoundCard card; 164 uint32_t glob_cnt; 165 uint32_t glob_sta; 166 uint32_t cas; 167 uint32_t last_samp; 168 AC97BusMasterRegs bm_regs[3]; 169 uint8_t mixer_data[256]; 170 SWVoiceIn *voice_pi; 171 SWVoiceOut *voice_po; 172 SWVoiceIn *voice_mc; 173 int invalid_freq[3]; 174 uint8_t silence[128]; 175 int bup_flag; 176 MemoryRegion io_nam; 177 MemoryRegion io_nabm; 178 } AC97LinkState; 179 180 enum { 181 BUP_SET = 1, 182 BUP_LAST = 2 183 }; 184 185 #ifdef DEBUG_AC97 186 #define dolog(...) AUD_log ("ac97", __VA_ARGS__) 187 #else 188 #define dolog(...) 189 #endif 190 191 #define MKREGS(prefix, start) \ 192 enum { \ 193 prefix ## _BDBAR = start, \ 194 prefix ## _CIV = start + 4, \ 195 prefix ## _LVI = start + 5, \ 196 prefix ## _SR = start + 6, \ 197 prefix ## _PICB = start + 8, \ 198 prefix ## _PIV = start + 10, \ 199 prefix ## _CR = start + 11 \ 200 } 201 202 enum { 203 PI_INDEX = 0, 204 PO_INDEX, 205 MC_INDEX, 206 LAST_INDEX 207 }; 208 209 MKREGS (PI, PI_INDEX * 16); 210 MKREGS (PO, PO_INDEX * 16); 211 MKREGS (MC, MC_INDEX * 16); 212 213 enum { 214 GLOB_CNT = 0x2c, 215 GLOB_STA = 0x30, 216 CAS = 0x34 217 }; 218 219 #define GET_BM(index) (((index) >> 4) & 3) 220 221 static void po_callback (void *opaque, int free); 222 static void pi_callback (void *opaque, int avail); 223 static void mc_callback (void *opaque, int avail); 224 225 static void warm_reset (AC97LinkState *s) 226 { 227 (void) s; 228 } 229 230 static void cold_reset (AC97LinkState * s) 231 { 232 (void) s; 233 } 234 235 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r) 236 { 237 uint8_t b[8]; 238 239 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8); 240 r->bd_valid = 1; 241 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3; 242 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]); 243 r->picb = r->bd.ctl_len & 0xffff; 244 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 245 r->civ, r->bd.addr, r->bd.ctl_len >> 16, 246 r->bd.ctl_len & 0xffff, 247 (r->bd.ctl_len & 0xffff) << 1); 248 } 249 250 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) 251 { 252 int event = 0; 253 int level = 0; 254 uint32_t new_mask = new_sr & SR_INT_MASK; 255 uint32_t old_mask = r->sr & SR_INT_MASK; 256 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT}; 257 258 if (new_mask ^ old_mask) { 259 /** @todo is IRQ deasserted when only one of status bits is cleared? */ 260 if (!new_mask) { 261 event = 1; 262 level = 0; 263 } 264 else { 265 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) { 266 event = 1; 267 level = 1; 268 } 269 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) { 270 event = 1; 271 level = 1; 272 } 273 } 274 } 275 276 r->sr = new_sr; 277 278 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n", 279 r->sr & SR_BCIS, r->sr & SR_LVBCI, 280 r->sr, 281 event, level); 282 283 if (!event) 284 return; 285 286 if (level) { 287 s->glob_sta |= masks[r - s->bm_regs]; 288 dolog ("set irq level=1\n"); 289 pci_irq_assert(&s->dev); 290 } 291 else { 292 s->glob_sta &= ~masks[r - s->bm_regs]; 293 dolog ("set irq level=0\n"); 294 pci_irq_deassert(&s->dev); 295 } 296 } 297 298 static void voice_set_active (AC97LinkState *s, int bm_index, int on) 299 { 300 switch (bm_index) { 301 case PI_INDEX: 302 AUD_set_active_in (s->voice_pi, on); 303 break; 304 305 case PO_INDEX: 306 AUD_set_active_out (s->voice_po, on); 307 break; 308 309 case MC_INDEX: 310 AUD_set_active_in (s->voice_mc, on); 311 break; 312 313 default: 314 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index); 315 break; 316 } 317 } 318 319 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r) 320 { 321 dolog ("reset_bm_regs\n"); 322 r->bdbar = 0; 323 r->civ = 0; 324 r->lvi = 0; 325 /** todo do we need to do that? */ 326 update_sr (s, r, SR_DCH); 327 r->picb = 0; 328 r->piv = 0; 329 r->cr = r->cr & CR_DONT_CLEAR_MASK; 330 r->bd_valid = 0; 331 332 voice_set_active (s, r - s->bm_regs, 0); 333 memset (s->silence, 0, sizeof (s->silence)); 334 } 335 336 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v) 337 { 338 if (i + 2 > sizeof (s->mixer_data)) { 339 dolog ("mixer_store: index %d out of bounds %zd\n", 340 i, sizeof (s->mixer_data)); 341 return; 342 } 343 344 s->mixer_data[i + 0] = v & 0xff; 345 s->mixer_data[i + 1] = v >> 8; 346 } 347 348 static uint16_t mixer_load (AC97LinkState *s, uint32_t i) 349 { 350 uint16_t val = 0xffff; 351 352 if (i + 2 > sizeof (s->mixer_data)) { 353 dolog ("mixer_load: index %d out of bounds %zd\n", 354 i, sizeof (s->mixer_data)); 355 } 356 else { 357 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8); 358 } 359 360 return val; 361 } 362 363 static void open_voice (AC97LinkState *s, int index, int freq) 364 { 365 struct audsettings as; 366 367 as.freq = freq; 368 as.nchannels = 2; 369 as.fmt = AUDIO_FORMAT_S16; 370 as.endianness = 0; 371 372 if (freq > 0) { 373 s->invalid_freq[index] = 0; 374 switch (index) { 375 case PI_INDEX: 376 s->voice_pi = AUD_open_in ( 377 &s->card, 378 s->voice_pi, 379 "ac97.pi", 380 s, 381 pi_callback, 382 &as 383 ); 384 break; 385 386 case PO_INDEX: 387 s->voice_po = AUD_open_out ( 388 &s->card, 389 s->voice_po, 390 "ac97.po", 391 s, 392 po_callback, 393 &as 394 ); 395 break; 396 397 case MC_INDEX: 398 s->voice_mc = AUD_open_in ( 399 &s->card, 400 s->voice_mc, 401 "ac97.mc", 402 s, 403 mc_callback, 404 &as 405 ); 406 break; 407 } 408 } 409 else { 410 s->invalid_freq[index] = freq; 411 switch (index) { 412 case PI_INDEX: 413 AUD_close_in (&s->card, s->voice_pi); 414 s->voice_pi = NULL; 415 break; 416 417 case PO_INDEX: 418 AUD_close_out (&s->card, s->voice_po); 419 s->voice_po = NULL; 420 break; 421 422 case MC_INDEX: 423 AUD_close_in (&s->card, s->voice_mc); 424 s->voice_mc = NULL; 425 break; 426 } 427 } 428 } 429 430 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX]) 431 { 432 uint16_t freq; 433 434 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate); 435 open_voice (s, PI_INDEX, freq); 436 AUD_set_active_in (s->voice_pi, active[PI_INDEX]); 437 438 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate); 439 open_voice (s, PO_INDEX, freq); 440 AUD_set_active_out (s->voice_po, active[PO_INDEX]); 441 442 freq = mixer_load (s, AC97_MIC_ADC_Rate); 443 open_voice (s, MC_INDEX, freq); 444 AUD_set_active_in (s->voice_mc, active[MC_INDEX]); 445 } 446 447 static void get_volume (uint16_t vol, uint16_t mask, int inverse, 448 int *mute, uint8_t *lvol, uint8_t *rvol) 449 { 450 *mute = (vol >> MUTE_SHIFT) & 1; 451 *rvol = (255 * (vol & mask)) / mask; 452 *lvol = (255 * ((vol >> 8) & mask)) / mask; 453 454 if (inverse) { 455 *rvol = 255 - *rvol; 456 *lvol = 255 - *lvol; 457 } 458 } 459 460 static void update_combined_volume_out (AC97LinkState *s) 461 { 462 uint8_t lvol, rvol, plvol, prvol; 463 int mute, pmute; 464 465 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1, 466 &mute, &lvol, &rvol); 467 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1, 468 &pmute, &plvol, &prvol); 469 470 mute = mute | pmute; 471 lvol = (lvol * plvol) / 255; 472 rvol = (rvol * prvol) / 255; 473 474 AUD_set_volume_out (s->voice_po, mute, lvol, rvol); 475 } 476 477 static void update_volume_in (AC97LinkState *s) 478 { 479 uint8_t lvol, rvol; 480 int mute; 481 482 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0, 483 &mute, &lvol, &rvol); 484 485 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol); 486 } 487 488 static void set_volume (AC97LinkState *s, int index, uint32_t val) 489 { 490 switch (index) { 491 case AC97_Master_Volume_Mute: 492 val &= 0xbf3f; 493 mixer_store (s, index, val); 494 update_combined_volume_out (s); 495 break; 496 case AC97_PCM_Out_Volume_Mute: 497 val &= 0x9f1f; 498 mixer_store (s, index, val); 499 update_combined_volume_out (s); 500 break; 501 case AC97_Record_Gain_Mute: 502 val &= 0x8f0f; 503 mixer_store (s, index, val); 504 update_volume_in (s); 505 break; 506 } 507 } 508 509 static void record_select (AC97LinkState *s, uint32_t val) 510 { 511 uint8_t rs = val & REC_MASK; 512 uint8_t ls = (val >> 8) & REC_MASK; 513 mixer_store (s, AC97_Record_Select, rs | (ls << 8)); 514 } 515 516 static void mixer_reset (AC97LinkState *s) 517 { 518 uint8_t active[LAST_INDEX]; 519 520 dolog ("mixer_reset\n"); 521 memset (s->mixer_data, 0, sizeof (s->mixer_data)); 522 memset (active, 0, sizeof (active)); 523 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */ 524 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000); 525 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000); 526 mixer_store (s, AC97_Master_Tone_RL, 0x0000); 527 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000); 528 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000); 529 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000); 530 mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000); 531 mixer_store (s, AC97_CD_Volume_Mute , 0x0000); 532 mixer_store (s, AC97_Video_Volume_Mute , 0x0000); 533 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000); 534 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000); 535 mixer_store (s, AC97_General_Purpose , 0x0000); 536 mixer_store (s, AC97_3D_Control , 0x0000); 537 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f); 538 539 /* 540 * Sigmatel 9700 (STAC9700) 541 */ 542 mixer_store (s, AC97_Vendor_ID1 , 0x8384); 543 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */ 544 545 mixer_store (s, AC97_Extended_Audio_ID , 0x0809); 546 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009); 547 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80); 548 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80); 549 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80); 550 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80); 551 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80); 552 553 record_select (s, 0); 554 set_volume (s, AC97_Master_Volume_Mute, 0x8000); 555 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808); 556 set_volume (s, AC97_Record_Gain_Mute, 0x8808); 557 558 reset_voices (s, active); 559 } 560 561 /** 562 * Native audio mixer 563 * I/O Reads 564 */ 565 static uint32_t nam_readb (void *opaque, uint32_t addr) 566 { 567 AC97LinkState *s = opaque; 568 dolog ("U nam readb %#x\n", addr); 569 s->cas = 0; 570 return ~0U; 571 } 572 573 static uint32_t nam_readw (void *opaque, uint32_t addr) 574 { 575 AC97LinkState *s = opaque; 576 uint32_t index = addr; 577 s->cas = 0; 578 return mixer_load(s, index); 579 } 580 581 static uint32_t nam_readl (void *opaque, uint32_t addr) 582 { 583 AC97LinkState *s = opaque; 584 dolog ("U nam readl %#x\n", addr); 585 s->cas = 0; 586 return ~0U; 587 } 588 589 /** 590 * Native audio mixer 591 * I/O Writes 592 */ 593 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) 594 { 595 AC97LinkState *s = opaque; 596 dolog ("U nam writeb %#x <- %#x\n", addr, val); 597 s->cas = 0; 598 } 599 600 static void nam_writew (void *opaque, uint32_t addr, uint32_t val) 601 { 602 AC97LinkState *s = opaque; 603 uint32_t index = addr; 604 s->cas = 0; 605 switch (index) { 606 case AC97_Reset: 607 mixer_reset (s); 608 break; 609 case AC97_Powerdown_Ctrl_Stat: 610 val &= ~0x800f; 611 val |= mixer_load (s, index) & 0xf; 612 mixer_store (s, index, val); 613 break; 614 case AC97_PCM_Out_Volume_Mute: 615 case AC97_Master_Volume_Mute: 616 case AC97_Record_Gain_Mute: 617 set_volume (s, index, val); 618 break; 619 case AC97_Record_Select: 620 record_select (s, val); 621 break; 622 case AC97_Vendor_ID1: 623 case AC97_Vendor_ID2: 624 dolog ("Attempt to write vendor ID to %#x\n", val); 625 break; 626 case AC97_Extended_Audio_ID: 627 dolog ("Attempt to write extended audio ID to %#x\n", val); 628 break; 629 case AC97_Extended_Audio_Ctrl_Stat: 630 if (!(val & EACS_VRA)) { 631 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80); 632 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80); 633 open_voice (s, PI_INDEX, 48000); 634 open_voice (s, PO_INDEX, 48000); 635 } 636 if (!(val & EACS_VRM)) { 637 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80); 638 open_voice (s, MC_INDEX, 48000); 639 } 640 dolog ("Setting extended audio control to %#x\n", val); 641 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val); 642 break; 643 case AC97_PCM_Front_DAC_Rate: 644 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 645 mixer_store (s, index, val); 646 dolog ("Set front DAC rate to %d\n", val); 647 open_voice (s, PO_INDEX, val); 648 } 649 else { 650 dolog ("Attempt to set front DAC rate to %d, " 651 "but VRA is not set\n", 652 val); 653 } 654 break; 655 case AC97_MIC_ADC_Rate: 656 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) { 657 mixer_store (s, index, val); 658 dolog ("Set MIC ADC rate to %d\n", val); 659 open_voice (s, MC_INDEX, val); 660 } 661 else { 662 dolog ("Attempt to set MIC ADC rate to %d, " 663 "but VRM is not set\n", 664 val); 665 } 666 break; 667 case AC97_PCM_LR_ADC_Rate: 668 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 669 mixer_store (s, index, val); 670 dolog ("Set front LR ADC rate to %d\n", val); 671 open_voice (s, PI_INDEX, val); 672 } 673 else { 674 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n", 675 val); 676 } 677 break; 678 case AC97_Headphone_Volume_Mute: 679 case AC97_Master_Volume_Mono_Mute: 680 case AC97_Master_Tone_RL: 681 case AC97_PC_BEEP_Volume_Mute: 682 case AC97_Phone_Volume_Mute: 683 case AC97_Mic_Volume_Mute: 684 case AC97_Line_In_Volume_Mute: 685 case AC97_CD_Volume_Mute: 686 case AC97_Video_Volume_Mute: 687 case AC97_Aux_Volume_Mute: 688 case AC97_Record_Gain_Mic_Mute: 689 case AC97_General_Purpose: 690 case AC97_3D_Control: 691 case AC97_Sigmatel_Analog: 692 case AC97_Sigmatel_Dac2Invert: 693 /* None of the features in these regs are emulated, so they are RO */ 694 break; 695 default: 696 dolog ("U nam writew %#x <- %#x\n", addr, val); 697 mixer_store (s, index, val); 698 break; 699 } 700 } 701 702 static void nam_writel (void *opaque, uint32_t addr, uint32_t val) 703 { 704 AC97LinkState *s = opaque; 705 dolog ("U nam writel %#x <- %#x\n", addr, val); 706 s->cas = 0; 707 } 708 709 /** 710 * Native audio bus master 711 * I/O Reads 712 */ 713 static uint32_t nabm_readb (void *opaque, uint32_t addr) 714 { 715 AC97LinkState *s = opaque; 716 AC97BusMasterRegs *r = NULL; 717 uint32_t index = addr; 718 uint32_t val = ~0U; 719 720 switch (index) { 721 case CAS: 722 dolog ("CAS %d\n", s->cas); 723 val = s->cas; 724 s->cas = 1; 725 break; 726 case PI_CIV: 727 case PO_CIV: 728 case MC_CIV: 729 r = &s->bm_regs[GET_BM (index)]; 730 val = r->civ; 731 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val); 732 break; 733 case PI_LVI: 734 case PO_LVI: 735 case MC_LVI: 736 r = &s->bm_regs[GET_BM (index)]; 737 val = r->lvi; 738 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val); 739 break; 740 case PI_PIV: 741 case PO_PIV: 742 case MC_PIV: 743 r = &s->bm_regs[GET_BM (index)]; 744 val = r->piv; 745 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val); 746 break; 747 case PI_CR: 748 case PO_CR: 749 case MC_CR: 750 r = &s->bm_regs[GET_BM (index)]; 751 val = r->cr; 752 dolog ("CR[%d] -> %#x\n", GET_BM (index), val); 753 break; 754 case PI_SR: 755 case PO_SR: 756 case MC_SR: 757 r = &s->bm_regs[GET_BM (index)]; 758 val = r->sr & 0xff; 759 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val); 760 break; 761 default: 762 dolog ("U nabm readb %#x -> %#x\n", addr, val); 763 break; 764 } 765 return val; 766 } 767 768 static uint32_t nabm_readw (void *opaque, uint32_t addr) 769 { 770 AC97LinkState *s = opaque; 771 AC97BusMasterRegs *r = NULL; 772 uint32_t index = addr; 773 uint32_t val = ~0U; 774 775 switch (index) { 776 case PI_SR: 777 case PO_SR: 778 case MC_SR: 779 r = &s->bm_regs[GET_BM (index)]; 780 val = r->sr; 781 dolog ("SR[%d] -> %#x\n", GET_BM (index), val); 782 break; 783 case PI_PICB: 784 case PO_PICB: 785 case MC_PICB: 786 r = &s->bm_regs[GET_BM (index)]; 787 val = r->picb; 788 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val); 789 break; 790 default: 791 dolog ("U nabm readw %#x -> %#x\n", addr, val); 792 break; 793 } 794 return val; 795 } 796 797 static uint32_t nabm_readl (void *opaque, uint32_t addr) 798 { 799 AC97LinkState *s = opaque; 800 AC97BusMasterRegs *r = NULL; 801 uint32_t index = addr; 802 uint32_t val = ~0U; 803 804 switch (index) { 805 case PI_BDBAR: 806 case PO_BDBAR: 807 case MC_BDBAR: 808 r = &s->bm_regs[GET_BM (index)]; 809 val = r->bdbar; 810 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val); 811 break; 812 case PI_CIV: 813 case PO_CIV: 814 case MC_CIV: 815 r = &s->bm_regs[GET_BM (index)]; 816 val = r->civ | (r->lvi << 8) | (r->sr << 16); 817 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index), 818 r->civ, r->lvi, r->sr); 819 break; 820 case PI_PICB: 821 case PO_PICB: 822 case MC_PICB: 823 r = &s->bm_regs[GET_BM (index)]; 824 val = r->picb | (r->piv << 16) | (r->cr << 24); 825 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index), 826 val, r->picb, r->piv, r->cr); 827 break; 828 case GLOB_CNT: 829 val = s->glob_cnt; 830 dolog ("glob_cnt -> %#x\n", val); 831 break; 832 case GLOB_STA: 833 val = s->glob_sta | GS_S0CR; 834 dolog ("glob_sta -> %#x\n", val); 835 break; 836 default: 837 dolog ("U nabm readl %#x -> %#x\n", addr, val); 838 break; 839 } 840 return val; 841 } 842 843 /** 844 * Native audio bus master 845 * I/O Writes 846 */ 847 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) 848 { 849 AC97LinkState *s = opaque; 850 AC97BusMasterRegs *r = NULL; 851 uint32_t index = addr; 852 switch (index) { 853 case PI_LVI: 854 case PO_LVI: 855 case MC_LVI: 856 r = &s->bm_regs[GET_BM (index)]; 857 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { 858 r->sr &= ~(SR_DCH | SR_CELV); 859 r->civ = r->piv; 860 r->piv = (r->piv + 1) % 32; 861 fetch_bd (s, r); 862 } 863 r->lvi = val % 32; 864 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val); 865 break; 866 case PI_CR: 867 case PO_CR: 868 case MC_CR: 869 r = &s->bm_regs[GET_BM (index)]; 870 if (val & CR_RR) { 871 reset_bm_regs (s, r); 872 } 873 else { 874 r->cr = val & CR_VALID_MASK; 875 if (!(r->cr & CR_RPBM)) { 876 voice_set_active (s, r - s->bm_regs, 0); 877 r->sr |= SR_DCH; 878 } 879 else { 880 r->civ = r->piv; 881 r->piv = (r->piv + 1) % 32; 882 fetch_bd (s, r); 883 r->sr &= ~SR_DCH; 884 voice_set_active (s, r - s->bm_regs, 1); 885 } 886 } 887 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr); 888 break; 889 case PI_SR: 890 case PO_SR: 891 case MC_SR: 892 r = &s->bm_regs[GET_BM (index)]; 893 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 894 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 895 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 896 break; 897 default: 898 dolog ("U nabm writeb %#x <- %#x\n", addr, val); 899 break; 900 } 901 } 902 903 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) 904 { 905 AC97LinkState *s = opaque; 906 AC97BusMasterRegs *r = NULL; 907 uint32_t index = addr; 908 switch (index) { 909 case PI_SR: 910 case PO_SR: 911 case MC_SR: 912 r = &s->bm_regs[GET_BM (index)]; 913 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 914 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 915 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 916 break; 917 default: 918 dolog ("U nabm writew %#x <- %#x\n", addr, val); 919 break; 920 } 921 } 922 923 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) 924 { 925 AC97LinkState *s = opaque; 926 AC97BusMasterRegs *r = NULL; 927 uint32_t index = addr; 928 switch (index) { 929 case PI_BDBAR: 930 case PO_BDBAR: 931 case MC_BDBAR: 932 r = &s->bm_regs[GET_BM (index)]; 933 r->bdbar = val & ~3; 934 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n", 935 GET_BM (index), val, r->bdbar); 936 break; 937 case GLOB_CNT: 938 if (val & GC_WR) 939 warm_reset (s); 940 if (val & GC_CR) 941 cold_reset (s); 942 if (!(val & (GC_WR | GC_CR))) 943 s->glob_cnt = val & GC_VALID_MASK; 944 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt); 945 break; 946 case GLOB_STA: 947 s->glob_sta &= ~(val & GS_WCLEAR_MASK); 948 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; 949 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta); 950 break; 951 default: 952 dolog ("U nabm writel %#x <- %#x\n", addr, val); 953 break; 954 } 955 } 956 957 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, 958 int max, int *stop) 959 { 960 uint8_t tmpbuf[4096]; 961 uint32_t addr = r->bd.addr; 962 uint32_t temp = r->picb << 1; 963 uint32_t written = 0; 964 int to_copy = 0; 965 temp = MIN (temp, max); 966 967 if (!temp) { 968 *stop = 1; 969 return 0; 970 } 971 972 while (temp) { 973 int copied; 974 to_copy = MIN (temp, sizeof (tmpbuf)); 975 pci_dma_read (&s->dev, addr, tmpbuf, to_copy); 976 copied = AUD_write (s->voice_po, tmpbuf, to_copy); 977 dolog ("write_audio max=%x to_copy=%x copied=%x\n", 978 max, to_copy, copied); 979 if (!copied) { 980 *stop = 1; 981 break; 982 } 983 temp -= copied; 984 addr += copied; 985 written += copied; 986 } 987 988 if (!temp) { 989 if (to_copy < 4) { 990 dolog ("whoops\n"); 991 s->last_samp = 0; 992 } 993 else { 994 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4]; 995 } 996 } 997 998 r->bd.addr = addr; 999 return written; 1000 } 1001 1002 static void write_bup (AC97LinkState *s, int elapsed) 1003 { 1004 dolog ("write_bup\n"); 1005 if (!(s->bup_flag & BUP_SET)) { 1006 if (s->bup_flag & BUP_LAST) { 1007 int i; 1008 uint8_t *p = s->silence; 1009 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) { 1010 *(uint32_t *) p = s->last_samp; 1011 } 1012 } 1013 else { 1014 memset (s->silence, 0, sizeof (s->silence)); 1015 } 1016 s->bup_flag |= BUP_SET; 1017 } 1018 1019 while (elapsed) { 1020 int temp = MIN (elapsed, sizeof (s->silence)); 1021 while (temp) { 1022 int copied = AUD_write (s->voice_po, s->silence, temp); 1023 if (!copied) 1024 return; 1025 temp -= copied; 1026 elapsed -= copied; 1027 } 1028 } 1029 } 1030 1031 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r, 1032 int max, int *stop) 1033 { 1034 uint8_t tmpbuf[4096]; 1035 uint32_t addr = r->bd.addr; 1036 uint32_t temp = r->picb << 1; 1037 uint32_t nread = 0; 1038 int to_copy = 0; 1039 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; 1040 1041 temp = MIN (temp, max); 1042 1043 if (!temp) { 1044 *stop = 1; 1045 return 0; 1046 } 1047 1048 while (temp) { 1049 int acquired; 1050 to_copy = MIN (temp, sizeof (tmpbuf)); 1051 acquired = AUD_read (voice, tmpbuf, to_copy); 1052 if (!acquired) { 1053 *stop = 1; 1054 break; 1055 } 1056 pci_dma_write (&s->dev, addr, tmpbuf, acquired); 1057 temp -= acquired; 1058 addr += acquired; 1059 nread += acquired; 1060 } 1061 1062 r->bd.addr = addr; 1063 return nread; 1064 } 1065 1066 static void transfer_audio (AC97LinkState *s, int index, int elapsed) 1067 { 1068 AC97BusMasterRegs *r = &s->bm_regs[index]; 1069 int stop = 0; 1070 1071 if (s->invalid_freq[index]) { 1072 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n", 1073 index, s->invalid_freq[index]); 1074 return; 1075 } 1076 1077 if (r->sr & SR_DCH) { 1078 if (r->cr & CR_RPBM) { 1079 switch (index) { 1080 case PO_INDEX: 1081 write_bup (s, elapsed); 1082 break; 1083 } 1084 } 1085 return; 1086 } 1087 1088 while ((elapsed >> 1) && !stop) { 1089 int temp; 1090 1091 if (!r->bd_valid) { 1092 dolog ("invalid bd\n"); 1093 fetch_bd (s, r); 1094 } 1095 1096 if (!r->picb) { 1097 dolog ("fresh bd %d is empty %#x %#x\n", 1098 r->civ, r->bd.addr, r->bd.ctl_len); 1099 if (r->civ == r->lvi) { 1100 r->sr |= SR_DCH; /* CELV? */ 1101 s->bup_flag = 0; 1102 break; 1103 } 1104 r->sr &= ~SR_CELV; 1105 r->civ = r->piv; 1106 r->piv = (r->piv + 1) % 32; 1107 fetch_bd (s, r); 1108 return; 1109 } 1110 1111 switch (index) { 1112 case PO_INDEX: 1113 temp = write_audio (s, r, elapsed, &stop); 1114 elapsed -= temp; 1115 r->picb -= (temp >> 1); 1116 break; 1117 1118 case PI_INDEX: 1119 case MC_INDEX: 1120 temp = read_audio (s, r, elapsed, &stop); 1121 elapsed -= temp; 1122 r->picb -= (temp >> 1); 1123 break; 1124 } 1125 1126 if (!r->picb) { 1127 uint32_t new_sr = r->sr & ~SR_CELV; 1128 1129 if (r->bd.ctl_len & BD_IOC) { 1130 new_sr |= SR_BCIS; 1131 } 1132 1133 if (r->civ == r->lvi) { 1134 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi); 1135 1136 new_sr |= SR_LVBCI | SR_DCH | SR_CELV; 1137 stop = 1; 1138 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0; 1139 } 1140 else { 1141 r->civ = r->piv; 1142 r->piv = (r->piv + 1) % 32; 1143 fetch_bd (s, r); 1144 } 1145 1146 update_sr (s, r, new_sr); 1147 } 1148 } 1149 } 1150 1151 static void pi_callback (void *opaque, int avail) 1152 { 1153 transfer_audio (opaque, PI_INDEX, avail); 1154 } 1155 1156 static void mc_callback (void *opaque, int avail) 1157 { 1158 transfer_audio (opaque, MC_INDEX, avail); 1159 } 1160 1161 static void po_callback (void *opaque, int free) 1162 { 1163 transfer_audio (opaque, PO_INDEX, free); 1164 } 1165 1166 static const VMStateDescription vmstate_ac97_bm_regs = { 1167 .name = "ac97_bm_regs", 1168 .version_id = 1, 1169 .minimum_version_id = 1, 1170 .fields = (VMStateField[]) { 1171 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs), 1172 VMSTATE_UINT8 (civ, AC97BusMasterRegs), 1173 VMSTATE_UINT8 (lvi, AC97BusMasterRegs), 1174 VMSTATE_UINT16 (sr, AC97BusMasterRegs), 1175 VMSTATE_UINT16 (picb, AC97BusMasterRegs), 1176 VMSTATE_UINT8 (piv, AC97BusMasterRegs), 1177 VMSTATE_UINT8 (cr, AC97BusMasterRegs), 1178 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs), 1179 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs), 1180 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs), 1181 VMSTATE_END_OF_LIST () 1182 } 1183 }; 1184 1185 static int ac97_post_load (void *opaque, int version_id) 1186 { 1187 uint8_t active[LAST_INDEX]; 1188 AC97LinkState *s = opaque; 1189 1190 record_select (s, mixer_load (s, AC97_Record_Select)); 1191 set_volume (s, AC97_Master_Volume_Mute, 1192 mixer_load (s, AC97_Master_Volume_Mute)); 1193 set_volume (s, AC97_PCM_Out_Volume_Mute, 1194 mixer_load (s, AC97_PCM_Out_Volume_Mute)); 1195 set_volume (s, AC97_Record_Gain_Mute, 1196 mixer_load (s, AC97_Record_Gain_Mute)); 1197 1198 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM); 1199 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM); 1200 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM); 1201 reset_voices (s, active); 1202 1203 s->bup_flag = 0; 1204 s->last_samp = 0; 1205 return 0; 1206 } 1207 1208 static bool is_version_2 (void *opaque, int version_id) 1209 { 1210 return version_id == 2; 1211 } 1212 1213 static const VMStateDescription vmstate_ac97 = { 1214 .name = "ac97", 1215 .version_id = 3, 1216 .minimum_version_id = 2, 1217 .post_load = ac97_post_load, 1218 .fields = (VMStateField[]) { 1219 VMSTATE_PCI_DEVICE (dev, AC97LinkState), 1220 VMSTATE_UINT32 (glob_cnt, AC97LinkState), 1221 VMSTATE_UINT32 (glob_sta, AC97LinkState), 1222 VMSTATE_UINT32 (cas, AC97LinkState), 1223 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1, 1224 vmstate_ac97_bm_regs, AC97BusMasterRegs), 1225 VMSTATE_BUFFER (mixer_data, AC97LinkState), 1226 VMSTATE_UNUSED_TEST (is_version_2, 3), 1227 VMSTATE_END_OF_LIST () 1228 } 1229 }; 1230 1231 static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size) 1232 { 1233 if ((addr / size) > 256) { 1234 return -1; 1235 } 1236 1237 switch (size) { 1238 case 1: 1239 return nam_readb(opaque, addr); 1240 case 2: 1241 return nam_readw(opaque, addr); 1242 case 4: 1243 return nam_readl(opaque, addr); 1244 default: 1245 return -1; 1246 } 1247 } 1248 1249 static void nam_write(void *opaque, hwaddr addr, uint64_t val, 1250 unsigned size) 1251 { 1252 if ((addr / size) > 256) { 1253 return; 1254 } 1255 1256 switch (size) { 1257 case 1: 1258 nam_writeb(opaque, addr, val); 1259 break; 1260 case 2: 1261 nam_writew(opaque, addr, val); 1262 break; 1263 case 4: 1264 nam_writel(opaque, addr, val); 1265 break; 1266 } 1267 } 1268 1269 static const MemoryRegionOps ac97_io_nam_ops = { 1270 .read = nam_read, 1271 .write = nam_write, 1272 .impl = { 1273 .min_access_size = 1, 1274 .max_access_size = 4, 1275 }, 1276 .endianness = DEVICE_LITTLE_ENDIAN, 1277 }; 1278 1279 static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) 1280 { 1281 if ((addr / size) > 64) { 1282 return -1; 1283 } 1284 1285 switch (size) { 1286 case 1: 1287 return nabm_readb(opaque, addr); 1288 case 2: 1289 return nabm_readw(opaque, addr); 1290 case 4: 1291 return nabm_readl(opaque, addr); 1292 default: 1293 return -1; 1294 } 1295 } 1296 1297 static void nabm_write(void *opaque, hwaddr addr, uint64_t val, 1298 unsigned size) 1299 { 1300 if ((addr / size) > 64) { 1301 return; 1302 } 1303 1304 switch (size) { 1305 case 1: 1306 nabm_writeb(opaque, addr, val); 1307 break; 1308 case 2: 1309 nabm_writew(opaque, addr, val); 1310 break; 1311 case 4: 1312 nabm_writel(opaque, addr, val); 1313 break; 1314 } 1315 } 1316 1317 1318 static const MemoryRegionOps ac97_io_nabm_ops = { 1319 .read = nabm_read, 1320 .write = nabm_write, 1321 .impl = { 1322 .min_access_size = 1, 1323 .max_access_size = 4, 1324 }, 1325 .endianness = DEVICE_LITTLE_ENDIAN, 1326 }; 1327 1328 static void ac97_on_reset (DeviceState *dev) 1329 { 1330 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev); 1331 1332 reset_bm_regs (s, &s->bm_regs[0]); 1333 reset_bm_regs (s, &s->bm_regs[1]); 1334 reset_bm_regs (s, &s->bm_regs[2]); 1335 1336 /* 1337 * Reset the mixer too. The Windows XP driver seems to rely on 1338 * this. At least it wants to read the vendor id before it resets 1339 * the codec manually. 1340 */ 1341 mixer_reset (s); 1342 } 1343 1344 static void ac97_realize(PCIDevice *dev, Error **errp) 1345 { 1346 AC97LinkState *s = AC97(dev); 1347 uint8_t *c = s->dev.config; 1348 1349 /* TODO: no need to override */ 1350 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */ 1351 c[PCI_COMMAND + 1] = 0x00; 1352 1353 /* TODO: */ 1354 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */ 1355 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 1356 1357 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */ 1358 1359 /* TODO set when bar is registered. no need to override. */ 1360 /* nabmar native audio mixer base address rw */ 1361 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO; 1362 c[PCI_BASE_ADDRESS_0 + 1] = 0x00; 1363 c[PCI_BASE_ADDRESS_0 + 2] = 0x00; 1364 c[PCI_BASE_ADDRESS_0 + 3] = 0x00; 1365 1366 /* TODO set when bar is registered. no need to override. */ 1367 /* nabmbar native audio bus mastering base address rw */ 1368 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO; 1369 c[PCI_BASE_ADDRESS_0 + 5] = 0x00; 1370 c[PCI_BASE_ADDRESS_0 + 6] = 0x00; 1371 c[PCI_BASE_ADDRESS_0 + 7] = 0x00; 1372 1373 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */ 1374 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ 1375 1376 memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s, 1377 "ac97-nam", 1024); 1378 memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s, 1379 "ac97-nabm", 256); 1380 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); 1381 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); 1382 AUD_register_card ("ac97", &s->card); 1383 ac97_on_reset(DEVICE(s)); 1384 } 1385 1386 static void ac97_exit(PCIDevice *dev) 1387 { 1388 AC97LinkState *s = AC97(dev); 1389 1390 AUD_close_in(&s->card, s->voice_pi); 1391 AUD_close_out(&s->card, s->voice_po); 1392 AUD_close_in(&s->card, s->voice_mc); 1393 AUD_remove_card(&s->card); 1394 } 1395 1396 static Property ac97_properties[] = { 1397 DEFINE_AUDIO_PROPERTIES(AC97LinkState, card), 1398 DEFINE_PROP_END_OF_LIST (), 1399 }; 1400 1401 static void ac97_class_init (ObjectClass *klass, void *data) 1402 { 1403 DeviceClass *dc = DEVICE_CLASS (klass); 1404 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass); 1405 1406 k->realize = ac97_realize; 1407 k->exit = ac97_exit; 1408 k->vendor_id = PCI_VENDOR_ID_INTEL; 1409 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5; 1410 k->revision = 0x01; 1411 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 1412 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1413 dc->desc = "Intel 82801AA AC97 Audio"; 1414 dc->vmsd = &vmstate_ac97; 1415 device_class_set_props(dc, ac97_properties); 1416 dc->reset = ac97_on_reset; 1417 } 1418 1419 static const TypeInfo ac97_info = { 1420 .name = TYPE_AC97, 1421 .parent = TYPE_PCI_DEVICE, 1422 .instance_size = sizeof (AC97LinkState), 1423 .class_init = ac97_class_init, 1424 .interfaces = (InterfaceInfo[]) { 1425 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1426 { }, 1427 }, 1428 }; 1429 1430 static void ac97_register_types (void) 1431 { 1432 type_register_static (&ac97_info); 1433 deprecated_register_soundhw("ac97", "Intel 82801AA AC97 Audio", 1434 0, TYPE_AC97); 1435 } 1436 1437 type_init (ac97_register_types) 1438