1 /* 2 * Copyright (C) 2006 InnoTek Systemberatung GmbH 3 * 4 * This file is part of VirtualBox Open Source Edition (OSE), as 5 * available from http://www.virtualbox.org. This file is free software; 6 * you can redistribute it and/or modify it under the terms of the GNU 7 * General Public License as published by the Free Software Foundation, 8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE 9 * distribution. VirtualBox OSE is distributed in the hope that it will 10 * be useful, but WITHOUT ANY WARRANTY of any kind. 11 * 12 * If you received this file as part of a commercial VirtualBox 13 * distribution, then only the terms of your commercial VirtualBox 14 * license agreement apply instead of the previous paragraph. 15 * 16 * Contributions after 2012-01-13 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "hw/audio/soundhw.h" 23 #include "audio/audio.h" 24 #include "hw/pci/pci.h" 25 #include "sysemu/dma.h" 26 27 enum { 28 AC97_Reset = 0x00, 29 AC97_Master_Volume_Mute = 0x02, 30 AC97_Headphone_Volume_Mute = 0x04, 31 AC97_Master_Volume_Mono_Mute = 0x06, 32 AC97_Master_Tone_RL = 0x08, 33 AC97_PC_BEEP_Volume_Mute = 0x0A, 34 AC97_Phone_Volume_Mute = 0x0C, 35 AC97_Mic_Volume_Mute = 0x0E, 36 AC97_Line_In_Volume_Mute = 0x10, 37 AC97_CD_Volume_Mute = 0x12, 38 AC97_Video_Volume_Mute = 0x14, 39 AC97_Aux_Volume_Mute = 0x16, 40 AC97_PCM_Out_Volume_Mute = 0x18, 41 AC97_Record_Select = 0x1A, 42 AC97_Record_Gain_Mute = 0x1C, 43 AC97_Record_Gain_Mic_Mute = 0x1E, 44 AC97_General_Purpose = 0x20, 45 AC97_3D_Control = 0x22, 46 AC97_AC_97_RESERVED = 0x24, 47 AC97_Powerdown_Ctrl_Stat = 0x26, 48 AC97_Extended_Audio_ID = 0x28, 49 AC97_Extended_Audio_Ctrl_Stat = 0x2A, 50 AC97_PCM_Front_DAC_Rate = 0x2C, 51 AC97_PCM_Surround_DAC_Rate = 0x2E, 52 AC97_PCM_LFE_DAC_Rate = 0x30, 53 AC97_PCM_LR_ADC_Rate = 0x32, 54 AC97_MIC_ADC_Rate = 0x34, 55 AC97_6Ch_Vol_C_LFE_Mute = 0x36, 56 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38, 57 AC97_Vendor_Reserved = 0x58, 58 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */ 59 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */ 60 AC97_Vendor_ID1 = 0x7c, 61 AC97_Vendor_ID2 = 0x7e 62 }; 63 64 #define SOFT_VOLUME 65 #define SR_FIFOE 16 /* rwc */ 66 #define SR_BCIS 8 /* rwc */ 67 #define SR_LVBCI 4 /* rwc */ 68 #define SR_CELV 2 /* ro */ 69 #define SR_DCH 1 /* ro */ 70 #define SR_VALID_MASK ((1 << 5) - 1) 71 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 72 #define SR_RO_MASK (SR_DCH | SR_CELV) 73 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 74 75 #define CR_IOCE 16 /* rw */ 76 #define CR_FEIE 8 /* rw */ 77 #define CR_LVBIE 4 /* rw */ 78 #define CR_RR 2 /* rw */ 79 #define CR_RPBM 1 /* rw */ 80 #define CR_VALID_MASK ((1 << 5) - 1) 81 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) 82 83 #define GC_WR 4 /* rw */ 84 #define GC_CR 2 /* rw */ 85 #define GC_VALID_MASK ((1 << 6) - 1) 86 87 #define GS_MD3 (1<<17) /* rw */ 88 #define GS_AD3 (1<<16) /* rw */ 89 #define GS_RCS (1<<15) /* rwc */ 90 #define GS_B3S12 (1<<14) /* ro */ 91 #define GS_B2S12 (1<<13) /* ro */ 92 #define GS_B1S12 (1<<12) /* ro */ 93 #define GS_S1R1 (1<<11) /* rwc */ 94 #define GS_S0R1 (1<<10) /* rwc */ 95 #define GS_S1CR (1<<9) /* ro */ 96 #define GS_S0CR (1<<8) /* ro */ 97 #define GS_MINT (1<<7) /* ro */ 98 #define GS_POINT (1<<6) /* ro */ 99 #define GS_PIINT (1<<5) /* ro */ 100 #define GS_RSRVD ((1<<4)|(1<<3)) 101 #define GS_MOINT (1<<2) /* ro */ 102 #define GS_MIINT (1<<1) /* ro */ 103 #define GS_GSCI 1 /* rwc */ 104 #define GS_RO_MASK (GS_B3S12| \ 105 GS_B2S12| \ 106 GS_B1S12| \ 107 GS_S1CR| \ 108 GS_S0CR| \ 109 GS_MINT| \ 110 GS_POINT| \ 111 GS_PIINT| \ 112 GS_RSRVD| \ 113 GS_MOINT| \ 114 GS_MIINT) 115 #define GS_VALID_MASK ((1 << 18) - 1) 116 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI) 117 118 #define BD_IOC (1<<31) 119 #define BD_BUP (1<<30) 120 121 #define EACS_VRA 1 122 #define EACS_VRM 8 123 124 #define MUTE_SHIFT 15 125 126 #define REC_MASK 7 127 enum { 128 REC_MIC = 0, 129 REC_CD, 130 REC_VIDEO, 131 REC_AUX, 132 REC_LINE_IN, 133 REC_STEREO_MIX, 134 REC_MONO_MIX, 135 REC_PHONE 136 }; 137 138 typedef struct BD { 139 uint32_t addr; 140 uint32_t ctl_len; 141 } BD; 142 143 typedef struct AC97BusMasterRegs { 144 uint32_t bdbar; /* rw 0 */ 145 uint8_t civ; /* ro 0 */ 146 uint8_t lvi; /* rw 0 */ 147 uint16_t sr; /* rw 1 */ 148 uint16_t picb; /* ro 0 */ 149 uint8_t piv; /* ro 0 */ 150 uint8_t cr; /* rw 0 */ 151 unsigned int bd_valid; 152 BD bd; 153 } AC97BusMasterRegs; 154 155 typedef struct AC97LinkState { 156 PCIDevice dev; 157 QEMUSoundCard card; 158 uint32_t use_broken_id; 159 uint32_t glob_cnt; 160 uint32_t glob_sta; 161 uint32_t cas; 162 uint32_t last_samp; 163 AC97BusMasterRegs bm_regs[3]; 164 uint8_t mixer_data[256]; 165 SWVoiceIn *voice_pi; 166 SWVoiceOut *voice_po; 167 SWVoiceIn *voice_mc; 168 int invalid_freq[3]; 169 uint8_t silence[128]; 170 int bup_flag; 171 MemoryRegion io_nam; 172 MemoryRegion io_nabm; 173 } AC97LinkState; 174 175 enum { 176 BUP_SET = 1, 177 BUP_LAST = 2 178 }; 179 180 #ifdef DEBUG_AC97 181 #define dolog(...) AUD_log ("ac97", __VA_ARGS__) 182 #else 183 #define dolog(...) 184 #endif 185 186 #define MKREGS(prefix, start) \ 187 enum { \ 188 prefix ## _BDBAR = start, \ 189 prefix ## _CIV = start + 4, \ 190 prefix ## _LVI = start + 5, \ 191 prefix ## _SR = start + 6, \ 192 prefix ## _PICB = start + 8, \ 193 prefix ## _PIV = start + 10, \ 194 prefix ## _CR = start + 11 \ 195 } 196 197 enum { 198 PI_INDEX = 0, 199 PO_INDEX, 200 MC_INDEX, 201 LAST_INDEX 202 }; 203 204 MKREGS (PI, PI_INDEX * 16); 205 MKREGS (PO, PO_INDEX * 16); 206 MKREGS (MC, MC_INDEX * 16); 207 208 enum { 209 GLOB_CNT = 0x2c, 210 GLOB_STA = 0x30, 211 CAS = 0x34 212 }; 213 214 #define GET_BM(index) (((index) >> 4) & 3) 215 216 static void po_callback (void *opaque, int free); 217 static void pi_callback (void *opaque, int avail); 218 static void mc_callback (void *opaque, int avail); 219 220 static void warm_reset (AC97LinkState *s) 221 { 222 (void) s; 223 } 224 225 static void cold_reset (AC97LinkState * s) 226 { 227 (void) s; 228 } 229 230 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r) 231 { 232 uint8_t b[8]; 233 234 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8); 235 r->bd_valid = 1; 236 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3; 237 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]); 238 r->picb = r->bd.ctl_len & 0xffff; 239 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 240 r->civ, r->bd.addr, r->bd.ctl_len >> 16, 241 r->bd.ctl_len & 0xffff, 242 (r->bd.ctl_len & 0xffff) << 1); 243 } 244 245 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) 246 { 247 int event = 0; 248 int level = 0; 249 uint32_t new_mask = new_sr & SR_INT_MASK; 250 uint32_t old_mask = r->sr & SR_INT_MASK; 251 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT}; 252 253 if (new_mask ^ old_mask) { 254 /** @todo is IRQ deasserted when only one of status bits is cleared? */ 255 if (!new_mask) { 256 event = 1; 257 level = 0; 258 } 259 else { 260 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) { 261 event = 1; 262 level = 1; 263 } 264 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) { 265 event = 1; 266 level = 1; 267 } 268 } 269 } 270 271 r->sr = new_sr; 272 273 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n", 274 r->sr & SR_BCIS, r->sr & SR_LVBCI, 275 r->sr, 276 event, level); 277 278 if (!event) 279 return; 280 281 if (level) { 282 s->glob_sta |= masks[r - s->bm_regs]; 283 dolog ("set irq level=1\n"); 284 pci_irq_assert(&s->dev); 285 } 286 else { 287 s->glob_sta &= ~masks[r - s->bm_regs]; 288 dolog ("set irq level=0\n"); 289 pci_irq_deassert(&s->dev); 290 } 291 } 292 293 static void voice_set_active (AC97LinkState *s, int bm_index, int on) 294 { 295 switch (bm_index) { 296 case PI_INDEX: 297 AUD_set_active_in (s->voice_pi, on); 298 break; 299 300 case PO_INDEX: 301 AUD_set_active_out (s->voice_po, on); 302 break; 303 304 case MC_INDEX: 305 AUD_set_active_in (s->voice_mc, on); 306 break; 307 308 default: 309 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index); 310 break; 311 } 312 } 313 314 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r) 315 { 316 dolog ("reset_bm_regs\n"); 317 r->bdbar = 0; 318 r->civ = 0; 319 r->lvi = 0; 320 /** todo do we need to do that? */ 321 update_sr (s, r, SR_DCH); 322 r->picb = 0; 323 r->piv = 0; 324 r->cr = r->cr & CR_DONT_CLEAR_MASK; 325 r->bd_valid = 0; 326 327 voice_set_active (s, r - s->bm_regs, 0); 328 memset (s->silence, 0, sizeof (s->silence)); 329 } 330 331 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v) 332 { 333 if (i + 2 > sizeof (s->mixer_data)) { 334 dolog ("mixer_store: index %d out of bounds %zd\n", 335 i, sizeof (s->mixer_data)); 336 return; 337 } 338 339 s->mixer_data[i + 0] = v & 0xff; 340 s->mixer_data[i + 1] = v >> 8; 341 } 342 343 static uint16_t mixer_load (AC97LinkState *s, uint32_t i) 344 { 345 uint16_t val = 0xffff; 346 347 if (i + 2 > sizeof (s->mixer_data)) { 348 dolog ("mixer_load: index %d out of bounds %zd\n", 349 i, sizeof (s->mixer_data)); 350 } 351 else { 352 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8); 353 } 354 355 return val; 356 } 357 358 static void open_voice (AC97LinkState *s, int index, int freq) 359 { 360 struct audsettings as; 361 362 as.freq = freq; 363 as.nchannels = 2; 364 as.fmt = AUD_FMT_S16; 365 as.endianness = 0; 366 367 if (freq > 0) { 368 s->invalid_freq[index] = 0; 369 switch (index) { 370 case PI_INDEX: 371 s->voice_pi = AUD_open_in ( 372 &s->card, 373 s->voice_pi, 374 "ac97.pi", 375 s, 376 pi_callback, 377 &as 378 ); 379 break; 380 381 case PO_INDEX: 382 s->voice_po = AUD_open_out ( 383 &s->card, 384 s->voice_po, 385 "ac97.po", 386 s, 387 po_callback, 388 &as 389 ); 390 break; 391 392 case MC_INDEX: 393 s->voice_mc = AUD_open_in ( 394 &s->card, 395 s->voice_mc, 396 "ac97.mc", 397 s, 398 mc_callback, 399 &as 400 ); 401 break; 402 } 403 } 404 else { 405 s->invalid_freq[index] = freq; 406 switch (index) { 407 case PI_INDEX: 408 AUD_close_in (&s->card, s->voice_pi); 409 s->voice_pi = NULL; 410 break; 411 412 case PO_INDEX: 413 AUD_close_out (&s->card, s->voice_po); 414 s->voice_po = NULL; 415 break; 416 417 case MC_INDEX: 418 AUD_close_in (&s->card, s->voice_mc); 419 s->voice_mc = NULL; 420 break; 421 } 422 } 423 } 424 425 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX]) 426 { 427 uint16_t freq; 428 429 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate); 430 open_voice (s, PI_INDEX, freq); 431 AUD_set_active_in (s->voice_pi, active[PI_INDEX]); 432 433 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate); 434 open_voice (s, PO_INDEX, freq); 435 AUD_set_active_out (s->voice_po, active[PO_INDEX]); 436 437 freq = mixer_load (s, AC97_MIC_ADC_Rate); 438 open_voice (s, MC_INDEX, freq); 439 AUD_set_active_in (s->voice_mc, active[MC_INDEX]); 440 } 441 442 static void get_volume (uint16_t vol, uint16_t mask, int inverse, 443 int *mute, uint8_t *lvol, uint8_t *rvol) 444 { 445 *mute = (vol >> MUTE_SHIFT) & 1; 446 *rvol = (255 * (vol & mask)) / mask; 447 *lvol = (255 * ((vol >> 8) & mask)) / mask; 448 449 if (inverse) { 450 *rvol = 255 - *rvol; 451 *lvol = 255 - *lvol; 452 } 453 } 454 455 static void update_combined_volume_out (AC97LinkState *s) 456 { 457 uint8_t lvol, rvol, plvol, prvol; 458 int mute, pmute; 459 460 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1, 461 &mute, &lvol, &rvol); 462 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1, 463 &pmute, &plvol, &prvol); 464 465 mute = mute | pmute; 466 lvol = (lvol * plvol) / 255; 467 rvol = (rvol * prvol) / 255; 468 469 AUD_set_volume_out (s->voice_po, mute, lvol, rvol); 470 } 471 472 static void update_volume_in (AC97LinkState *s) 473 { 474 uint8_t lvol, rvol; 475 int mute; 476 477 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0, 478 &mute, &lvol, &rvol); 479 480 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol); 481 } 482 483 static void set_volume (AC97LinkState *s, int index, uint32_t val) 484 { 485 switch (index) { 486 case AC97_Master_Volume_Mute: 487 val &= 0xbf3f; 488 mixer_store (s, index, val); 489 update_combined_volume_out (s); 490 break; 491 case AC97_PCM_Out_Volume_Mute: 492 val &= 0x9f1f; 493 mixer_store (s, index, val); 494 update_combined_volume_out (s); 495 break; 496 case AC97_Record_Gain_Mute: 497 val &= 0x8f0f; 498 mixer_store (s, index, val); 499 update_volume_in (s); 500 break; 501 } 502 } 503 504 static void record_select (AC97LinkState *s, uint32_t val) 505 { 506 uint8_t rs = val & REC_MASK; 507 uint8_t ls = (val >> 8) & REC_MASK; 508 mixer_store (s, AC97_Record_Select, rs | (ls << 8)); 509 } 510 511 static void mixer_reset (AC97LinkState *s) 512 { 513 uint8_t active[LAST_INDEX]; 514 515 dolog ("mixer_reset\n"); 516 memset (s->mixer_data, 0, sizeof (s->mixer_data)); 517 memset (active, 0, sizeof (active)); 518 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */ 519 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000); 520 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000); 521 mixer_store (s, AC97_Master_Tone_RL, 0x0000); 522 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000); 523 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000); 524 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000); 525 mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000); 526 mixer_store (s, AC97_CD_Volume_Mute , 0x0000); 527 mixer_store (s, AC97_Video_Volume_Mute , 0x0000); 528 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000); 529 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000); 530 mixer_store (s, AC97_General_Purpose , 0x0000); 531 mixer_store (s, AC97_3D_Control , 0x0000); 532 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f); 533 534 /* 535 * Sigmatel 9700 (STAC9700) 536 */ 537 mixer_store (s, AC97_Vendor_ID1 , 0x8384); 538 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */ 539 540 mixer_store (s, AC97_Extended_Audio_ID , 0x0809); 541 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009); 542 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80); 543 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80); 544 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80); 545 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80); 546 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80); 547 548 record_select (s, 0); 549 set_volume (s, AC97_Master_Volume_Mute, 0x8000); 550 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808); 551 set_volume (s, AC97_Record_Gain_Mute, 0x8808); 552 553 reset_voices (s, active); 554 } 555 556 /** 557 * Native audio mixer 558 * I/O Reads 559 */ 560 static uint32_t nam_readb (void *opaque, uint32_t addr) 561 { 562 AC97LinkState *s = opaque; 563 dolog ("U nam readb %#x\n", addr); 564 s->cas = 0; 565 return ~0U; 566 } 567 568 static uint32_t nam_readw (void *opaque, uint32_t addr) 569 { 570 AC97LinkState *s = opaque; 571 uint32_t val = ~0U; 572 uint32_t index = addr; 573 s->cas = 0; 574 val = mixer_load (s, index); 575 return val; 576 } 577 578 static uint32_t nam_readl (void *opaque, uint32_t addr) 579 { 580 AC97LinkState *s = opaque; 581 dolog ("U nam readl %#x\n", addr); 582 s->cas = 0; 583 return ~0U; 584 } 585 586 /** 587 * Native audio mixer 588 * I/O Writes 589 */ 590 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) 591 { 592 AC97LinkState *s = opaque; 593 dolog ("U nam writeb %#x <- %#x\n", addr, val); 594 s->cas = 0; 595 } 596 597 static void nam_writew (void *opaque, uint32_t addr, uint32_t val) 598 { 599 AC97LinkState *s = opaque; 600 uint32_t index = addr; 601 s->cas = 0; 602 switch (index) { 603 case AC97_Reset: 604 mixer_reset (s); 605 break; 606 case AC97_Powerdown_Ctrl_Stat: 607 val &= ~0x800f; 608 val |= mixer_load (s, index) & 0xf; 609 mixer_store (s, index, val); 610 break; 611 case AC97_PCM_Out_Volume_Mute: 612 case AC97_Master_Volume_Mute: 613 case AC97_Record_Gain_Mute: 614 set_volume (s, index, val); 615 break; 616 case AC97_Record_Select: 617 record_select (s, val); 618 break; 619 case AC97_Vendor_ID1: 620 case AC97_Vendor_ID2: 621 dolog ("Attempt to write vendor ID to %#x\n", val); 622 break; 623 case AC97_Extended_Audio_ID: 624 dolog ("Attempt to write extended audio ID to %#x\n", val); 625 break; 626 case AC97_Extended_Audio_Ctrl_Stat: 627 if (!(val & EACS_VRA)) { 628 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80); 629 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80); 630 open_voice (s, PI_INDEX, 48000); 631 open_voice (s, PO_INDEX, 48000); 632 } 633 if (!(val & EACS_VRM)) { 634 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80); 635 open_voice (s, MC_INDEX, 48000); 636 } 637 dolog ("Setting extended audio control to %#x\n", val); 638 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val); 639 break; 640 case AC97_PCM_Front_DAC_Rate: 641 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 642 mixer_store (s, index, val); 643 dolog ("Set front DAC rate to %d\n", val); 644 open_voice (s, PO_INDEX, val); 645 } 646 else { 647 dolog ("Attempt to set front DAC rate to %d, " 648 "but VRA is not set\n", 649 val); 650 } 651 break; 652 case AC97_MIC_ADC_Rate: 653 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) { 654 mixer_store (s, index, val); 655 dolog ("Set MIC ADC rate to %d\n", val); 656 open_voice (s, MC_INDEX, val); 657 } 658 else { 659 dolog ("Attempt to set MIC ADC rate to %d, " 660 "but VRM is not set\n", 661 val); 662 } 663 break; 664 case AC97_PCM_LR_ADC_Rate: 665 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 666 mixer_store (s, index, val); 667 dolog ("Set front LR ADC rate to %d\n", val); 668 open_voice (s, PI_INDEX, val); 669 } 670 else { 671 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n", 672 val); 673 } 674 break; 675 case AC97_Headphone_Volume_Mute: 676 case AC97_Master_Volume_Mono_Mute: 677 case AC97_Master_Tone_RL: 678 case AC97_PC_BEEP_Volume_Mute: 679 case AC97_Phone_Volume_Mute: 680 case AC97_Mic_Volume_Mute: 681 case AC97_Line_In_Volume_Mute: 682 case AC97_CD_Volume_Mute: 683 case AC97_Video_Volume_Mute: 684 case AC97_Aux_Volume_Mute: 685 case AC97_Record_Gain_Mic_Mute: 686 case AC97_General_Purpose: 687 case AC97_3D_Control: 688 case AC97_Sigmatel_Analog: 689 case AC97_Sigmatel_Dac2Invert: 690 /* None of the features in these regs are emulated, so they are RO */ 691 break; 692 default: 693 dolog ("U nam writew %#x <- %#x\n", addr, val); 694 mixer_store (s, index, val); 695 break; 696 } 697 } 698 699 static void nam_writel (void *opaque, uint32_t addr, uint32_t val) 700 { 701 AC97LinkState *s = opaque; 702 dolog ("U nam writel %#x <- %#x\n", addr, val); 703 s->cas = 0; 704 } 705 706 /** 707 * Native audio bus master 708 * I/O Reads 709 */ 710 static uint32_t nabm_readb (void *opaque, uint32_t addr) 711 { 712 AC97LinkState *s = opaque; 713 AC97BusMasterRegs *r = NULL; 714 uint32_t index = addr; 715 uint32_t val = ~0U; 716 717 switch (index) { 718 case CAS: 719 dolog ("CAS %d\n", s->cas); 720 val = s->cas; 721 s->cas = 1; 722 break; 723 case PI_CIV: 724 case PO_CIV: 725 case MC_CIV: 726 r = &s->bm_regs[GET_BM (index)]; 727 val = r->civ; 728 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val); 729 break; 730 case PI_LVI: 731 case PO_LVI: 732 case MC_LVI: 733 r = &s->bm_regs[GET_BM (index)]; 734 val = r->lvi; 735 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val); 736 break; 737 case PI_PIV: 738 case PO_PIV: 739 case MC_PIV: 740 r = &s->bm_regs[GET_BM (index)]; 741 val = r->piv; 742 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val); 743 break; 744 case PI_CR: 745 case PO_CR: 746 case MC_CR: 747 r = &s->bm_regs[GET_BM (index)]; 748 val = r->cr; 749 dolog ("CR[%d] -> %#x\n", GET_BM (index), val); 750 break; 751 case PI_SR: 752 case PO_SR: 753 case MC_SR: 754 r = &s->bm_regs[GET_BM (index)]; 755 val = r->sr & 0xff; 756 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val); 757 break; 758 default: 759 dolog ("U nabm readb %#x -> %#x\n", addr, val); 760 break; 761 } 762 return val; 763 } 764 765 static uint32_t nabm_readw (void *opaque, uint32_t addr) 766 { 767 AC97LinkState *s = opaque; 768 AC97BusMasterRegs *r = NULL; 769 uint32_t index = addr; 770 uint32_t val = ~0U; 771 772 switch (index) { 773 case PI_SR: 774 case PO_SR: 775 case MC_SR: 776 r = &s->bm_regs[GET_BM (index)]; 777 val = r->sr; 778 dolog ("SR[%d] -> %#x\n", GET_BM (index), val); 779 break; 780 case PI_PICB: 781 case PO_PICB: 782 case MC_PICB: 783 r = &s->bm_regs[GET_BM (index)]; 784 val = r->picb; 785 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val); 786 break; 787 default: 788 dolog ("U nabm readw %#x -> %#x\n", addr, val); 789 break; 790 } 791 return val; 792 } 793 794 static uint32_t nabm_readl (void *opaque, uint32_t addr) 795 { 796 AC97LinkState *s = opaque; 797 AC97BusMasterRegs *r = NULL; 798 uint32_t index = addr; 799 uint32_t val = ~0U; 800 801 switch (index) { 802 case PI_BDBAR: 803 case PO_BDBAR: 804 case MC_BDBAR: 805 r = &s->bm_regs[GET_BM (index)]; 806 val = r->bdbar; 807 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val); 808 break; 809 case PI_CIV: 810 case PO_CIV: 811 case MC_CIV: 812 r = &s->bm_regs[GET_BM (index)]; 813 val = r->civ | (r->lvi << 8) | (r->sr << 16); 814 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index), 815 r->civ, r->lvi, r->sr); 816 break; 817 case PI_PICB: 818 case PO_PICB: 819 case MC_PICB: 820 r = &s->bm_regs[GET_BM (index)]; 821 val = r->picb | (r->piv << 16) | (r->cr << 24); 822 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index), 823 val, r->picb, r->piv, r->cr); 824 break; 825 case GLOB_CNT: 826 val = s->glob_cnt; 827 dolog ("glob_cnt -> %#x\n", val); 828 break; 829 case GLOB_STA: 830 val = s->glob_sta | GS_S0CR; 831 dolog ("glob_sta -> %#x\n", val); 832 break; 833 default: 834 dolog ("U nabm readl %#x -> %#x\n", addr, val); 835 break; 836 } 837 return val; 838 } 839 840 /** 841 * Native audio bus master 842 * I/O Writes 843 */ 844 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) 845 { 846 AC97LinkState *s = opaque; 847 AC97BusMasterRegs *r = NULL; 848 uint32_t index = addr; 849 switch (index) { 850 case PI_LVI: 851 case PO_LVI: 852 case MC_LVI: 853 r = &s->bm_regs[GET_BM (index)]; 854 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { 855 r->sr &= ~(SR_DCH | SR_CELV); 856 r->civ = r->piv; 857 r->piv = (r->piv + 1) % 32; 858 fetch_bd (s, r); 859 } 860 r->lvi = val % 32; 861 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val); 862 break; 863 case PI_CR: 864 case PO_CR: 865 case MC_CR: 866 r = &s->bm_regs[GET_BM (index)]; 867 if (val & CR_RR) { 868 reset_bm_regs (s, r); 869 } 870 else { 871 r->cr = val & CR_VALID_MASK; 872 if (!(r->cr & CR_RPBM)) { 873 voice_set_active (s, r - s->bm_regs, 0); 874 r->sr |= SR_DCH; 875 } 876 else { 877 r->civ = r->piv; 878 r->piv = (r->piv + 1) % 32; 879 fetch_bd (s, r); 880 r->sr &= ~SR_DCH; 881 voice_set_active (s, r - s->bm_regs, 1); 882 } 883 } 884 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr); 885 break; 886 case PI_SR: 887 case PO_SR: 888 case MC_SR: 889 r = &s->bm_regs[GET_BM (index)]; 890 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 891 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 892 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 893 break; 894 default: 895 dolog ("U nabm writeb %#x <- %#x\n", addr, val); 896 break; 897 } 898 } 899 900 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) 901 { 902 AC97LinkState *s = opaque; 903 AC97BusMasterRegs *r = NULL; 904 uint32_t index = addr; 905 switch (index) { 906 case PI_SR: 907 case PO_SR: 908 case MC_SR: 909 r = &s->bm_regs[GET_BM (index)]; 910 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 911 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 912 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 913 break; 914 default: 915 dolog ("U nabm writew %#x <- %#x\n", addr, val); 916 break; 917 } 918 } 919 920 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) 921 { 922 AC97LinkState *s = opaque; 923 AC97BusMasterRegs *r = NULL; 924 uint32_t index = addr; 925 switch (index) { 926 case PI_BDBAR: 927 case PO_BDBAR: 928 case MC_BDBAR: 929 r = &s->bm_regs[GET_BM (index)]; 930 r->bdbar = val & ~3; 931 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n", 932 GET_BM (index), val, r->bdbar); 933 break; 934 case GLOB_CNT: 935 if (val & GC_WR) 936 warm_reset (s); 937 if (val & GC_CR) 938 cold_reset (s); 939 if (!(val & (GC_WR | GC_CR))) 940 s->glob_cnt = val & GC_VALID_MASK; 941 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt); 942 break; 943 case GLOB_STA: 944 s->glob_sta &= ~(val & GS_WCLEAR_MASK); 945 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; 946 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta); 947 break; 948 default: 949 dolog ("U nabm writel %#x <- %#x\n", addr, val); 950 break; 951 } 952 } 953 954 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, 955 int max, int *stop) 956 { 957 uint8_t tmpbuf[4096]; 958 uint32_t addr = r->bd.addr; 959 uint32_t temp = r->picb << 1; 960 uint32_t written = 0; 961 int to_copy = 0; 962 temp = audio_MIN (temp, max); 963 964 if (!temp) { 965 *stop = 1; 966 return 0; 967 } 968 969 while (temp) { 970 int copied; 971 to_copy = audio_MIN (temp, sizeof (tmpbuf)); 972 pci_dma_read (&s->dev, addr, tmpbuf, to_copy); 973 copied = AUD_write (s->voice_po, tmpbuf, to_copy); 974 dolog ("write_audio max=%x to_copy=%x copied=%x\n", 975 max, to_copy, copied); 976 if (!copied) { 977 *stop = 1; 978 break; 979 } 980 temp -= copied; 981 addr += copied; 982 written += copied; 983 } 984 985 if (!temp) { 986 if (to_copy < 4) { 987 dolog ("whoops\n"); 988 s->last_samp = 0; 989 } 990 else { 991 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4]; 992 } 993 } 994 995 r->bd.addr = addr; 996 return written; 997 } 998 999 static void write_bup (AC97LinkState *s, int elapsed) 1000 { 1001 dolog ("write_bup\n"); 1002 if (!(s->bup_flag & BUP_SET)) { 1003 if (s->bup_flag & BUP_LAST) { 1004 int i; 1005 uint8_t *p = s->silence; 1006 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) { 1007 *(uint32_t *) p = s->last_samp; 1008 } 1009 } 1010 else { 1011 memset (s->silence, 0, sizeof (s->silence)); 1012 } 1013 s->bup_flag |= BUP_SET; 1014 } 1015 1016 while (elapsed) { 1017 int temp = audio_MIN (elapsed, sizeof (s->silence)); 1018 while (temp) { 1019 int copied = AUD_write (s->voice_po, s->silence, temp); 1020 if (!copied) 1021 return; 1022 temp -= copied; 1023 elapsed -= copied; 1024 } 1025 } 1026 } 1027 1028 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r, 1029 int max, int *stop) 1030 { 1031 uint8_t tmpbuf[4096]; 1032 uint32_t addr = r->bd.addr; 1033 uint32_t temp = r->picb << 1; 1034 uint32_t nread = 0; 1035 int to_copy = 0; 1036 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; 1037 1038 temp = audio_MIN (temp, max); 1039 1040 if (!temp) { 1041 *stop = 1; 1042 return 0; 1043 } 1044 1045 while (temp) { 1046 int acquired; 1047 to_copy = audio_MIN (temp, sizeof (tmpbuf)); 1048 acquired = AUD_read (voice, tmpbuf, to_copy); 1049 if (!acquired) { 1050 *stop = 1; 1051 break; 1052 } 1053 pci_dma_write (&s->dev, addr, tmpbuf, acquired); 1054 temp -= acquired; 1055 addr += acquired; 1056 nread += acquired; 1057 } 1058 1059 r->bd.addr = addr; 1060 return nread; 1061 } 1062 1063 static void transfer_audio (AC97LinkState *s, int index, int elapsed) 1064 { 1065 AC97BusMasterRegs *r = &s->bm_regs[index]; 1066 int stop = 0; 1067 1068 if (s->invalid_freq[index]) { 1069 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n", 1070 index, s->invalid_freq[index]); 1071 return; 1072 } 1073 1074 if (r->sr & SR_DCH) { 1075 if (r->cr & CR_RPBM) { 1076 switch (index) { 1077 case PO_INDEX: 1078 write_bup (s, elapsed); 1079 break; 1080 } 1081 } 1082 return; 1083 } 1084 1085 while ((elapsed >> 1) && !stop) { 1086 int temp; 1087 1088 if (!r->bd_valid) { 1089 dolog ("invalid bd\n"); 1090 fetch_bd (s, r); 1091 } 1092 1093 if (!r->picb) { 1094 dolog ("fresh bd %d is empty %#x %#x\n", 1095 r->civ, r->bd.addr, r->bd.ctl_len); 1096 if (r->civ == r->lvi) { 1097 r->sr |= SR_DCH; /* CELV? */ 1098 s->bup_flag = 0; 1099 break; 1100 } 1101 r->sr &= ~SR_CELV; 1102 r->civ = r->piv; 1103 r->piv = (r->piv + 1) % 32; 1104 fetch_bd (s, r); 1105 return; 1106 } 1107 1108 switch (index) { 1109 case PO_INDEX: 1110 temp = write_audio (s, r, elapsed, &stop); 1111 elapsed -= temp; 1112 r->picb -= (temp >> 1); 1113 break; 1114 1115 case PI_INDEX: 1116 case MC_INDEX: 1117 temp = read_audio (s, r, elapsed, &stop); 1118 elapsed -= temp; 1119 r->picb -= (temp >> 1); 1120 break; 1121 } 1122 1123 if (!r->picb) { 1124 uint32_t new_sr = r->sr & ~SR_CELV; 1125 1126 if (r->bd.ctl_len & BD_IOC) { 1127 new_sr |= SR_BCIS; 1128 } 1129 1130 if (r->civ == r->lvi) { 1131 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi); 1132 1133 new_sr |= SR_LVBCI | SR_DCH | SR_CELV; 1134 stop = 1; 1135 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0; 1136 } 1137 else { 1138 r->civ = r->piv; 1139 r->piv = (r->piv + 1) % 32; 1140 fetch_bd (s, r); 1141 } 1142 1143 update_sr (s, r, new_sr); 1144 } 1145 } 1146 } 1147 1148 static void pi_callback (void *opaque, int avail) 1149 { 1150 transfer_audio (opaque, PI_INDEX, avail); 1151 } 1152 1153 static void mc_callback (void *opaque, int avail) 1154 { 1155 transfer_audio (opaque, MC_INDEX, avail); 1156 } 1157 1158 static void po_callback (void *opaque, int free) 1159 { 1160 transfer_audio (opaque, PO_INDEX, free); 1161 } 1162 1163 static const VMStateDescription vmstate_ac97_bm_regs = { 1164 .name = "ac97_bm_regs", 1165 .version_id = 1, 1166 .minimum_version_id = 1, 1167 .fields = (VMStateField[]) { 1168 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs), 1169 VMSTATE_UINT8 (civ, AC97BusMasterRegs), 1170 VMSTATE_UINT8 (lvi, AC97BusMasterRegs), 1171 VMSTATE_UINT16 (sr, AC97BusMasterRegs), 1172 VMSTATE_UINT16 (picb, AC97BusMasterRegs), 1173 VMSTATE_UINT8 (piv, AC97BusMasterRegs), 1174 VMSTATE_UINT8 (cr, AC97BusMasterRegs), 1175 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs), 1176 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs), 1177 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs), 1178 VMSTATE_END_OF_LIST () 1179 } 1180 }; 1181 1182 static int ac97_post_load (void *opaque, int version_id) 1183 { 1184 uint8_t active[LAST_INDEX]; 1185 AC97LinkState *s = opaque; 1186 1187 record_select (s, mixer_load (s, AC97_Record_Select)); 1188 set_volume (s, AC97_Master_Volume_Mute, 1189 mixer_load (s, AC97_Master_Volume_Mute)); 1190 set_volume (s, AC97_PCM_Out_Volume_Mute, 1191 mixer_load (s, AC97_PCM_Out_Volume_Mute)); 1192 set_volume (s, AC97_Record_Gain_Mute, 1193 mixer_load (s, AC97_Record_Gain_Mute)); 1194 1195 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM); 1196 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM); 1197 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM); 1198 reset_voices (s, active); 1199 1200 s->bup_flag = 0; 1201 s->last_samp = 0; 1202 return 0; 1203 } 1204 1205 static bool is_version_2 (void *opaque, int version_id) 1206 { 1207 return version_id == 2; 1208 } 1209 1210 static const VMStateDescription vmstate_ac97 = { 1211 .name = "ac97", 1212 .version_id = 3, 1213 .minimum_version_id = 2, 1214 .post_load = ac97_post_load, 1215 .fields = (VMStateField[]) { 1216 VMSTATE_PCI_DEVICE (dev, AC97LinkState), 1217 VMSTATE_UINT32 (glob_cnt, AC97LinkState), 1218 VMSTATE_UINT32 (glob_sta, AC97LinkState), 1219 VMSTATE_UINT32 (cas, AC97LinkState), 1220 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1, 1221 vmstate_ac97_bm_regs, AC97BusMasterRegs), 1222 VMSTATE_BUFFER (mixer_data, AC97LinkState), 1223 VMSTATE_UNUSED_TEST (is_version_2, 3), 1224 VMSTATE_END_OF_LIST () 1225 } 1226 }; 1227 1228 static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size) 1229 { 1230 if ((addr / size) > 256) { 1231 return -1; 1232 } 1233 1234 switch (size) { 1235 case 1: 1236 return nam_readb(opaque, addr); 1237 case 2: 1238 return nam_readw(opaque, addr); 1239 case 4: 1240 return nam_readl(opaque, addr); 1241 default: 1242 return -1; 1243 } 1244 } 1245 1246 static void nam_write(void *opaque, hwaddr addr, uint64_t val, 1247 unsigned size) 1248 { 1249 if ((addr / size) > 256) { 1250 return; 1251 } 1252 1253 switch (size) { 1254 case 1: 1255 nam_writeb(opaque, addr, val); 1256 break; 1257 case 2: 1258 nam_writew(opaque, addr, val); 1259 break; 1260 case 4: 1261 nam_writel(opaque, addr, val); 1262 break; 1263 } 1264 } 1265 1266 static const MemoryRegionOps ac97_io_nam_ops = { 1267 .read = nam_read, 1268 .write = nam_write, 1269 .impl = { 1270 .min_access_size = 1, 1271 .max_access_size = 4, 1272 }, 1273 .endianness = DEVICE_LITTLE_ENDIAN, 1274 }; 1275 1276 static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) 1277 { 1278 if ((addr / size) > 64) { 1279 return -1; 1280 } 1281 1282 switch (size) { 1283 case 1: 1284 return nabm_readb(opaque, addr); 1285 case 2: 1286 return nabm_readw(opaque, addr); 1287 case 4: 1288 return nabm_readl(opaque, addr); 1289 default: 1290 return -1; 1291 } 1292 } 1293 1294 static void nabm_write(void *opaque, hwaddr addr, uint64_t val, 1295 unsigned size) 1296 { 1297 if ((addr / size) > 64) { 1298 return; 1299 } 1300 1301 switch (size) { 1302 case 1: 1303 nabm_writeb(opaque, addr, val); 1304 break; 1305 case 2: 1306 nabm_writew(opaque, addr, val); 1307 break; 1308 case 4: 1309 nabm_writel(opaque, addr, val); 1310 break; 1311 } 1312 } 1313 1314 1315 static const MemoryRegionOps ac97_io_nabm_ops = { 1316 .read = nabm_read, 1317 .write = nabm_write, 1318 .impl = { 1319 .min_access_size = 1, 1320 .max_access_size = 4, 1321 }, 1322 .endianness = DEVICE_LITTLE_ENDIAN, 1323 }; 1324 1325 static void ac97_on_reset (DeviceState *dev) 1326 { 1327 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev); 1328 1329 reset_bm_regs (s, &s->bm_regs[0]); 1330 reset_bm_regs (s, &s->bm_regs[1]); 1331 reset_bm_regs (s, &s->bm_regs[2]); 1332 1333 /* 1334 * Reset the mixer too. The Windows XP driver seems to rely on 1335 * this. At least it wants to read the vendor id before it resets 1336 * the codec manually. 1337 */ 1338 mixer_reset (s); 1339 } 1340 1341 static void ac97_realize(PCIDevice *dev, Error **errp) 1342 { 1343 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev); 1344 uint8_t *c = s->dev.config; 1345 1346 /* TODO: no need to override */ 1347 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */ 1348 c[PCI_COMMAND + 1] = 0x00; 1349 1350 /* TODO: */ 1351 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */ 1352 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 1353 1354 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */ 1355 1356 /* TODO set when bar is registered. no need to override. */ 1357 /* nabmar native audio mixer base address rw */ 1358 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO; 1359 c[PCI_BASE_ADDRESS_0 + 1] = 0x00; 1360 c[PCI_BASE_ADDRESS_0 + 2] = 0x00; 1361 c[PCI_BASE_ADDRESS_0 + 3] = 0x00; 1362 1363 /* TODO set when bar is registered. no need to override. */ 1364 /* nabmbar native audio bus mastering base address rw */ 1365 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO; 1366 c[PCI_BASE_ADDRESS_0 + 5] = 0x00; 1367 c[PCI_BASE_ADDRESS_0 + 6] = 0x00; 1368 c[PCI_BASE_ADDRESS_0 + 7] = 0x00; 1369 1370 if (s->use_broken_id) { 1371 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; 1372 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80; 1373 c[PCI_SUBSYSTEM_ID] = 0x00; 1374 c[PCI_SUBSYSTEM_ID + 1] = 0x00; 1375 } 1376 1377 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */ 1378 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ 1379 1380 memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s, 1381 "ac97-nam", 1024); 1382 memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s, 1383 "ac97-nabm", 256); 1384 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); 1385 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); 1386 AUD_register_card ("ac97", &s->card); 1387 ac97_on_reset (&s->dev.qdev); 1388 } 1389 1390 static void ac97_exit(PCIDevice *dev) 1391 { 1392 AC97LinkState *s = DO_UPCAST(AC97LinkState, dev, dev); 1393 1394 AUD_close_in(&s->card, s->voice_pi); 1395 AUD_close_out(&s->card, s->voice_po); 1396 AUD_close_in(&s->card, s->voice_mc); 1397 AUD_remove_card(&s->card); 1398 } 1399 1400 static int ac97_init (PCIBus *bus) 1401 { 1402 pci_create_simple (bus, -1, "AC97"); 1403 return 0; 1404 } 1405 1406 static Property ac97_properties[] = { 1407 DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0), 1408 DEFINE_PROP_END_OF_LIST (), 1409 }; 1410 1411 static void ac97_class_init (ObjectClass *klass, void *data) 1412 { 1413 DeviceClass *dc = DEVICE_CLASS (klass); 1414 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass); 1415 1416 k->realize = ac97_realize; 1417 k->exit = ac97_exit; 1418 k->vendor_id = PCI_VENDOR_ID_INTEL; 1419 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5; 1420 k->revision = 0x01; 1421 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 1422 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1423 dc->desc = "Intel 82801AA AC97 Audio"; 1424 dc->vmsd = &vmstate_ac97; 1425 dc->props = ac97_properties; 1426 dc->reset = ac97_on_reset; 1427 } 1428 1429 static const TypeInfo ac97_info = { 1430 .name = "AC97", 1431 .parent = TYPE_PCI_DEVICE, 1432 .instance_size = sizeof (AC97LinkState), 1433 .class_init = ac97_class_init, 1434 .interfaces = (InterfaceInfo[]) { 1435 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1436 { }, 1437 }, 1438 }; 1439 1440 static void ac97_register_types (void) 1441 { 1442 type_register_static (&ac97_info); 1443 pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init); 1444 } 1445 1446 type_init (ac97_register_types) 1447