xref: /openbmc/qemu/hw/arm/xlnx-zynqmp.c (revision fa59483d)
1 /*
2  * Xilinx Zynq MPSoC emulation
3  *
4  * Copyright (C) 2015 Xilinx Inc
5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu-common.h"
21 #include "cpu.h"
22 #include "hw/arm/xlnx-zynqmp.h"
23 #include "hw/intc/arm_gic_common.h"
24 #include "exec/address-spaces.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_arm.h"
27 
28 #define GIC_NUM_SPI_INTR 160
29 
30 #define ARM_PHYS_TIMER_PPI  30
31 #define ARM_VIRT_TIMER_PPI  27
32 #define ARM_HYP_TIMER_PPI   26
33 #define ARM_SEC_TIMER_PPI   29
34 #define GIC_MAINTENANCE_PPI 25
35 
36 #define GEM_REVISION        0x40070106
37 
38 #define GIC_BASE_ADDR       0xf9000000
39 #define GIC_DIST_ADDR       0xf9010000
40 #define GIC_CPU_ADDR        0xf9020000
41 #define GIC_VIFACE_ADDR     0xf9040000
42 #define GIC_VCPU_ADDR       0xf9060000
43 
44 #define SATA_INTR           133
45 #define SATA_ADDR           0xFD0C0000
46 #define SATA_NUM_PORTS      2
47 
48 #define QSPI_ADDR           0xff0f0000
49 #define LQSPI_ADDR          0xc0000000
50 #define QSPI_IRQ            15
51 
52 #define DP_ADDR             0xfd4a0000
53 #define DP_IRQ              113
54 
55 #define DPDMA_ADDR          0xfd4c0000
56 #define DPDMA_IRQ           116
57 
58 #define IPI_ADDR            0xFF300000
59 #define IPI_IRQ             64
60 
61 #define RTC_ADDR            0xffa60000
62 #define RTC_IRQ             26
63 
64 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
65 
66 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
67     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
68 };
69 
70 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
71     57, 59, 61, 63,
72 };
73 
74 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
75     0xFF000000, 0xFF010000,
76 };
77 
78 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
79     21, 22,
80 };
81 
82 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
83     0xFF160000, 0xFF170000,
84 };
85 
86 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
87     48, 49,
88 };
89 
90 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
91     0xFF040000, 0xFF050000,
92 };
93 
94 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
95     19, 20,
96 };
97 
98 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
99     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
100     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
101 };
102 
103 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
104     124, 125, 126, 127, 128, 129, 130, 131
105 };
106 
107 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
108     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
109     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
110 };
111 
112 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
113     77, 78, 79, 80, 81, 82, 83, 84
114 };
115 
116 typedef struct XlnxZynqMPGICRegion {
117     int region_index;
118     uint32_t address;
119     uint32_t offset;
120     bool virt;
121 } XlnxZynqMPGICRegion;
122 
123 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
124     /* Distributor */
125     {
126         .region_index = 0,
127         .address = GIC_DIST_ADDR,
128         .offset = 0,
129         .virt = false
130     },
131 
132     /* CPU interface */
133     {
134         .region_index = 1,
135         .address = GIC_CPU_ADDR,
136         .offset = 0,
137         .virt = false
138     },
139     {
140         .region_index = 1,
141         .address = GIC_CPU_ADDR + 0x10000,
142         .offset = 0x1000,
143         .virt = false
144     },
145 
146     /* Virtual interface */
147     {
148         .region_index = 2,
149         .address = GIC_VIFACE_ADDR,
150         .offset = 0,
151         .virt = true
152     },
153 
154     /* Virtual CPU interface */
155     {
156         .region_index = 3,
157         .address = GIC_VCPU_ADDR,
158         .offset = 0,
159         .virt = true
160     },
161     {
162         .region_index = 3,
163         .address = GIC_VCPU_ADDR + 0x10000,
164         .offset = 0x1000,
165         .virt = true
166     },
167 };
168 
169 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
170 {
171     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
172 }
173 
174 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
175                                    Error **errp)
176 {
177     Error *err = NULL;
178     int i;
179     int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
180 
181     if (num_rpus <= 0) {
182         /* Don't create rpu-cluster object if there's nothing to put in it */
183         return;
184     }
185 
186     object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
187                             sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER,
188                             &error_abort, NULL);
189     qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
190 
191     for (i = 0; i < num_rpus; i++) {
192         char *name;
193 
194         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
195                           "cortex-r5f-" TYPE_ARM_CPU);
196         object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
197                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
198 
199         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
200         if (strcmp(name, boot_cpu)) {
201             /* Secondary CPUs start in PSCI powered-down state */
202             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
203                                      "start-powered-off", &error_abort);
204         } else {
205             s->boot_cpu_ptr = &s->rpu_cpu[i];
206         }
207         g_free(name);
208 
209         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
210                                  &error_abort);
211         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
212                                  &err);
213         if (err) {
214             error_propagate(errp, err);
215             return;
216         }
217     }
218 
219     qdev_init_nofail(DEVICE(&s->rpu_cluster));
220 }
221 
222 static void xlnx_zynqmp_init(Object *obj)
223 {
224     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
225     int i;
226     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
227 
228     object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
229                             sizeof(s->apu_cluster), TYPE_CPU_CLUSTER,
230                             &error_abort, NULL);
231     qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
232 
233     for (i = 0; i < num_apus; i++) {
234         object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
235                                 &s->apu_cpu[i], sizeof(s->apu_cpu[i]),
236                                 "cortex-a53-" TYPE_ARM_CPU, &error_abort,
237                                 NULL);
238     }
239 
240     sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
241                           gic_class_name());
242 
243     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
244         sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]),
245                               TYPE_CADENCE_GEM);
246     }
247 
248     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
249         sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
250                               TYPE_CADENCE_UART);
251     }
252 
253     sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
254                           TYPE_SYSBUS_AHCI);
255 
256     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
257         sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i],
258                               sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI);
259     }
260 
261     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
262         sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
263                               TYPE_XILINX_SPIPS);
264     }
265 
266     sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi),
267                           TYPE_XLNX_ZYNQMP_QSPIPS);
268 
269     sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP);
270 
271     sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma),
272                           TYPE_XLNX_DPDMA);
273 
274     sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi),
275                           TYPE_XLNX_ZYNQMP_IPI);
276 
277     sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
278                           TYPE_XLNX_ZYNQMP_RTC);
279 
280     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
281         sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]),
282                               TYPE_XLNX_ZDMA);
283     }
284 
285     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
286         sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]),
287                               TYPE_XLNX_ZDMA);
288     }
289 }
290 
291 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
292 {
293     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
294     MemoryRegion *system_memory = get_system_memory();
295     uint8_t i;
296     uint64_t ram_size;
297     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
298     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
299     ram_addr_t ddr_low_size, ddr_high_size;
300     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
301     Error *err = NULL;
302 
303     ram_size = memory_region_size(s->ddr_ram);
304 
305     /* Create the DDR Memory Regions. User friendly checks should happen at
306      * the board level
307      */
308     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
309         /* The RAM size is above the maximum available for the low DDR.
310          * Create the high DDR memory region as well.
311          */
312         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
313         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
314         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
315 
316         memory_region_init_alias(&s->ddr_ram_high, NULL,
317                                  "ddr-ram-high", s->ddr_ram,
318                                   ddr_low_size, ddr_high_size);
319         memory_region_add_subregion(get_system_memory(),
320                                     XLNX_ZYNQMP_HIGH_RAM_START,
321                                     &s->ddr_ram_high);
322     } else {
323         /* RAM must be non-zero */
324         assert(ram_size);
325         ddr_low_size = ram_size;
326     }
327 
328     memory_region_init_alias(&s->ddr_ram_low, NULL,
329                              "ddr-ram-low", s->ddr_ram,
330                               0, ddr_low_size);
331     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
332 
333     /* Create the four OCM banks */
334     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
335         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
336 
337         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
338                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
339         memory_region_add_subregion(get_system_memory(),
340                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
341                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
342                                     &s->ocm_ram[i]);
343 
344         g_free(ocm_name);
345     }
346 
347     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
348     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
349     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
350     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
351     qdev_prop_set_bit(DEVICE(&s->gic),
352                       "has-virtualization-extensions", s->virt);
353 
354     qdev_init_nofail(DEVICE(&s->apu_cluster));
355 
356     /* Realize APUs before realizing the GIC. KVM requires this.  */
357     for (i = 0; i < num_apus; i++) {
358         char *name;
359 
360         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
361                                 "psci-conduit", &error_abort);
362 
363         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
364         if (strcmp(name, boot_cpu)) {
365             /* Secondary CPUs start in PSCI powered-down state */
366             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
367                                      "start-powered-off", &error_abort);
368         } else {
369             s->boot_cpu_ptr = &s->apu_cpu[i];
370         }
371         g_free(name);
372 
373         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
374                                  s->secure, "has_el3", NULL);
375         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
376                                  s->virt, "has_el2", NULL);
377         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
378                                 "reset-cbar", &error_abort);
379         object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
380                                 "core-count", &error_abort);
381         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
382                                  &err);
383         if (err) {
384             error_propagate(errp, err);
385             return;
386         }
387     }
388 
389     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
390     if (err) {
391         error_propagate(errp, err);
392         return;
393     }
394 
395     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
396     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
397         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
398         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
399         MemoryRegion *mr;
400         uint32_t addr = r->address;
401         int j;
402 
403         if (r->virt && !s->virt) {
404             continue;
405         }
406 
407         mr = sysbus_mmio_get_region(gic, r->region_index);
408         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
409             MemoryRegion *alias = &s->gic_mr[i][j];
410 
411             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
412                                      r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
413             memory_region_add_subregion(system_memory, addr, alias);
414 
415             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
416         }
417     }
418 
419     for (i = 0; i < num_apus; i++) {
420         qemu_irq irq;
421 
422         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
423                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
424                                             ARM_CPU_IRQ));
425         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
426                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
427                                             ARM_CPU_FIQ));
428         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
429                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
430                                             ARM_CPU_VIRQ));
431         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
432                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
433                                             ARM_CPU_VFIQ));
434         irq = qdev_get_gpio_in(DEVICE(&s->gic),
435                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
436         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
437         irq = qdev_get_gpio_in(DEVICE(&s->gic),
438                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
439         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
440         irq = qdev_get_gpio_in(DEVICE(&s->gic),
441                                arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
442         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
443         irq = qdev_get_gpio_in(DEVICE(&s->gic),
444                                arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
445         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
446 
447         if (s->virt) {
448             irq = qdev_get_gpio_in(DEVICE(&s->gic),
449                                    arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
450             sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
451         }
452     }
453 
454     if (s->has_rpu) {
455         info_report("The 'has_rpu' property is no longer required, to use the "
456                     "RPUs just use -smp 6.");
457     }
458 
459     xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
460     if (err) {
461         error_propagate(errp, err);
462         return;
463     }
464 
465     if (!s->boot_cpu_ptr) {
466         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
467         return;
468     }
469 
470     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
471         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
472     }
473 
474     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
475         NICInfo *nd = &nd_table[i];
476 
477         if (nd->used) {
478             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
479             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
480         }
481         object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
482                                 &error_abort);
483         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
484                                 &error_abort);
485         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
486         if (err) {
487             error_propagate(errp, err);
488             return;
489         }
490         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
491         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
492                            gic_spi[gem_intr[i]]);
493     }
494 
495     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
496         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
497         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
498         if (err) {
499             error_propagate(errp, err);
500             return;
501         }
502         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
503         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
504                            gic_spi[uart_intr[i]]);
505     }
506 
507     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
508                             &error_abort);
509     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
510     if (err) {
511         error_propagate(errp, err);
512         return;
513     }
514 
515     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
516     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
517 
518     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
519         char *bus_name = g_strdup_printf("sd-bus%d", i);
520         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
521         Object *sdhci = OBJECT(&s->sdhci[i]);
522 
523         /* Compatible with:
524          * - SD Host Controller Specification Version 3.00
525          * - SDIO Specification Version 3.0
526          * - eMMC Specification Version 4.51
527          */
528         object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
529         object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
530         object_property_set_uint(sdhci, UHS_I, "uhs", &err);
531         object_property_set_bool(sdhci, true, "realized", &err);
532         if (err) {
533             error_propagate(errp, err);
534             return;
535         }
536         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
537         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
538 
539         /* Alias controller SD bus to the SoC itself */
540         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
541                                   &error_abort);
542         g_free(bus_name);
543     }
544 
545     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
546         gchar *bus_name;
547 
548         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
549 
550         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
551         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
552                            gic_spi[spi_intr[i]]);
553 
554         /* Alias controller SPI bus to the SoC itself */
555         bus_name = g_strdup_printf("spi%d", i);
556         object_property_add_alias(OBJECT(s), bus_name,
557                                   OBJECT(&s->spi[i]), "spi0",
558                                   &error_abort);
559         g_free(bus_name);
560     }
561 
562     object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
563     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
564     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
565     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
566 
567     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
568         gchar *bus_name;
569         gchar *target_bus;
570 
571         /* Alias controller SPI bus to the SoC itself */
572         bus_name = g_strdup_printf("qspi%d", i);
573         target_bus = g_strdup_printf("spi%d", i);
574         object_property_add_alias(OBJECT(s), bus_name,
575                                   OBJECT(&s->qspi), target_bus,
576                                   &error_abort);
577         g_free(bus_name);
578         g_free(target_bus);
579     }
580 
581     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
582     if (err) {
583         error_propagate(errp, err);
584         return;
585     }
586     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
587     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
588 
589     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
590     if (err) {
591         error_propagate(errp, err);
592         return;
593     }
594     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
595                              &error_abort);
596     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
597     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
598 
599     object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
600     if (err) {
601         error_propagate(errp, err);
602         return;
603     }
604     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
605     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
606 
607     object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
608     if (err) {
609         error_propagate(errp, err);
610         return;
611     }
612     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
613     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
614 
615     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
616         object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
617         object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
618         if (err) {
619             error_propagate(errp, err);
620             return;
621         }
622 
623         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
624         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
625                            gic_spi[gdma_ch_intr[i]]);
626     }
627 
628     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
629         object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
630         if (err) {
631             error_propagate(errp, err);
632             return;
633         }
634 
635         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
636         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
637                            gic_spi[adma_ch_intr[i]]);
638     }
639 }
640 
641 static Property xlnx_zynqmp_props[] = {
642     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
643     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
644     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
645     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
646     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
647                      MemoryRegion *),
648     DEFINE_PROP_END_OF_LIST()
649 };
650 
651 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
652 {
653     DeviceClass *dc = DEVICE_CLASS(oc);
654 
655     dc->props = xlnx_zynqmp_props;
656     dc->realize = xlnx_zynqmp_realize;
657     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
658     dc->user_creatable = false;
659 }
660 
661 static const TypeInfo xlnx_zynqmp_type_info = {
662     .name = TYPE_XLNX_ZYNQMP,
663     .parent = TYPE_DEVICE,
664     .instance_size = sizeof(XlnxZynqMPState),
665     .instance_init = xlnx_zynqmp_init,
666     .class_init = xlnx_zynqmp_class_init,
667 };
668 
669 static void xlnx_zynqmp_register_types(void)
670 {
671     type_register_static(&xlnx_zynqmp_type_info);
672 }
673 
674 type_init(xlnx_zynqmp_register_types)
675