1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "hw/arm/xlnx-zynqmp.h" 19 #include "hw/intc/arm_gic_common.h" 20 #include "exec/address-spaces.h" 21 22 #define GIC_NUM_SPI_INTR 160 23 24 #define ARM_PHYS_TIMER_PPI 30 25 #define ARM_VIRT_TIMER_PPI 27 26 27 #define GIC_BASE_ADDR 0xf9000000 28 #define GIC_DIST_ADDR 0xf9010000 29 #define GIC_CPU_ADDR 0xf9020000 30 31 typedef struct XlnxZynqMPGICRegion { 32 int region_index; 33 uint32_t address; 34 } XlnxZynqMPGICRegion; 35 36 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 37 { .region_index = 0, .address = GIC_DIST_ADDR, }, 38 { .region_index = 1, .address = GIC_CPU_ADDR, }, 39 }; 40 41 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 42 { 43 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 44 } 45 46 static void xlnx_zynqmp_init(Object *obj) 47 { 48 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 49 int i; 50 51 for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { 52 object_initialize(&s->cpu[i], sizeof(s->cpu[i]), 53 "cortex-a53-" TYPE_ARM_CPU); 54 object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), 55 &error_abort); 56 } 57 58 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 59 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 60 } 61 62 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 63 { 64 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 65 MemoryRegion *system_memory = get_system_memory(); 66 uint8_t i; 67 Error *err = NULL; 68 69 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 70 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 71 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS); 72 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 73 if (err) { 74 error_propagate((errp), (err)); 75 return; 76 } 77 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 78 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 79 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 80 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 81 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 82 uint32_t addr = r->address; 83 int j; 84 85 sysbus_mmio_map(gic, r->region_index, addr); 86 87 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 88 MemoryRegion *alias = &s->gic_mr[i][j]; 89 90 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 91 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 92 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 93 memory_region_add_subregion(system_memory, addr, alias); 94 } 95 } 96 97 for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { 98 qemu_irq irq; 99 100 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 101 "psci-conduit", &error_abort); 102 if (i > 0) { 103 /* Secondary CPUs start in PSCI powered-down state */ 104 object_property_set_bool(OBJECT(&s->cpu[i]), true, 105 "start-powered-off", &error_abort); 106 } 107 108 object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR, 109 "reset-cbar", &err); 110 if (err) { 111 error_propagate((errp), (err)); 112 return; 113 } 114 115 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 116 if (err) { 117 error_propagate((errp), (err)); 118 return; 119 } 120 121 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 122 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 123 irq = qdev_get_gpio_in(DEVICE(&s->gic), 124 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 125 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq); 126 irq = qdev_get_gpio_in(DEVICE(&s->gic), 127 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 128 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq); 129 } 130 } 131 132 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 133 { 134 DeviceClass *dc = DEVICE_CLASS(oc); 135 136 dc->realize = xlnx_zynqmp_realize; 137 } 138 139 static const TypeInfo xlnx_zynqmp_type_info = { 140 .name = TYPE_XLNX_ZYNQMP, 141 .parent = TYPE_DEVICE, 142 .instance_size = sizeof(XlnxZynqMPState), 143 .instance_init = xlnx_zynqmp_init, 144 .class_init = xlnx_zynqmp_class_init, 145 }; 146 147 static void xlnx_zynqmp_register_types(void) 148 { 149 type_register_static(&xlnx_zynqmp_type_info); 150 } 151 152 type_init(xlnx_zynqmp_register_types) 153