1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 33 #define GEM_REVISION 0x40070106 34 35 #define GIC_BASE_ADDR 0xf9000000 36 #define GIC_DIST_ADDR 0xf9010000 37 #define GIC_CPU_ADDR 0xf9020000 38 39 #define SATA_INTR 133 40 #define SATA_ADDR 0xFD0C0000 41 #define SATA_NUM_PORTS 2 42 43 #define QSPI_ADDR 0xff0f0000 44 #define LQSPI_ADDR 0xc0000000 45 #define QSPI_IRQ 15 46 47 #define DP_ADDR 0xfd4a0000 48 #define DP_IRQ 113 49 50 #define DPDMA_ADDR 0xfd4c0000 51 #define DPDMA_IRQ 116 52 53 #define IPI_ADDR 0xFF300000 54 #define IPI_IRQ 64 55 56 #define RTC_ADDR 0xffa60000 57 #define RTC_IRQ 26 58 59 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 60 61 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 62 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 63 }; 64 65 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 66 57, 59, 61, 63, 67 }; 68 69 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 70 0xFF000000, 0xFF010000, 71 }; 72 73 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 74 21, 22, 75 }; 76 77 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 78 0xFF160000, 0xFF170000, 79 }; 80 81 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 82 48, 49, 83 }; 84 85 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 86 0xFF040000, 0xFF050000, 87 }; 88 89 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 90 19, 20, 91 }; 92 93 typedef struct XlnxZynqMPGICRegion { 94 int region_index; 95 uint32_t address; 96 } XlnxZynqMPGICRegion; 97 98 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 99 { .region_index = 0, .address = GIC_DIST_ADDR, }, 100 { .region_index = 1, .address = GIC_CPU_ADDR, }, 101 }; 102 103 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 104 { 105 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 106 } 107 108 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 109 Error **errp) 110 { 111 Error *err = NULL; 112 int i; 113 int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); 114 115 for (i = 0; i < num_rpus; i++) { 116 char *name; 117 118 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 119 "cortex-r5-" TYPE_ARM_CPU); 120 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 121 OBJECT(&s->rpu_cpu[i]), &error_abort); 122 123 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 124 if (strcmp(name, boot_cpu)) { 125 /* Secondary CPUs start in PSCI powered-down state */ 126 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 127 "start-powered-off", &error_abort); 128 } else { 129 s->boot_cpu_ptr = &s->rpu_cpu[i]; 130 } 131 g_free(name); 132 133 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 134 &error_abort); 135 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 136 &err); 137 if (err) { 138 error_propagate(errp, err); 139 return; 140 } 141 } 142 } 143 144 static void xlnx_zynqmp_init(Object *obj) 145 { 146 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 147 int i; 148 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 149 150 for (i = 0; i < num_apus; i++) { 151 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 152 "cortex-a53-" TYPE_ARM_CPU); 153 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 154 &error_abort); 155 } 156 157 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 158 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 159 160 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 161 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 162 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 163 } 164 165 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 166 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 167 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 168 } 169 170 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 171 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 172 173 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 174 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 175 TYPE_SYSBUS_SDHCI); 176 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 177 sysbus_get_default()); 178 } 179 180 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 181 object_initialize(&s->spi[i], sizeof(s->spi[i]), 182 TYPE_XILINX_SPIPS); 183 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 184 } 185 186 object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); 187 qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); 188 189 object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); 190 qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); 191 192 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); 193 qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); 194 195 object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); 196 qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); 197 198 object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); 199 qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); 200 } 201 202 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 203 { 204 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 205 MemoryRegion *system_memory = get_system_memory(); 206 uint8_t i; 207 uint64_t ram_size; 208 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 209 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 210 ram_addr_t ddr_low_size, ddr_high_size; 211 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 212 Error *err = NULL; 213 214 ram_size = memory_region_size(s->ddr_ram); 215 216 /* Create the DDR Memory Regions. User friendly checks should happen at 217 * the board level 218 */ 219 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 220 /* The RAM size is above the maximum available for the low DDR. 221 * Create the high DDR memory region as well. 222 */ 223 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 224 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 225 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 226 227 memory_region_init_alias(&s->ddr_ram_high, NULL, 228 "ddr-ram-high", s->ddr_ram, 229 ddr_low_size, ddr_high_size); 230 memory_region_add_subregion(get_system_memory(), 231 XLNX_ZYNQMP_HIGH_RAM_START, 232 &s->ddr_ram_high); 233 } else { 234 /* RAM must be non-zero */ 235 assert(ram_size); 236 ddr_low_size = ram_size; 237 } 238 239 memory_region_init_alias(&s->ddr_ram_low, NULL, 240 "ddr-ram-low", s->ddr_ram, 241 0, ddr_low_size); 242 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 243 244 /* Create the four OCM banks */ 245 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 246 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 247 248 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 249 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 250 memory_region_add_subregion(get_system_memory(), 251 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 252 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 253 &s->ocm_ram[i]); 254 255 g_free(ocm_name); 256 } 257 258 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 259 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 260 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 261 262 /* Realize APUs before realizing the GIC. KVM requires this. */ 263 for (i = 0; i < num_apus; i++) { 264 char *name; 265 266 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 267 "psci-conduit", &error_abort); 268 269 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 270 if (strcmp(name, boot_cpu)) { 271 /* Secondary CPUs start in PSCI powered-down state */ 272 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 273 "start-powered-off", &error_abort); 274 } else { 275 s->boot_cpu_ptr = &s->apu_cpu[i]; 276 } 277 g_free(name); 278 279 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 280 s->secure, "has_el3", NULL); 281 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 282 s->virt, "has_el2", NULL); 283 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 284 "reset-cbar", &error_abort); 285 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 286 &err); 287 if (err) { 288 error_propagate(errp, err); 289 return; 290 } 291 } 292 293 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 294 if (err) { 295 error_propagate(errp, err); 296 return; 297 } 298 299 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 300 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 301 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 302 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 303 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 304 uint32_t addr = r->address; 305 int j; 306 307 sysbus_mmio_map(gic, r->region_index, addr); 308 309 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 310 MemoryRegion *alias = &s->gic_mr[i][j]; 311 312 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 313 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 314 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 315 memory_region_add_subregion(system_memory, addr, alias); 316 } 317 } 318 319 for (i = 0; i < num_apus; i++) { 320 qemu_irq irq; 321 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 323 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 324 ARM_CPU_IRQ)); 325 irq = qdev_get_gpio_in(DEVICE(&s->gic), 326 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 327 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 328 irq = qdev_get_gpio_in(DEVICE(&s->gic), 329 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 330 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 331 } 332 333 if (s->has_rpu) { 334 info_report("The 'has_rpu' property is no longer required, to use the " 335 "RPUs just use -smp 6."); 336 } 337 338 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 339 if (err) { 340 error_propagate(errp, err); 341 return; 342 } 343 344 if (!s->boot_cpu_ptr) { 345 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 346 return; 347 } 348 349 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 350 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 351 } 352 353 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 354 NICInfo *nd = &nd_table[i]; 355 356 if (nd->used) { 357 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 358 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 359 } 360 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 361 &error_abort); 362 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 363 &error_abort); 364 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 365 if (err) { 366 error_propagate(errp, err); 367 return; 368 } 369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 370 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 371 gic_spi[gem_intr[i]]); 372 } 373 374 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 375 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); 376 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 377 if (err) { 378 error_propagate(errp, err); 379 return; 380 } 381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 382 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 383 gic_spi[uart_intr[i]]); 384 } 385 386 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 387 &error_abort); 388 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 389 if (err) { 390 error_propagate(errp, err); 391 return; 392 } 393 394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 395 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 396 397 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 398 char *bus_name = g_strdup_printf("sd-bus%d", i); 399 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 400 Object *sdhci = OBJECT(&s->sdhci[i]); 401 402 /* Compatible with: 403 * - SD Host Controller Specification Version 3.00 404 * - SDIO Specification Version 3.0 405 * - eMMC Specification Version 4.51 406 */ 407 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 408 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 409 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 410 object_property_set_bool(sdhci, true, "realized", &err); 411 if (err) { 412 error_propagate(errp, err); 413 return; 414 } 415 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 416 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 417 418 /* Alias controller SD bus to the SoC itself */ 419 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus", 420 &error_abort); 421 g_free(bus_name); 422 } 423 424 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 425 gchar *bus_name; 426 427 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 428 429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 431 gic_spi[spi_intr[i]]); 432 433 /* Alias controller SPI bus to the SoC itself */ 434 bus_name = g_strdup_printf("spi%d", i); 435 object_property_add_alias(OBJECT(s), bus_name, 436 OBJECT(&s->spi[i]), "spi0", 437 &error_abort); 438 g_free(bus_name); 439 } 440 441 object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); 442 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 445 446 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 447 gchar *bus_name; 448 gchar *target_bus; 449 450 /* Alias controller SPI bus to the SoC itself */ 451 bus_name = g_strdup_printf("qspi%d", i); 452 target_bus = g_strdup_printf("spi%d", i); 453 object_property_add_alias(OBJECT(s), bus_name, 454 OBJECT(&s->qspi), target_bus, 455 &error_abort); 456 g_free(bus_name); 457 g_free(target_bus); 458 } 459 460 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 461 if (err) { 462 error_propagate(errp, err); 463 return; 464 } 465 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 467 468 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 469 if (err) { 470 error_propagate(errp, err); 471 return; 472 } 473 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 474 &error_abort); 475 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 476 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 477 478 object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err); 479 if (err) { 480 error_propagate(errp, err); 481 return; 482 } 483 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 485 486 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 487 if (err) { 488 error_propagate(errp, err); 489 return; 490 } 491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 493 } 494 495 static Property xlnx_zynqmp_props[] = { 496 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 497 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 498 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 499 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 500 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 501 MemoryRegion *), 502 DEFINE_PROP_END_OF_LIST() 503 }; 504 505 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 506 { 507 DeviceClass *dc = DEVICE_CLASS(oc); 508 509 dc->props = xlnx_zynqmp_props; 510 dc->realize = xlnx_zynqmp_realize; 511 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 512 dc->user_creatable = false; 513 } 514 515 static const TypeInfo xlnx_zynqmp_type_info = { 516 .name = TYPE_XLNX_ZYNQMP, 517 .parent = TYPE_DEVICE, 518 .instance_size = sizeof(XlnxZynqMPState), 519 .instance_init = xlnx_zynqmp_init, 520 .class_init = xlnx_zynqmp_class_init, 521 }; 522 523 static void xlnx_zynqmp_register_types(void) 524 { 525 type_register_static(&xlnx_zynqmp_type_info); 526 } 527 528 type_init(xlnx_zynqmp_register_types) 529