1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/arm/xlnx-zynqmp.h" 20 #include "hw/intc/arm_gic_common.h" 21 #include "exec/address-spaces.h" 22 23 #define GIC_NUM_SPI_INTR 160 24 25 #define ARM_PHYS_TIMER_PPI 30 26 #define ARM_VIRT_TIMER_PPI 27 27 28 #define GIC_BASE_ADDR 0xf9000000 29 #define GIC_DIST_ADDR 0xf9010000 30 #define GIC_CPU_ADDR 0xf9020000 31 32 #define SATA_INTR 133 33 #define SATA_ADDR 0xFD0C0000 34 #define SATA_NUM_PORTS 2 35 36 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 37 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 38 }; 39 40 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 41 57, 59, 61, 63, 42 }; 43 44 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 45 0xFF000000, 0xFF010000, 46 }; 47 48 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 49 21, 22, 50 }; 51 52 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 53 0xFF160000, 0xFF170000, 54 }; 55 56 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 57 48, 49, 58 }; 59 60 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 61 0xFF040000, 0xFF050000, 62 }; 63 64 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 65 19, 20, 66 }; 67 68 typedef struct XlnxZynqMPGICRegion { 69 int region_index; 70 uint32_t address; 71 } XlnxZynqMPGICRegion; 72 73 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 74 { .region_index = 0, .address = GIC_DIST_ADDR, }, 75 { .region_index = 1, .address = GIC_CPU_ADDR, }, 76 }; 77 78 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 79 { 80 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 81 } 82 83 static void xlnx_zynqmp_init(Object *obj) 84 { 85 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 86 int i; 87 88 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 89 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 90 "cortex-a53-" TYPE_ARM_CPU); 91 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 92 &error_abort); 93 } 94 95 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 96 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 97 "cortex-r5-" TYPE_ARM_CPU); 98 object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), 99 &error_abort); 100 } 101 102 object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, 103 (Object **)&s->ddr_ram, 104 qdev_prop_allow_set_link_before_realize, 105 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 106 107 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 108 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 109 110 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 111 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 112 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 113 } 114 115 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 116 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 117 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 118 } 119 120 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 121 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 122 123 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 124 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 125 TYPE_SYSBUS_SDHCI); 126 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 127 sysbus_get_default()); 128 } 129 130 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 131 object_initialize(&s->spi[i], sizeof(s->spi[i]), 132 TYPE_XILINX_SPIPS); 133 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 134 } 135 } 136 137 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 138 { 139 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 140 MemoryRegion *system_memory = get_system_memory(); 141 uint8_t i; 142 uint64_t ram_size; 143 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 144 ram_addr_t ddr_low_size, ddr_high_size; 145 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 146 Error *err = NULL; 147 148 ram_size = memory_region_size(s->ddr_ram); 149 150 /* Create the DDR Memory Regions. User friendly checks should happen at 151 * the board level 152 */ 153 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 154 /* The RAM size is above the maximum available for the low DDR. 155 * Create the high DDR memory region as well. 156 */ 157 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 158 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 159 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 160 161 memory_region_init_alias(&s->ddr_ram_high, NULL, 162 "ddr-ram-high", s->ddr_ram, 163 ddr_low_size, ddr_high_size); 164 memory_region_add_subregion(get_system_memory(), 165 XLNX_ZYNQMP_HIGH_RAM_START, 166 &s->ddr_ram_high); 167 } else { 168 /* RAM must be non-zero */ 169 assert(ram_size); 170 ddr_low_size = ram_size; 171 } 172 173 memory_region_init_alias(&s->ddr_ram_low, NULL, 174 "ddr-ram-low", s->ddr_ram, 175 0, ddr_low_size); 176 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 177 178 /* Create the four OCM banks */ 179 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 180 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 181 182 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 183 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 184 vmstate_register_ram_global(&s->ocm_ram[i]); 185 memory_region_add_subregion(get_system_memory(), 186 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 187 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 188 &s->ocm_ram[i]); 189 190 g_free(ocm_name); 191 } 192 193 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 194 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 195 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 196 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 197 if (err) { 198 error_propagate(errp, err); 199 return; 200 } 201 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 202 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 203 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 204 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 205 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 206 uint32_t addr = r->address; 207 int j; 208 209 sysbus_mmio_map(gic, r->region_index, addr); 210 211 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 212 MemoryRegion *alias = &s->gic_mr[i][j]; 213 214 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 215 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 216 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 217 memory_region_add_subregion(system_memory, addr, alias); 218 } 219 } 220 221 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 222 qemu_irq irq; 223 char *name; 224 225 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 226 "psci-conduit", &error_abort); 227 228 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 229 if (strcmp(name, boot_cpu)) { 230 /* Secondary CPUs start in PSCI powered-down state */ 231 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 232 "start-powered-off", &error_abort); 233 } else { 234 s->boot_cpu_ptr = &s->apu_cpu[i]; 235 } 236 g_free(name); 237 238 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 239 "reset-cbar", &error_abort); 240 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 241 &err); 242 if (err) { 243 error_propagate(errp, err); 244 return; 245 } 246 247 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 248 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 249 ARM_CPU_IRQ)); 250 irq = qdev_get_gpio_in(DEVICE(&s->gic), 251 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 252 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 253 irq = qdev_get_gpio_in(DEVICE(&s->gic), 254 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 255 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 256 } 257 258 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 259 char *name; 260 261 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 262 if (strcmp(name, boot_cpu)) { 263 /* Secondary CPUs start in PSCI powered-down state */ 264 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 265 "start-powered-off", &error_abort); 266 } else { 267 s->boot_cpu_ptr = &s->rpu_cpu[i]; 268 } 269 g_free(name); 270 271 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 272 &error_abort); 273 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 274 &err); 275 if (err) { 276 error_propagate(errp, err); 277 return; 278 } 279 } 280 281 if (!s->boot_cpu_ptr) { 282 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 283 return; 284 } 285 286 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 287 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 288 } 289 290 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 291 NICInfo *nd = &nd_table[i]; 292 293 if (nd->used) { 294 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 295 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 296 } 297 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 298 if (err) { 299 error_propagate(errp, err); 300 return; 301 } 302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 304 gic_spi[gem_intr[i]]); 305 } 306 307 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 308 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 309 if (err) { 310 error_propagate(errp, err); 311 return; 312 } 313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 315 gic_spi[uart_intr[i]]); 316 } 317 318 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 319 &error_abort); 320 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 321 if (err) { 322 error_propagate(errp, err); 323 return; 324 } 325 326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 328 329 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 330 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 331 "realized", &err); 332 if (err) { 333 error_propagate(errp, err); 334 return; 335 } 336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 337 sdhci_addr[i]); 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 339 gic_spi[sdhci_intr[i]]); 340 } 341 342 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 343 gchar *bus_name; 344 345 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 346 347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 349 gic_spi[spi_intr[i]]); 350 351 /* Alias controller SPI bus to the SoC itself */ 352 bus_name = g_strdup_printf("spi%d", i); 353 object_property_add_alias(OBJECT(s), bus_name, 354 OBJECT(&s->spi[i]), "spi0", 355 &error_abort); 356 g_free(bus_name); 357 } 358 } 359 360 static Property xlnx_zynqmp_props[] = { 361 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 362 DEFINE_PROP_END_OF_LIST() 363 }; 364 365 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 366 { 367 DeviceClass *dc = DEVICE_CLASS(oc); 368 369 dc->props = xlnx_zynqmp_props; 370 dc->realize = xlnx_zynqmp_realize; 371 372 /* 373 * Reason: creates an ARM CPU, thus use after free(), see 374 * arm_cpu_class_init() 375 */ 376 dc->cannot_destroy_with_object_finalize_yet = true; 377 } 378 379 static const TypeInfo xlnx_zynqmp_type_info = { 380 .name = TYPE_XLNX_ZYNQMP, 381 .parent = TYPE_DEVICE, 382 .instance_size = sizeof(XlnxZynqMPState), 383 .instance_init = xlnx_zynqmp_init, 384 .class_init = xlnx_zynqmp_class_init, 385 }; 386 387 static void xlnx_zynqmp_register_types(void) 388 { 389 type_register_static(&xlnx_zynqmp_type_info); 390 } 391 392 type_init(xlnx_zynqmp_register_types) 393