1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "hw/arm/xlnx-zynqmp.h" 19 #include "hw/intc/arm_gic_common.h" 20 #include "exec/address-spaces.h" 21 22 #define GIC_NUM_SPI_INTR 160 23 24 #define ARM_PHYS_TIMER_PPI 30 25 #define ARM_VIRT_TIMER_PPI 27 26 27 #define GIC_BASE_ADDR 0xf9000000 28 #define GIC_DIST_ADDR 0xf9010000 29 #define GIC_CPU_ADDR 0xf9020000 30 31 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 32 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 33 }; 34 35 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 36 57, 59, 61, 63, 37 }; 38 39 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 40 0xFF000000, 0xFF010000, 41 }; 42 43 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 44 21, 22, 45 }; 46 47 typedef struct XlnxZynqMPGICRegion { 48 int region_index; 49 uint32_t address; 50 } XlnxZynqMPGICRegion; 51 52 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 53 { .region_index = 0, .address = GIC_DIST_ADDR, }, 54 { .region_index = 1, .address = GIC_CPU_ADDR, }, 55 }; 56 57 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 58 { 59 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 60 } 61 62 static void xlnx_zynqmp_init(Object *obj) 63 { 64 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 65 int i; 66 67 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 68 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 69 "cortex-a53-" TYPE_ARM_CPU); 70 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 71 &error_abort); 72 } 73 74 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 75 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 76 "cortex-r5-" TYPE_ARM_CPU); 77 object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), 78 &error_abort); 79 } 80 81 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 82 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 83 84 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 85 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 86 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 87 } 88 89 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 90 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 91 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 92 } 93 } 94 95 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 96 { 97 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 98 MemoryRegion *system_memory = get_system_memory(); 99 uint8_t i; 100 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 101 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 102 Error *err = NULL; 103 104 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 105 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 106 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 107 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 108 if (err) { 109 error_propagate((errp), (err)); 110 return; 111 } 112 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 113 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 114 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 115 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 116 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 117 uint32_t addr = r->address; 118 int j; 119 120 sysbus_mmio_map(gic, r->region_index, addr); 121 122 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 123 MemoryRegion *alias = &s->gic_mr[i][j]; 124 125 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 126 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 127 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 128 memory_region_add_subregion(system_memory, addr, alias); 129 } 130 } 131 132 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 133 qemu_irq irq; 134 char *name; 135 136 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 137 "psci-conduit", &error_abort); 138 139 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 140 if (strcmp(name, boot_cpu)) { 141 /* Secondary CPUs start in PSCI powered-down state */ 142 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 143 "start-powered-off", &error_abort); 144 } else { 145 s->boot_cpu_ptr = &s->apu_cpu[i]; 146 } 147 148 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 149 "reset-cbar", &err); 150 if (err) { 151 error_propagate((errp), (err)); 152 return; 153 } 154 155 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 156 &err); 157 if (err) { 158 error_propagate((errp), (err)); 159 return; 160 } 161 162 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 163 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 164 ARM_CPU_IRQ)); 165 irq = qdev_get_gpio_in(DEVICE(&s->gic), 166 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 167 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 168 irq = qdev_get_gpio_in(DEVICE(&s->gic), 169 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 170 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 171 } 172 173 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 174 char *name; 175 176 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 177 if (strcmp(name, boot_cpu)) { 178 /* Secondary CPUs start in PSCI powered-down state */ 179 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 180 "start-powered-off", &error_abort); 181 } else { 182 s->boot_cpu_ptr = &s->rpu_cpu[i]; 183 } 184 185 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 186 &err); 187 if (err != NULL) { 188 error_propagate(errp, err); 189 return; 190 } 191 192 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 193 &err); 194 if (err) { 195 error_propagate((errp), (err)); 196 return; 197 } 198 } 199 200 if (!s->boot_cpu_ptr) { 201 error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu); 202 return; 203 } 204 205 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 206 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 207 } 208 209 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 210 NICInfo *nd = &nd_table[i]; 211 212 if (nd->used) { 213 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 214 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 215 } 216 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 217 if (err) { 218 error_propagate((errp), (err)); 219 return; 220 } 221 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 222 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 223 gic_spi[gem_intr[i]]); 224 } 225 226 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 227 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 228 if (err) { 229 error_propagate((errp), (err)); 230 return; 231 } 232 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 233 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 234 gic_spi[uart_intr[i]]); 235 } 236 } 237 238 static Property xlnx_zynqmp_props[] = { 239 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 240 DEFINE_PROP_END_OF_LIST() 241 }; 242 243 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 244 { 245 DeviceClass *dc = DEVICE_CLASS(oc); 246 247 dc->props = xlnx_zynqmp_props; 248 dc->realize = xlnx_zynqmp_realize; 249 } 250 251 static const TypeInfo xlnx_zynqmp_type_info = { 252 .name = TYPE_XLNX_ZYNQMP, 253 .parent = TYPE_DEVICE, 254 .instance_size = sizeof(XlnxZynqMPState), 255 .instance_init = xlnx_zynqmp_init, 256 .class_init = xlnx_zynqmp_class_init, 257 }; 258 259 static void xlnx_zynqmp_register_types(void) 260 { 261 type_register_static(&xlnx_zynqmp_type_info); 262 } 263 264 type_init(xlnx_zynqmp_register_types) 265