1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "hw/arm/xlnx-zynqmp.h" 19 #include "hw/intc/arm_gic_common.h" 20 #include "exec/address-spaces.h" 21 22 #define GIC_NUM_SPI_INTR 160 23 24 #define ARM_PHYS_TIMER_PPI 30 25 #define ARM_VIRT_TIMER_PPI 27 26 27 #define GIC_BASE_ADDR 0xf9000000 28 #define GIC_DIST_ADDR 0xf9010000 29 #define GIC_CPU_ADDR 0xf9020000 30 31 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 32 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 33 }; 34 35 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 36 57, 59, 61, 63, 37 }; 38 39 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 40 0xFF000000, 0xFF010000, 41 }; 42 43 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 44 21, 22, 45 }; 46 47 typedef struct XlnxZynqMPGICRegion { 48 int region_index; 49 uint32_t address; 50 } XlnxZynqMPGICRegion; 51 52 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 53 { .region_index = 0, .address = GIC_DIST_ADDR, }, 54 { .region_index = 1, .address = GIC_CPU_ADDR, }, 55 }; 56 57 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 58 { 59 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 60 } 61 62 static void xlnx_zynqmp_init(Object *obj) 63 { 64 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 65 int i; 66 67 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 68 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 69 "cortex-a53-" TYPE_ARM_CPU); 70 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 71 &error_abort); 72 } 73 74 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 75 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 76 "cortex-r5-" TYPE_ARM_CPU); 77 object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), 78 &error_abort); 79 } 80 81 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 82 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 83 84 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 85 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 86 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 87 } 88 89 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 90 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 91 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 92 } 93 } 94 95 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 96 { 97 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 98 MemoryRegion *system_memory = get_system_memory(); 99 uint8_t i; 100 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 101 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 102 Error *err = NULL; 103 104 /* Create the four OCM banks */ 105 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 106 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 107 108 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 109 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_abort); 110 vmstate_register_ram_global(&s->ocm_ram[i]); 111 memory_region_add_subregion(get_system_memory(), 112 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 113 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 114 &s->ocm_ram[i]); 115 116 g_free(ocm_name); 117 } 118 119 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 120 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 121 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 122 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 123 if (err) { 124 error_propagate((errp), (err)); 125 return; 126 } 127 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 128 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 129 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 130 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 131 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 132 uint32_t addr = r->address; 133 int j; 134 135 sysbus_mmio_map(gic, r->region_index, addr); 136 137 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 138 MemoryRegion *alias = &s->gic_mr[i][j]; 139 140 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 141 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 142 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 143 memory_region_add_subregion(system_memory, addr, alias); 144 } 145 } 146 147 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 148 qemu_irq irq; 149 char *name; 150 151 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 152 "psci-conduit", &error_abort); 153 154 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 155 if (strcmp(name, boot_cpu)) { 156 /* Secondary CPUs start in PSCI powered-down state */ 157 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 158 "start-powered-off", &error_abort); 159 } else { 160 s->boot_cpu_ptr = &s->apu_cpu[i]; 161 } 162 g_free(name); 163 164 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 165 "reset-cbar", &err); 166 if (err) { 167 error_propagate((errp), (err)); 168 return; 169 } 170 171 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 172 &err); 173 if (err) { 174 error_propagate((errp), (err)); 175 return; 176 } 177 178 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 179 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 180 ARM_CPU_IRQ)); 181 irq = qdev_get_gpio_in(DEVICE(&s->gic), 182 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 183 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 184 irq = qdev_get_gpio_in(DEVICE(&s->gic), 185 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 186 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 187 } 188 189 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 190 char *name; 191 192 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 193 if (strcmp(name, boot_cpu)) { 194 /* Secondary CPUs start in PSCI powered-down state */ 195 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 196 "start-powered-off", &error_abort); 197 } else { 198 s->boot_cpu_ptr = &s->rpu_cpu[i]; 199 } 200 g_free(name); 201 202 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 203 &err); 204 if (err != NULL) { 205 error_propagate(errp, err); 206 return; 207 } 208 209 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 210 &err); 211 if (err) { 212 error_propagate((errp), (err)); 213 return; 214 } 215 } 216 217 if (!s->boot_cpu_ptr) { 218 error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu); 219 return; 220 } 221 222 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 223 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 224 } 225 226 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 227 NICInfo *nd = &nd_table[i]; 228 229 if (nd->used) { 230 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 231 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 232 } 233 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 234 if (err) { 235 error_propagate((errp), (err)); 236 return; 237 } 238 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 239 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 240 gic_spi[gem_intr[i]]); 241 } 242 243 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 244 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 245 if (err) { 246 error_propagate((errp), (err)); 247 return; 248 } 249 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 250 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 251 gic_spi[uart_intr[i]]); 252 } 253 } 254 255 static Property xlnx_zynqmp_props[] = { 256 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 257 DEFINE_PROP_END_OF_LIST() 258 }; 259 260 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 261 { 262 DeviceClass *dc = DEVICE_CLASS(oc); 263 264 dc->props = xlnx_zynqmp_props; 265 dc->realize = xlnx_zynqmp_realize; 266 } 267 268 static const TypeInfo xlnx_zynqmp_type_info = { 269 .name = TYPE_XLNX_ZYNQMP, 270 .parent = TYPE_DEVICE, 271 .instance_size = sizeof(XlnxZynqMPState), 272 .instance_init = xlnx_zynqmp_init, 273 .class_init = xlnx_zynqmp_class_init, 274 }; 275 276 static void xlnx_zynqmp_register_types(void) 277 { 278 type_register_static(&xlnx_zynqmp_type_info); 279 } 280 281 type_init(xlnx_zynqmp_register_types) 282