1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "hw/arm/xlnx-zynqmp.h" 22 #include "hw/intc/arm_gic_common.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/boards.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/sysemu.h" 27 #include "kvm_arm.h" 28 29 #define GIC_NUM_SPI_INTR 160 30 31 #define ARM_PHYS_TIMER_PPI 30 32 #define ARM_VIRT_TIMER_PPI 27 33 #define ARM_HYP_TIMER_PPI 26 34 #define ARM_SEC_TIMER_PPI 29 35 #define GIC_MAINTENANCE_PPI 25 36 37 #define GEM_REVISION 0x40070106 38 39 #define GIC_BASE_ADDR 0xf9000000 40 #define GIC_DIST_ADDR 0xf9010000 41 #define GIC_CPU_ADDR 0xf9020000 42 #define GIC_VIFACE_ADDR 0xf9040000 43 #define GIC_VCPU_ADDR 0xf9060000 44 45 #define SATA_INTR 133 46 #define SATA_ADDR 0xFD0C0000 47 #define SATA_NUM_PORTS 2 48 49 #define QSPI_ADDR 0xff0f0000 50 #define LQSPI_ADDR 0xc0000000 51 #define QSPI_IRQ 15 52 #define QSPI_DMA_ADDR 0xff0f0800 53 #define NUM_QSPI_IRQ_LINES 2 54 55 #define CRF_ADDR 0xfd1a0000 56 #define CRF_IRQ 120 57 58 /* Serializer/Deserializer. */ 59 #define SERDES_ADDR 0xfd400000 60 #define SERDES_SIZE 0x20000 61 62 #define DP_ADDR 0xfd4a0000 63 #define DP_IRQ 113 64 65 #define DPDMA_ADDR 0xfd4c0000 66 #define DPDMA_IRQ 116 67 68 #define APU_ADDR 0xfd5c0000 69 #define APU_IRQ 153 70 71 #define IPI_ADDR 0xFF300000 72 #define IPI_IRQ 64 73 74 #define RTC_ADDR 0xffa60000 75 #define RTC_IRQ 26 76 77 #define BBRAM_ADDR 0xffcd0000 78 #define BBRAM_IRQ 11 79 80 #define EFUSE_ADDR 0xffcc0000 81 #define EFUSE_IRQ 87 82 83 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 84 85 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 86 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 87 }; 88 89 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 90 57, 59, 61, 63, 91 }; 92 93 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 94 0xFF000000, 0xFF010000, 95 }; 96 97 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 98 21, 22, 99 }; 100 101 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { 102 0xFF060000, 0xFF070000, 103 }; 104 105 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { 106 23, 24, 107 }; 108 109 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 110 0xFF160000, 0xFF170000, 111 }; 112 113 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 114 48, 49, 115 }; 116 117 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 118 0xFF040000, 0xFF050000, 119 }; 120 121 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 122 19, 20, 123 }; 124 125 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 126 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 127 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 128 }; 129 130 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 131 124, 125, 126, 127, 128, 129, 130, 131 132 }; 133 134 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 135 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 136 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 137 }; 138 139 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 140 77, 78, 79, 80, 81, 82, 83, 84 141 }; 142 143 typedef struct XlnxZynqMPGICRegion { 144 int region_index; 145 uint32_t address; 146 uint32_t offset; 147 bool virt; 148 } XlnxZynqMPGICRegion; 149 150 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 151 /* Distributor */ 152 { 153 .region_index = 0, 154 .address = GIC_DIST_ADDR, 155 .offset = 0, 156 .virt = false 157 }, 158 159 /* CPU interface */ 160 { 161 .region_index = 1, 162 .address = GIC_CPU_ADDR, 163 .offset = 0, 164 .virt = false 165 }, 166 { 167 .region_index = 1, 168 .address = GIC_CPU_ADDR + 0x10000, 169 .offset = 0x1000, 170 .virt = false 171 }, 172 173 /* Virtual interface */ 174 { 175 .region_index = 2, 176 .address = GIC_VIFACE_ADDR, 177 .offset = 0, 178 .virt = true 179 }, 180 181 /* Virtual CPU interface */ 182 { 183 .region_index = 3, 184 .address = GIC_VCPU_ADDR, 185 .offset = 0, 186 .virt = true 187 }, 188 { 189 .region_index = 3, 190 .address = GIC_VCPU_ADDR + 0x10000, 191 .offset = 0x1000, 192 .virt = true 193 }, 194 }; 195 196 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 197 { 198 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 199 } 200 201 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 202 const char *boot_cpu, Error **errp) 203 { 204 int i; 205 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 206 XLNX_ZYNQMP_NUM_RPU_CPUS); 207 208 if (num_rpus <= 0) { 209 /* Don't create rpu-cluster object if there's nothing to put in it */ 210 return; 211 } 212 213 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 214 TYPE_CPU_CLUSTER); 215 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 216 217 for (i = 0; i < num_rpus; i++) { 218 const char *name; 219 220 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 221 &s->rpu_cpu[i], 222 ARM_CPU_TYPE_NAME("cortex-r5f")); 223 224 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 225 if (strcmp(name, boot_cpu)) { 226 /* 227 * Secondary CPUs start in powered-down state. 228 */ 229 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 230 "start-powered-off", true, &error_abort); 231 } else { 232 s->boot_cpu_ptr = &s->rpu_cpu[i]; 233 } 234 235 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 236 &error_abort); 237 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { 238 return; 239 } 240 } 241 242 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 243 } 244 245 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) 246 { 247 SysBusDevice *sbd; 248 249 object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, 250 sizeof(s->bbram), TYPE_XLNX_BBRAM, 251 &error_fatal, 252 "crc-zpads", "1", 253 NULL); 254 sbd = SYS_BUS_DEVICE(&s->bbram); 255 256 sysbus_realize(sbd, &error_fatal); 257 sysbus_mmio_map(sbd, 0, BBRAM_ADDR); 258 sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); 259 } 260 261 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) 262 { 263 Object *bits = OBJECT(&s->efuse); 264 Object *ctrl = OBJECT(&s->efuse_ctrl); 265 SysBusDevice *sbd; 266 267 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, 268 TYPE_XLNX_ZYNQMP_EFUSE); 269 270 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 271 sizeof(s->efuse), 272 TYPE_XLNX_EFUSE, &error_abort, 273 "efuse-nr", "3", 274 "efuse-size", "2048", 275 NULL); 276 277 qdev_realize(DEVICE(bits), NULL, &error_abort); 278 object_property_set_link(ctrl, "efuse", bits, &error_abort); 279 280 sbd = SYS_BUS_DEVICE(ctrl); 281 sysbus_realize(sbd, &error_abort); 282 sysbus_mmio_map(sbd, 0, EFUSE_ADDR); 283 sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); 284 } 285 286 static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) 287 { 288 SysBusDevice *sbd; 289 int i; 290 291 object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, 292 TYPE_XLNX_ZYNQMP_APU_CTRL); 293 sbd = SYS_BUS_DEVICE(&s->apu_ctrl); 294 295 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 296 g_autofree gchar *name = g_strdup_printf("cpu%d", i); 297 298 object_property_set_link(OBJECT(&s->apu_ctrl), name, 299 OBJECT(&s->apu_cpu[i]), &error_abort); 300 } 301 302 sysbus_realize(sbd, &error_fatal); 303 sysbus_mmio_map(sbd, 0, APU_ADDR); 304 sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); 305 } 306 307 static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) 308 { 309 SysBusDevice *sbd; 310 311 object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); 312 sbd = SYS_BUS_DEVICE(&s->crf); 313 314 sysbus_realize(sbd, &error_fatal); 315 sysbus_mmio_map(sbd, 0, CRF_ADDR); 316 sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); 317 } 318 319 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) 320 { 321 static const struct UnimpInfo { 322 const char *name; 323 hwaddr base; 324 hwaddr size; 325 } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { 326 { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, 327 }; 328 unsigned int nr; 329 330 for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) { 331 const struct UnimpInfo *info = &unimp_areas[nr]; 332 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 333 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 334 335 assert(info->name && info->base && info->size > 0); 336 qdev_prop_set_string(dev, "name", info->name); 337 qdev_prop_set_uint64(dev, "size", info->size); 338 object_property_add_child(OBJECT(s), info->name, OBJECT(dev)); 339 340 sysbus_realize_and_unref(sbd, &error_fatal); 341 sysbus_mmio_map(sbd, 0, info->base); 342 } 343 } 344 345 static void xlnx_zynqmp_init(Object *obj) 346 { 347 MachineState *ms = MACHINE(qdev_get_machine()); 348 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 349 int i; 350 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 351 352 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 353 TYPE_CPU_CLUSTER); 354 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 355 356 for (i = 0; i < num_apus; i++) { 357 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 358 &s->apu_cpu[i], 359 ARM_CPU_TYPE_NAME("cortex-a53")); 360 } 361 362 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 363 364 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 365 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 366 } 367 368 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 369 object_initialize_child(obj, "uart[*]", &s->uart[i], 370 TYPE_CADENCE_UART); 371 } 372 373 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 374 object_initialize_child(obj, "can[*]", &s->can[i], 375 TYPE_XLNX_ZYNQMP_CAN); 376 } 377 378 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 379 380 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 381 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 382 TYPE_SYSBUS_SDHCI); 383 } 384 385 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 386 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 387 } 388 389 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 390 391 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 392 393 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 394 395 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 396 397 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 398 399 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 400 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 401 } 402 403 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 404 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 405 } 406 407 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA); 408 object_initialize_child(obj, "qspi-irq-orgate", 409 &s->qspi_irq_orgate, TYPE_OR_IRQ); 410 } 411 412 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 413 { 414 MachineState *ms = MACHINE(qdev_get_machine()); 415 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 416 MemoryRegion *system_memory = get_system_memory(); 417 uint8_t i; 418 uint64_t ram_size; 419 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 420 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 421 ram_addr_t ddr_low_size, ddr_high_size; 422 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 423 Error *err = NULL; 424 425 ram_size = memory_region_size(s->ddr_ram); 426 427 /* 428 * Create the DDR Memory Regions. User friendly checks should happen at 429 * the board level 430 */ 431 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 432 /* 433 * The RAM size is above the maximum available for the low DDR. 434 * Create the high DDR memory region as well. 435 */ 436 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 437 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 438 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 439 440 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 441 "ddr-ram-high", s->ddr_ram, ddr_low_size, 442 ddr_high_size); 443 memory_region_add_subregion(get_system_memory(), 444 XLNX_ZYNQMP_HIGH_RAM_START, 445 &s->ddr_ram_high); 446 } else { 447 /* RAM must be non-zero */ 448 assert(ram_size); 449 ddr_low_size = ram_size; 450 } 451 452 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 453 s->ddr_ram, 0, ddr_low_size); 454 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 455 456 /* Create the four OCM banks */ 457 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 458 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 459 460 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 461 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 462 memory_region_add_subregion(get_system_memory(), 463 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 464 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 465 &s->ocm_ram[i]); 466 467 g_free(ocm_name); 468 } 469 470 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 471 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 472 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 473 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 474 qdev_prop_set_bit(DEVICE(&s->gic), 475 "has-virtualization-extensions", s->virt); 476 477 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 478 479 /* Realize APUs before realizing the GIC. KVM requires this. */ 480 for (i = 0; i < num_apus; i++) { 481 const char *name; 482 483 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 484 if (strcmp(name, boot_cpu)) { 485 /* 486 * Secondary CPUs start in powered-down state. 487 */ 488 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 489 "start-powered-off", true, &error_abort); 490 } else { 491 s->boot_cpu_ptr = &s->apu_cpu[i]; 492 } 493 494 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 495 NULL); 496 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 497 NULL); 498 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 499 GIC_BASE_ADDR, &error_abort); 500 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 501 num_apus, &error_abort); 502 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { 503 return; 504 } 505 } 506 507 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 508 return; 509 } 510 511 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 512 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 513 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 514 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 515 MemoryRegion *mr; 516 uint32_t addr = r->address; 517 int j; 518 519 if (r->virt && !s->virt) { 520 continue; 521 } 522 523 mr = sysbus_mmio_get_region(gic, r->region_index); 524 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 525 MemoryRegion *alias = &s->gic_mr[i][j]; 526 527 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 528 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 529 memory_region_add_subregion(system_memory, addr, alias); 530 531 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 532 } 533 } 534 535 for (i = 0; i < num_apus; i++) { 536 qemu_irq irq; 537 538 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 539 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 540 ARM_CPU_IRQ)); 541 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 542 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 543 ARM_CPU_FIQ)); 544 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 545 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 546 ARM_CPU_VIRQ)); 547 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 548 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 549 ARM_CPU_VFIQ)); 550 irq = qdev_get_gpio_in(DEVICE(&s->gic), 551 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 552 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 553 irq = qdev_get_gpio_in(DEVICE(&s->gic), 554 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 555 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 556 irq = qdev_get_gpio_in(DEVICE(&s->gic), 557 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 558 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 559 irq = qdev_get_gpio_in(DEVICE(&s->gic), 560 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 561 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 562 563 if (s->virt) { 564 irq = qdev_get_gpio_in(DEVICE(&s->gic), 565 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 566 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 567 } 568 } 569 570 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 571 if (err) { 572 error_propagate(errp, err); 573 return; 574 } 575 576 if (!s->boot_cpu_ptr) { 577 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 578 return; 579 } 580 581 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 582 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 583 } 584 585 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 586 NICInfo *nd = &nd_table[i]; 587 588 /* FIXME use qdev NIC properties instead of nd_table[] */ 589 if (nd->used) { 590 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 591 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 592 } 593 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 594 &error_abort); 595 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, 596 &error_abort); 597 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 598 &error_abort); 599 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { 600 return; 601 } 602 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 603 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 604 gic_spi[gem_intr[i]]); 605 } 606 607 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 608 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 609 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 610 return; 611 } 612 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 613 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 614 gic_spi[uart_intr[i]]); 615 } 616 617 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 618 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", 619 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); 620 621 object_property_set_link(OBJECT(&s->can[i]), "canbus", 622 OBJECT(s->canbus[i]), &error_fatal); 623 624 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); 625 if (err) { 626 error_propagate(errp, err); 627 return; 628 } 629 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); 630 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, 631 gic_spi[can_intr[i]]); 632 } 633 634 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 635 &error_abort); 636 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 637 return; 638 } 639 640 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 641 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 642 643 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 644 char *bus_name; 645 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 646 Object *sdhci = OBJECT(&s->sdhci[i]); 647 648 /* 649 * Compatible with: 650 * - SD Host Controller Specification Version 3.00 651 * - SDIO Specification Version 3.0 652 * - eMMC Specification Version 4.51 653 */ 654 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { 655 return; 656 } 657 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, 658 errp)) { 659 return; 660 } 661 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { 662 return; 663 } 664 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { 665 return; 666 } 667 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 668 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 669 670 /* Alias controller SD bus to the SoC itself */ 671 bus_name = g_strdup_printf("sd-bus%d", i); 672 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 673 g_free(bus_name); 674 } 675 676 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 677 gchar *bus_name; 678 679 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 680 return; 681 } 682 683 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 684 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 685 gic_spi[spi_intr[i]]); 686 687 /* Alias controller SPI bus to the SoC itself */ 688 bus_name = g_strdup_printf("spi%d", i); 689 object_property_add_alias(OBJECT(s), bus_name, 690 OBJECT(&s->spi[i]), "spi0"); 691 g_free(bus_name); 692 } 693 694 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { 695 return; 696 } 697 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 698 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 699 700 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { 701 return; 702 } 703 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 704 &error_abort); 705 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 706 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 707 708 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { 709 return; 710 } 711 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 712 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 713 714 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 715 return; 716 } 717 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 718 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 719 720 xlnx_zynqmp_create_bbram(s, gic_spi); 721 xlnx_zynqmp_create_efuse(s, gic_spi); 722 xlnx_zynqmp_create_apu_ctrl(s, gic_spi); 723 xlnx_zynqmp_create_crf(s, gic_spi); 724 xlnx_zynqmp_create_unimp_mmio(s); 725 726 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 727 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, 728 errp)) { 729 return; 730 } 731 if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", 732 OBJECT(system_memory), errp)) { 733 return; 734 } 735 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { 736 return; 737 } 738 739 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 740 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 741 gic_spi[gdma_ch_intr[i]]); 742 } 743 744 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 745 if (!object_property_set_link(OBJECT(&s->adma[i]), "dma", 746 OBJECT(system_memory), errp)) { 747 return; 748 } 749 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { 750 return; 751 } 752 753 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 754 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 755 gic_spi[adma_ch_intr[i]]); 756 } 757 758 object_property_set_int(OBJECT(&s->qspi_irq_orgate), 759 "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal); 760 qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal); 761 qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]); 762 763 if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma", 764 OBJECT(system_memory), errp)) { 765 return; 766 } 767 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { 768 return; 769 } 770 771 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); 772 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, 773 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); 774 775 if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", 776 OBJECT(&s->qspi_dma), errp)) { 777 return; 778 } 779 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { 780 return; 781 } 782 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 783 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 784 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, 785 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1)); 786 787 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 788 g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i); 789 g_autofree gchar *target_bus = g_strdup_printf("spi%d", i); 790 791 /* Alias controller SPI bus to the SoC itself */ 792 object_property_add_alias(OBJECT(s), bus_name, 793 OBJECT(&s->qspi), target_bus); 794 } 795 } 796 797 static Property xlnx_zynqmp_props[] = { 798 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 799 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 800 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 801 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 802 MemoryRegion *), 803 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, 804 CanBusState *), 805 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, 806 CanBusState *), 807 DEFINE_PROP_END_OF_LIST() 808 }; 809 810 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 811 { 812 DeviceClass *dc = DEVICE_CLASS(oc); 813 814 device_class_set_props(dc, xlnx_zynqmp_props); 815 dc->realize = xlnx_zynqmp_realize; 816 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 817 dc->user_creatable = false; 818 } 819 820 static const TypeInfo xlnx_zynqmp_type_info = { 821 .name = TYPE_XLNX_ZYNQMP, 822 .parent = TYPE_DEVICE, 823 .instance_size = sizeof(XlnxZynqMPState), 824 .instance_init = xlnx_zynqmp_init, 825 .class_init = xlnx_zynqmp_class_init, 826 }; 827 828 static void xlnx_zynqmp_register_types(void) 829 { 830 type_register_static(&xlnx_zynqmp_type_info); 831 } 832 833 type_init(xlnx_zynqmp_register_types) 834