1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 33 #define GEM_REVISION 0x40070106 34 35 #define GIC_BASE_ADDR 0xf9000000 36 #define GIC_DIST_ADDR 0xf9010000 37 #define GIC_CPU_ADDR 0xf9020000 38 39 #define SATA_INTR 133 40 #define SATA_ADDR 0xFD0C0000 41 #define SATA_NUM_PORTS 2 42 43 #define DP_ADDR 0xfd4a0000 44 #define DP_IRQ 113 45 46 #define DPDMA_ADDR 0xfd4c0000 47 #define DPDMA_IRQ 116 48 49 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 50 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 51 }; 52 53 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 54 57, 59, 61, 63, 55 }; 56 57 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 58 0xFF000000, 0xFF010000, 59 }; 60 61 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 62 21, 22, 63 }; 64 65 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 66 0xFF160000, 0xFF170000, 67 }; 68 69 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 70 48, 49, 71 }; 72 73 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 74 0xFF040000, 0xFF050000, 75 }; 76 77 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 78 19, 20, 79 }; 80 81 typedef struct XlnxZynqMPGICRegion { 82 int region_index; 83 uint32_t address; 84 } XlnxZynqMPGICRegion; 85 86 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 87 { .region_index = 0, .address = GIC_DIST_ADDR, }, 88 { .region_index = 1, .address = GIC_CPU_ADDR, }, 89 }; 90 91 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 92 { 93 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 94 } 95 96 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 97 Error **errp) 98 { 99 Error *err = NULL; 100 int i; 101 102 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 103 char *name; 104 105 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 106 "cortex-r5-" TYPE_ARM_CPU); 107 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 108 OBJECT(&s->rpu_cpu[i]), &error_abort); 109 110 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 111 if (strcmp(name, boot_cpu)) { 112 /* Secondary CPUs start in PSCI powered-down state */ 113 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 114 "start-powered-off", &error_abort); 115 } else { 116 s->boot_cpu_ptr = &s->rpu_cpu[i]; 117 } 118 g_free(name); 119 120 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 121 &error_abort); 122 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 123 &err); 124 if (err) { 125 error_propagate(errp, err); 126 return; 127 } 128 } 129 } 130 131 static void xlnx_zynqmp_init(Object *obj) 132 { 133 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 134 int i; 135 136 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 137 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 138 "cortex-a53-" TYPE_ARM_CPU); 139 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 140 &error_abort); 141 } 142 143 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 144 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 145 146 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 147 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 148 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 149 } 150 151 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 152 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 153 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 154 } 155 156 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 157 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 158 159 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 160 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 161 TYPE_SYSBUS_SDHCI); 162 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 163 sysbus_get_default()); 164 } 165 166 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 167 object_initialize(&s->spi[i], sizeof(s->spi[i]), 168 TYPE_XILINX_SPIPS); 169 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 170 } 171 172 object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); 173 qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); 174 175 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); 176 qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); 177 } 178 179 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 180 { 181 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 182 MemoryRegion *system_memory = get_system_memory(); 183 uint8_t i; 184 uint64_t ram_size; 185 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 186 ram_addr_t ddr_low_size, ddr_high_size; 187 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 188 Error *err = NULL; 189 190 ram_size = memory_region_size(s->ddr_ram); 191 192 /* Create the DDR Memory Regions. User friendly checks should happen at 193 * the board level 194 */ 195 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 196 /* The RAM size is above the maximum available for the low DDR. 197 * Create the high DDR memory region as well. 198 */ 199 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 200 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 201 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 202 203 memory_region_init_alias(&s->ddr_ram_high, NULL, 204 "ddr-ram-high", s->ddr_ram, 205 ddr_low_size, ddr_high_size); 206 memory_region_add_subregion(get_system_memory(), 207 XLNX_ZYNQMP_HIGH_RAM_START, 208 &s->ddr_ram_high); 209 } else { 210 /* RAM must be non-zero */ 211 assert(ram_size); 212 ddr_low_size = ram_size; 213 } 214 215 memory_region_init_alias(&s->ddr_ram_low, NULL, 216 "ddr-ram-low", s->ddr_ram, 217 0, ddr_low_size); 218 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 219 220 /* Create the four OCM banks */ 221 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 222 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 223 224 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 225 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 226 memory_region_add_subregion(get_system_memory(), 227 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 228 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 229 &s->ocm_ram[i]); 230 231 g_free(ocm_name); 232 } 233 234 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 235 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 236 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 237 238 /* Realize APUs before realizing the GIC. KVM requires this. */ 239 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 240 char *name; 241 242 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 243 "psci-conduit", &error_abort); 244 245 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 246 if (strcmp(name, boot_cpu)) { 247 /* Secondary CPUs start in PSCI powered-down state */ 248 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 249 "start-powered-off", &error_abort); 250 } else { 251 s->boot_cpu_ptr = &s->apu_cpu[i]; 252 } 253 g_free(name); 254 255 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 256 s->secure, "has_el3", NULL); 257 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 258 false, "has_el2", NULL); 259 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 260 "reset-cbar", &error_abort); 261 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 262 &err); 263 if (err) { 264 error_propagate(errp, err); 265 return; 266 } 267 } 268 269 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 270 if (err) { 271 error_propagate(errp, err); 272 return; 273 } 274 275 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 276 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 277 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 278 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 279 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 280 uint32_t addr = r->address; 281 int j; 282 283 sysbus_mmio_map(gic, r->region_index, addr); 284 285 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 286 MemoryRegion *alias = &s->gic_mr[i][j]; 287 288 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 289 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 290 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 291 memory_region_add_subregion(system_memory, addr, alias); 292 } 293 } 294 295 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 296 qemu_irq irq; 297 298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 299 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 300 ARM_CPU_IRQ)); 301 irq = qdev_get_gpio_in(DEVICE(&s->gic), 302 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 303 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 304 irq = qdev_get_gpio_in(DEVICE(&s->gic), 305 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 306 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 307 } 308 309 if (s->has_rpu) { 310 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 311 if (err) { 312 error_propagate(errp, err); 313 return; 314 } 315 } 316 317 if (!s->boot_cpu_ptr) { 318 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 319 return; 320 } 321 322 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 323 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 324 } 325 326 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 327 NICInfo *nd = &nd_table[i]; 328 329 if (nd->used) { 330 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 331 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 332 } 333 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 334 &error_abort); 335 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 336 &error_abort); 337 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 338 if (err) { 339 error_propagate(errp, err); 340 return; 341 } 342 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 344 gic_spi[gem_intr[i]]); 345 } 346 347 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 348 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); 349 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 350 if (err) { 351 error_propagate(errp, err); 352 return; 353 } 354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 356 gic_spi[uart_intr[i]]); 357 } 358 359 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 360 &error_abort); 361 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 362 if (err) { 363 error_propagate(errp, err); 364 return; 365 } 366 367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 368 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 369 370 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 371 char *bus_name; 372 373 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 374 "realized", &err); 375 if (err) { 376 error_propagate(errp, err); 377 return; 378 } 379 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 380 sdhci_addr[i]); 381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 382 gic_spi[sdhci_intr[i]]); 383 /* Alias controller SD bus to the SoC itself */ 384 bus_name = g_strdup_printf("sd-bus%d", i); 385 object_property_add_alias(OBJECT(s), bus_name, 386 OBJECT(&s->sdhci[i]), "sd-bus", 387 &error_abort); 388 g_free(bus_name); 389 } 390 391 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 392 gchar *bus_name; 393 394 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 395 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 398 gic_spi[spi_intr[i]]); 399 400 /* Alias controller SPI bus to the SoC itself */ 401 bus_name = g_strdup_printf("spi%d", i); 402 object_property_add_alias(OBJECT(s), bus_name, 403 OBJECT(&s->spi[i]), "spi0", 404 &error_abort); 405 g_free(bus_name); 406 } 407 408 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 409 if (err) { 410 error_propagate(errp, err); 411 return; 412 } 413 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 414 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 415 416 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 417 if (err) { 418 error_propagate(errp, err); 419 return; 420 } 421 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 422 &error_abort); 423 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 424 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 425 } 426 427 static Property xlnx_zynqmp_props[] = { 428 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 429 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 430 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 431 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 432 MemoryRegion *), 433 DEFINE_PROP_END_OF_LIST() 434 }; 435 436 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 437 { 438 DeviceClass *dc = DEVICE_CLASS(oc); 439 440 dc->props = xlnx_zynqmp_props; 441 dc->realize = xlnx_zynqmp_realize; 442 } 443 444 static const TypeInfo xlnx_zynqmp_type_info = { 445 .name = TYPE_XLNX_ZYNQMP, 446 .parent = TYPE_DEVICE, 447 .instance_size = sizeof(XlnxZynqMPState), 448 .instance_init = xlnx_zynqmp_init, 449 .class_init = xlnx_zynqmp_class_init, 450 }; 451 452 static void xlnx_zynqmp_register_types(void) 453 { 454 type_register_static(&xlnx_zynqmp_type_info); 455 } 456 457 type_init(xlnx_zynqmp_register_types) 458