1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 33 #define GIC_BASE_ADDR 0xf9000000 34 #define GIC_DIST_ADDR 0xf9010000 35 #define GIC_CPU_ADDR 0xf9020000 36 37 #define SATA_INTR 133 38 #define SATA_ADDR 0xFD0C0000 39 #define SATA_NUM_PORTS 2 40 41 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 42 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 43 }; 44 45 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 46 57, 59, 61, 63, 47 }; 48 49 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 50 0xFF000000, 0xFF010000, 51 }; 52 53 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 54 21, 22, 55 }; 56 57 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 58 0xFF160000, 0xFF170000, 59 }; 60 61 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 62 48, 49, 63 }; 64 65 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 66 0xFF040000, 0xFF050000, 67 }; 68 69 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 70 19, 20, 71 }; 72 73 typedef struct XlnxZynqMPGICRegion { 74 int region_index; 75 uint32_t address; 76 } XlnxZynqMPGICRegion; 77 78 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 79 { .region_index = 0, .address = GIC_DIST_ADDR, }, 80 { .region_index = 1, .address = GIC_CPU_ADDR, }, 81 }; 82 83 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 84 { 85 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 86 } 87 88 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 89 Error **errp) 90 { 91 Error *err = NULL; 92 int i; 93 94 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 95 char *name; 96 97 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 98 "cortex-r5-" TYPE_ARM_CPU); 99 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 100 OBJECT(&s->rpu_cpu[i]), &error_abort); 101 102 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 103 if (strcmp(name, boot_cpu)) { 104 /* Secondary CPUs start in PSCI powered-down state */ 105 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 106 "start-powered-off", &error_abort); 107 } else { 108 s->boot_cpu_ptr = &s->rpu_cpu[i]; 109 } 110 g_free(name); 111 112 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 113 &error_abort); 114 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 115 &err); 116 if (err) { 117 error_propagate(errp, err); 118 return; 119 } 120 } 121 } 122 123 static void xlnx_zynqmp_init(Object *obj) 124 { 125 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 126 int i; 127 128 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 129 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 130 "cortex-a53-" TYPE_ARM_CPU); 131 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 132 &error_abort); 133 } 134 135 object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, 136 (Object **)&s->ddr_ram, 137 qdev_prop_allow_set_link_before_realize, 138 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 139 140 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 141 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 142 143 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 144 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 145 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 146 } 147 148 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 149 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 150 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 151 } 152 153 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 154 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 155 156 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 157 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 158 TYPE_SYSBUS_SDHCI); 159 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 160 sysbus_get_default()); 161 } 162 163 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 164 object_initialize(&s->spi[i], sizeof(s->spi[i]), 165 TYPE_XILINX_SPIPS); 166 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 167 } 168 } 169 170 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 171 { 172 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 173 MemoryRegion *system_memory = get_system_memory(); 174 uint8_t i; 175 uint64_t ram_size; 176 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 177 ram_addr_t ddr_low_size, ddr_high_size; 178 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 179 Error *err = NULL; 180 181 ram_size = memory_region_size(s->ddr_ram); 182 183 /* Create the DDR Memory Regions. User friendly checks should happen at 184 * the board level 185 */ 186 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 187 /* The RAM size is above the maximum available for the low DDR. 188 * Create the high DDR memory region as well. 189 */ 190 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 191 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 192 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 193 194 memory_region_init_alias(&s->ddr_ram_high, NULL, 195 "ddr-ram-high", s->ddr_ram, 196 ddr_low_size, ddr_high_size); 197 memory_region_add_subregion(get_system_memory(), 198 XLNX_ZYNQMP_HIGH_RAM_START, 199 &s->ddr_ram_high); 200 } else { 201 /* RAM must be non-zero */ 202 assert(ram_size); 203 ddr_low_size = ram_size; 204 } 205 206 memory_region_init_alias(&s->ddr_ram_low, NULL, 207 "ddr-ram-low", s->ddr_ram, 208 0, ddr_low_size); 209 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 210 211 /* Create the four OCM banks */ 212 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 213 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 214 215 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 216 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 217 vmstate_register_ram_global(&s->ocm_ram[i]); 218 memory_region_add_subregion(get_system_memory(), 219 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 220 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 221 &s->ocm_ram[i]); 222 223 g_free(ocm_name); 224 } 225 226 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 227 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 228 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 229 230 /* Realize APUs before realizing the GIC. KVM requires this. */ 231 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 232 char *name; 233 234 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 235 "psci-conduit", &error_abort); 236 237 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 238 if (strcmp(name, boot_cpu)) { 239 /* Secondary CPUs start in PSCI powered-down state */ 240 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 241 "start-powered-off", &error_abort); 242 } else { 243 s->boot_cpu_ptr = &s->apu_cpu[i]; 244 } 245 g_free(name); 246 247 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 248 s->secure, "has_el3", NULL); 249 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 250 "reset-cbar", &error_abort); 251 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 252 &err); 253 if (err) { 254 error_propagate(errp, err); 255 return; 256 } 257 } 258 259 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 260 if (err) { 261 error_propagate(errp, err); 262 return; 263 } 264 265 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 266 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 267 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 268 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 269 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 270 uint32_t addr = r->address; 271 int j; 272 273 sysbus_mmio_map(gic, r->region_index, addr); 274 275 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 276 MemoryRegion *alias = &s->gic_mr[i][j]; 277 278 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 279 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 280 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 281 memory_region_add_subregion(system_memory, addr, alias); 282 } 283 } 284 285 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 286 qemu_irq irq; 287 288 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 289 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 290 ARM_CPU_IRQ)); 291 irq = qdev_get_gpio_in(DEVICE(&s->gic), 292 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 293 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 294 irq = qdev_get_gpio_in(DEVICE(&s->gic), 295 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 296 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 297 } 298 299 if (s->has_rpu) { 300 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 301 if (err) { 302 error_propagate(errp, err); 303 return; 304 } 305 } 306 307 if (!s->boot_cpu_ptr) { 308 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 309 return; 310 } 311 312 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 313 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 314 } 315 316 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 317 NICInfo *nd = &nd_table[i]; 318 319 if (nd->used) { 320 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 321 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 322 } 323 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 324 if (err) { 325 error_propagate(errp, err); 326 return; 327 } 328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 330 gic_spi[gem_intr[i]]); 331 } 332 333 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 334 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); 335 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 336 if (err) { 337 error_propagate(errp, err); 338 return; 339 } 340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 342 gic_spi[uart_intr[i]]); 343 } 344 345 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 346 &error_abort); 347 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 348 if (err) { 349 error_propagate(errp, err); 350 return; 351 } 352 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 355 356 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 357 char *bus_name; 358 359 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 360 "realized", &err); 361 if (err) { 362 error_propagate(errp, err); 363 return; 364 } 365 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 366 sdhci_addr[i]); 367 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 368 gic_spi[sdhci_intr[i]]); 369 /* Alias controller SD bus to the SoC itself */ 370 bus_name = g_strdup_printf("sd-bus%d", i); 371 object_property_add_alias(OBJECT(s), bus_name, 372 OBJECT(&s->sdhci[i]), "sd-bus", 373 &error_abort); 374 g_free(bus_name); 375 } 376 377 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 378 gchar *bus_name; 379 380 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 381 382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 384 gic_spi[spi_intr[i]]); 385 386 /* Alias controller SPI bus to the SoC itself */ 387 bus_name = g_strdup_printf("spi%d", i); 388 object_property_add_alias(OBJECT(s), bus_name, 389 OBJECT(&s->spi[i]), "spi0", 390 &error_abort); 391 g_free(bus_name); 392 } 393 } 394 395 static Property xlnx_zynqmp_props[] = { 396 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 397 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 398 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 399 DEFINE_PROP_END_OF_LIST() 400 }; 401 402 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 403 { 404 DeviceClass *dc = DEVICE_CLASS(oc); 405 406 dc->props = xlnx_zynqmp_props; 407 dc->realize = xlnx_zynqmp_realize; 408 409 /* 410 * Reason: creates an ARM CPU, thus use after free(), see 411 * arm_cpu_class_init() 412 */ 413 dc->cannot_destroy_with_object_finalize_yet = true; 414 } 415 416 static const TypeInfo xlnx_zynqmp_type_info = { 417 .name = TYPE_XLNX_ZYNQMP, 418 .parent = TYPE_DEVICE, 419 .instance_size = sizeof(XlnxZynqMPState), 420 .instance_init = xlnx_zynqmp_init, 421 .class_init = xlnx_zynqmp_class_init, 422 }; 423 424 static void xlnx_zynqmp_register_types(void) 425 { 426 type_register_static(&xlnx_zynqmp_type_info); 427 } 428 429 type_init(xlnx_zynqmp_register_types) 430