1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 33 #define GEM_REVISION 0x40070106 34 35 #define GIC_BASE_ADDR 0xf9000000 36 #define GIC_DIST_ADDR 0xf9010000 37 #define GIC_CPU_ADDR 0xf9020000 38 39 #define SATA_INTR 133 40 #define SATA_ADDR 0xFD0C0000 41 #define SATA_NUM_PORTS 2 42 43 #define DP_ADDR 0xfd4a0000 44 #define DP_IRQ 113 45 46 #define DPDMA_ADDR 0xfd4c0000 47 #define DPDMA_IRQ 116 48 49 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 50 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 51 }; 52 53 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 54 57, 59, 61, 63, 55 }; 56 57 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 58 0xFF000000, 0xFF010000, 59 }; 60 61 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 62 21, 22, 63 }; 64 65 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 66 0xFF160000, 0xFF170000, 67 }; 68 69 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 70 48, 49, 71 }; 72 73 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 74 0xFF040000, 0xFF050000, 75 }; 76 77 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 78 19, 20, 79 }; 80 81 typedef struct XlnxZynqMPGICRegion { 82 int region_index; 83 uint32_t address; 84 } XlnxZynqMPGICRegion; 85 86 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 87 { .region_index = 0, .address = GIC_DIST_ADDR, }, 88 { .region_index = 1, .address = GIC_CPU_ADDR, }, 89 }; 90 91 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 92 { 93 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 94 } 95 96 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 97 Error **errp) 98 { 99 Error *err = NULL; 100 int i; 101 int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); 102 103 for (i = 0; i < num_rpus; i++) { 104 char *name; 105 106 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 107 "cortex-r5-" TYPE_ARM_CPU); 108 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 109 OBJECT(&s->rpu_cpu[i]), &error_abort); 110 111 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 112 if (strcmp(name, boot_cpu)) { 113 /* Secondary CPUs start in PSCI powered-down state */ 114 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 115 "start-powered-off", &error_abort); 116 } else { 117 s->boot_cpu_ptr = &s->rpu_cpu[i]; 118 } 119 g_free(name); 120 121 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 122 &error_abort); 123 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 124 &err); 125 if (err) { 126 error_propagate(errp, err); 127 return; 128 } 129 } 130 } 131 132 static void xlnx_zynqmp_init(Object *obj) 133 { 134 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 135 int i; 136 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 137 138 for (i = 0; i < num_apus; i++) { 139 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 140 "cortex-a53-" TYPE_ARM_CPU); 141 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 142 &error_abort); 143 } 144 145 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 146 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 147 148 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 149 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 150 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 151 } 152 153 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 154 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 155 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 156 } 157 158 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 159 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 160 161 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 162 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 163 TYPE_SYSBUS_SDHCI); 164 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 165 sysbus_get_default()); 166 } 167 168 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 169 object_initialize(&s->spi[i], sizeof(s->spi[i]), 170 TYPE_XILINX_SPIPS); 171 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 172 } 173 174 object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); 175 qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); 176 177 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); 178 qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); 179 } 180 181 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 182 { 183 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 184 MemoryRegion *system_memory = get_system_memory(); 185 uint8_t i; 186 uint64_t ram_size; 187 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 188 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 189 ram_addr_t ddr_low_size, ddr_high_size; 190 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 191 Error *err = NULL; 192 193 ram_size = memory_region_size(s->ddr_ram); 194 195 /* Create the DDR Memory Regions. User friendly checks should happen at 196 * the board level 197 */ 198 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 199 /* The RAM size is above the maximum available for the low DDR. 200 * Create the high DDR memory region as well. 201 */ 202 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 203 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 204 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 205 206 memory_region_init_alias(&s->ddr_ram_high, NULL, 207 "ddr-ram-high", s->ddr_ram, 208 ddr_low_size, ddr_high_size); 209 memory_region_add_subregion(get_system_memory(), 210 XLNX_ZYNQMP_HIGH_RAM_START, 211 &s->ddr_ram_high); 212 } else { 213 /* RAM must be non-zero */ 214 assert(ram_size); 215 ddr_low_size = ram_size; 216 } 217 218 memory_region_init_alias(&s->ddr_ram_low, NULL, 219 "ddr-ram-low", s->ddr_ram, 220 0, ddr_low_size); 221 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 222 223 /* Create the four OCM banks */ 224 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 225 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 226 227 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 228 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 229 memory_region_add_subregion(get_system_memory(), 230 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 231 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 232 &s->ocm_ram[i]); 233 234 g_free(ocm_name); 235 } 236 237 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 238 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 239 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 240 241 /* Realize APUs before realizing the GIC. KVM requires this. */ 242 for (i = 0; i < num_apus; i++) { 243 char *name; 244 245 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 246 "psci-conduit", &error_abort); 247 248 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 249 if (strcmp(name, boot_cpu)) { 250 /* Secondary CPUs start in PSCI powered-down state */ 251 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 252 "start-powered-off", &error_abort); 253 } else { 254 s->boot_cpu_ptr = &s->apu_cpu[i]; 255 } 256 g_free(name); 257 258 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 259 s->secure, "has_el3", NULL); 260 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 261 s->virt, "has_el2", NULL); 262 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 263 "reset-cbar", &error_abort); 264 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 265 &err); 266 if (err) { 267 error_propagate(errp, err); 268 return; 269 } 270 } 271 272 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 273 if (err) { 274 error_propagate(errp, err); 275 return; 276 } 277 278 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 279 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 280 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 281 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 282 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 283 uint32_t addr = r->address; 284 int j; 285 286 sysbus_mmio_map(gic, r->region_index, addr); 287 288 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 289 MemoryRegion *alias = &s->gic_mr[i][j]; 290 291 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 292 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 293 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 294 memory_region_add_subregion(system_memory, addr, alias); 295 } 296 } 297 298 for (i = 0; i < num_apus; i++) { 299 qemu_irq irq; 300 301 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 302 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 303 ARM_CPU_IRQ)); 304 irq = qdev_get_gpio_in(DEVICE(&s->gic), 305 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 306 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 307 irq = qdev_get_gpio_in(DEVICE(&s->gic), 308 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 309 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 310 } 311 312 if (s->has_rpu) { 313 info_report("The 'has_rpu' property is no longer required, to use the " 314 "RPUs just use -smp 6."); 315 } 316 317 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 318 if (err) { 319 error_propagate(errp, err); 320 return; 321 } 322 323 if (!s->boot_cpu_ptr) { 324 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 325 return; 326 } 327 328 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 329 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 330 } 331 332 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 333 NICInfo *nd = &nd_table[i]; 334 335 if (nd->used) { 336 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 337 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 338 } 339 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 340 &error_abort); 341 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 342 &error_abort); 343 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 344 if (err) { 345 error_propagate(errp, err); 346 return; 347 } 348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 349 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 350 gic_spi[gem_intr[i]]); 351 } 352 353 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 354 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); 355 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 356 if (err) { 357 error_propagate(errp, err); 358 return; 359 } 360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 362 gic_spi[uart_intr[i]]); 363 } 364 365 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 366 &error_abort); 367 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 368 if (err) { 369 error_propagate(errp, err); 370 return; 371 } 372 373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 374 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 375 376 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 377 char *bus_name; 378 379 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 380 "realized", &err); 381 if (err) { 382 error_propagate(errp, err); 383 return; 384 } 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 386 sdhci_addr[i]); 387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 388 gic_spi[sdhci_intr[i]]); 389 /* Alias controller SD bus to the SoC itself */ 390 bus_name = g_strdup_printf("sd-bus%d", i); 391 object_property_add_alias(OBJECT(s), bus_name, 392 OBJECT(&s->sdhci[i]), "sd-bus", 393 &error_abort); 394 g_free(bus_name); 395 } 396 397 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 398 gchar *bus_name; 399 400 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 401 402 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 404 gic_spi[spi_intr[i]]); 405 406 /* Alias controller SPI bus to the SoC itself */ 407 bus_name = g_strdup_printf("spi%d", i); 408 object_property_add_alias(OBJECT(s), bus_name, 409 OBJECT(&s->spi[i]), "spi0", 410 &error_abort); 411 g_free(bus_name); 412 } 413 414 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 415 if (err) { 416 error_propagate(errp, err); 417 return; 418 } 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 421 422 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 423 if (err) { 424 error_propagate(errp, err); 425 return; 426 } 427 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 428 &error_abort); 429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 431 } 432 433 static Property xlnx_zynqmp_props[] = { 434 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 435 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 436 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 437 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 438 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 439 MemoryRegion *), 440 DEFINE_PROP_END_OF_LIST() 441 }; 442 443 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 444 { 445 DeviceClass *dc = DEVICE_CLASS(oc); 446 447 dc->props = xlnx_zynqmp_props; 448 dc->realize = xlnx_zynqmp_realize; 449 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 450 dc->user_creatable = false; 451 } 452 453 static const TypeInfo xlnx_zynqmp_type_info = { 454 .name = TYPE_XLNX_ZYNQMP, 455 .parent = TYPE_DEVICE, 456 .instance_size = sizeof(XlnxZynqMPState), 457 .instance_init = xlnx_zynqmp_init, 458 .class_init = xlnx_zynqmp_class_init, 459 }; 460 461 static void xlnx_zynqmp_register_types(void) 462 { 463 type_register_static(&xlnx_zynqmp_type_info); 464 } 465 466 type_init(xlnx_zynqmp_register_types) 467