xref: /openbmc/qemu/hw/arm/xlnx-zynqmp.c (revision 75bbe5e5)
1 /*
2  * Xilinx Zynq MPSoC emulation
3  *
4  * Copyright (C) 2015 Xilinx Inc
5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/intc/arm_gic_common.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/boards.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/sysemu.h"
27 #include "kvm_arm.h"
28 
29 #define GIC_NUM_SPI_INTR 160
30 
31 #define ARM_PHYS_TIMER_PPI  30
32 #define ARM_VIRT_TIMER_PPI  27
33 #define ARM_HYP_TIMER_PPI   26
34 #define ARM_SEC_TIMER_PPI   29
35 #define GIC_MAINTENANCE_PPI 25
36 
37 #define GEM_REVISION        0x40070106
38 
39 #define GIC_BASE_ADDR       0xf9000000
40 #define GIC_DIST_ADDR       0xf9010000
41 #define GIC_CPU_ADDR        0xf9020000
42 #define GIC_VIFACE_ADDR     0xf9040000
43 #define GIC_VCPU_ADDR       0xf9060000
44 
45 #define SATA_INTR           133
46 #define SATA_ADDR           0xFD0C0000
47 #define SATA_NUM_PORTS      2
48 
49 #define QSPI_ADDR           0xff0f0000
50 #define LQSPI_ADDR          0xc0000000
51 #define QSPI_IRQ            15
52 #define QSPI_DMA_ADDR       0xff0f0800
53 #define NUM_QSPI_IRQ_LINES  2
54 
55 #define CRF_ADDR            0xfd1a0000
56 #define CRF_IRQ             120
57 
58 /* Serializer/Deserializer.  */
59 #define SERDES_ADDR         0xfd400000
60 #define SERDES_SIZE         0x20000
61 
62 #define DP_ADDR             0xfd4a0000
63 #define DP_IRQ              113
64 
65 #define DPDMA_ADDR          0xfd4c0000
66 #define DPDMA_IRQ           116
67 
68 #define APU_ADDR            0xfd5c0000
69 #define APU_IRQ             153
70 
71 #define TTC0_ADDR           0xFF110000
72 #define TTC0_IRQ            36
73 
74 #define IPI_ADDR            0xFF300000
75 #define IPI_IRQ             64
76 
77 #define RTC_ADDR            0xffa60000
78 #define RTC_IRQ             26
79 
80 #define BBRAM_ADDR          0xffcd0000
81 #define BBRAM_IRQ           11
82 
83 #define EFUSE_ADDR          0xffcc0000
84 #define EFUSE_IRQ           87
85 
86 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
87 
88 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
89     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
90 };
91 
92 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
93     57, 59, 61, 63,
94 };
95 
96 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
97     0xFF000000, 0xFF010000,
98 };
99 
100 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
101     21, 22,
102 };
103 
104 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
105     0xFF060000, 0xFF070000,
106 };
107 
108 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
109     23, 24,
110 };
111 
112 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
113     0xFF160000, 0xFF170000,
114 };
115 
116 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
117     48, 49,
118 };
119 
120 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
121     0xFF040000, 0xFF050000,
122 };
123 
124 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
125     19, 20,
126 };
127 
128 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
129     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
130     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
131 };
132 
133 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
134     124, 125, 126, 127, 128, 129, 130, 131
135 };
136 
137 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
138     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
139     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
140 };
141 
142 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
143     77, 78, 79, 80, 81, 82, 83, 84
144 };
145 
146 typedef struct XlnxZynqMPGICRegion {
147     int region_index;
148     uint32_t address;
149     uint32_t offset;
150     bool virt;
151 } XlnxZynqMPGICRegion;
152 
153 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
154     /* Distributor */
155     {
156         .region_index = 0,
157         .address = GIC_DIST_ADDR,
158         .offset = 0,
159         .virt = false
160     },
161 
162     /* CPU interface */
163     {
164         .region_index = 1,
165         .address = GIC_CPU_ADDR,
166         .offset = 0,
167         .virt = false
168     },
169     {
170         .region_index = 1,
171         .address = GIC_CPU_ADDR + 0x10000,
172         .offset = 0x1000,
173         .virt = false
174     },
175 
176     /* Virtual interface */
177     {
178         .region_index = 2,
179         .address = GIC_VIFACE_ADDR,
180         .offset = 0,
181         .virt = true
182     },
183 
184     /* Virtual CPU interface */
185     {
186         .region_index = 3,
187         .address = GIC_VCPU_ADDR,
188         .offset = 0,
189         .virt = true
190     },
191     {
192         .region_index = 3,
193         .address = GIC_VCPU_ADDR + 0x10000,
194         .offset = 0x1000,
195         .virt = true
196     },
197 };
198 
199 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
200 {
201     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
202 }
203 
204 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
205                                    const char *boot_cpu, Error **errp)
206 {
207     int i;
208     int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
209                        XLNX_ZYNQMP_NUM_RPU_CPUS);
210 
211     if (num_rpus <= 0) {
212         /* Don't create rpu-cluster object if there's nothing to put in it */
213         return;
214     }
215 
216     object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
217                             TYPE_CPU_CLUSTER);
218     qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
219 
220     for (i = 0; i < num_rpus; i++) {
221         const char *name;
222 
223         object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
224                                 &s->rpu_cpu[i],
225                                 ARM_CPU_TYPE_NAME("cortex-r5f"));
226 
227         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
228         if (strcmp(name, boot_cpu)) {
229             /*
230              * Secondary CPUs start in powered-down state.
231              */
232             object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
233                                      "start-powered-off", true, &error_abort);
234         } else {
235             s->boot_cpu_ptr = &s->rpu_cpu[i];
236         }
237 
238         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
239                                  &error_abort);
240         if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
241             return;
242         }
243     }
244 
245     qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
246 }
247 
248 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
249 {
250     SysBusDevice *sbd;
251 
252     object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
253                                        sizeof(s->bbram), TYPE_XLNX_BBRAM,
254                                        &error_fatal,
255                                        "crc-zpads", "1",
256                                        NULL);
257     sbd = SYS_BUS_DEVICE(&s->bbram);
258 
259     sysbus_realize(sbd, &error_fatal);
260     sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
261     sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
262 }
263 
264 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
265 {
266     Object *bits = OBJECT(&s->efuse);
267     Object *ctrl = OBJECT(&s->efuse_ctrl);
268     SysBusDevice *sbd;
269 
270     object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
271                             TYPE_XLNX_ZYNQMP_EFUSE);
272 
273     object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
274                                        sizeof(s->efuse),
275                                        TYPE_XLNX_EFUSE, &error_abort,
276                                        "efuse-nr", "3",
277                                        "efuse-size", "2048",
278                                        NULL);
279 
280     qdev_realize(DEVICE(bits), NULL, &error_abort);
281     object_property_set_link(ctrl, "efuse", bits, &error_abort);
282 
283     sbd = SYS_BUS_DEVICE(ctrl);
284     sysbus_realize(sbd, &error_abort);
285     sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
286     sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
287 }
288 
289 static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
290 {
291     SysBusDevice *sbd;
292     int i;
293 
294     object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
295                             TYPE_XLNX_ZYNQMP_APU_CTRL);
296     sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
297 
298     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
299         g_autofree gchar *name = g_strdup_printf("cpu%d", i);
300 
301         object_property_set_link(OBJECT(&s->apu_ctrl), name,
302                                  OBJECT(&s->apu_cpu[i]), &error_abort);
303     }
304 
305     sysbus_realize(sbd, &error_fatal);
306     sysbus_mmio_map(sbd, 0, APU_ADDR);
307     sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
308 }
309 
310 static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
311 {
312     SysBusDevice *sbd;
313 
314     object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
315     sbd = SYS_BUS_DEVICE(&s->crf);
316 
317     sysbus_realize(sbd, &error_fatal);
318     sysbus_mmio_map(sbd, 0, CRF_ADDR);
319     sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
320 }
321 
322 static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
323 {
324     SysBusDevice *sbd;
325     int i, irq;
326 
327     for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
328         object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
329                                 TYPE_CADENCE_TTC);
330         sbd = SYS_BUS_DEVICE(&s->ttc[i]);
331 
332         sysbus_realize(sbd, &error_fatal);
333         sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
334         for (irq = 0; irq < 3; irq++) {
335             sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
336         }
337     }
338 }
339 
340 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
341 {
342     static const struct UnimpInfo {
343         const char *name;
344         hwaddr base;
345         hwaddr size;
346     } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
347         { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
348     };
349     unsigned int nr;
350 
351     for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) {
352         const struct UnimpInfo *info = &unimp_areas[nr];
353         DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
354         SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
355 
356         assert(info->name && info->base && info->size > 0);
357         qdev_prop_set_string(dev, "name", info->name);
358         qdev_prop_set_uint64(dev, "size", info->size);
359         object_property_add_child(OBJECT(s), info->name, OBJECT(dev));
360 
361         sysbus_realize_and_unref(sbd, &error_fatal);
362         sysbus_mmio_map(sbd, 0, info->base);
363     }
364 }
365 
366 static void xlnx_zynqmp_init(Object *obj)
367 {
368     MachineState *ms = MACHINE(qdev_get_machine());
369     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
370     int i;
371     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
372 
373     object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
374                             TYPE_CPU_CLUSTER);
375     qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
376 
377     for (i = 0; i < num_apus; i++) {
378         object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
379                                 &s->apu_cpu[i],
380                                 ARM_CPU_TYPE_NAME("cortex-a53"));
381     }
382 
383     object_initialize_child(obj, "gic", &s->gic, gic_class_name());
384 
385     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
386         object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
387     }
388 
389     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
390         object_initialize_child(obj, "uart[*]", &s->uart[i],
391                                 TYPE_CADENCE_UART);
392     }
393 
394     for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
395         object_initialize_child(obj, "can[*]", &s->can[i],
396                                 TYPE_XLNX_ZYNQMP_CAN);
397     }
398 
399     object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
400 
401     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
402         object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
403                                 TYPE_SYSBUS_SDHCI);
404     }
405 
406     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
407         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
408     }
409 
410     object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
411 
412     object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
413 
414     object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
415 
416     object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
417 
418     object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
419 
420     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
421         object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
422     }
423 
424     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
425         object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
426     }
427 
428     object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
429     object_initialize_child(obj, "qspi-irq-orgate",
430                             &s->qspi_irq_orgate, TYPE_OR_IRQ);
431 }
432 
433 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
434 {
435     MachineState *ms = MACHINE(qdev_get_machine());
436     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
437     MemoryRegion *system_memory = get_system_memory();
438     uint8_t i;
439     uint64_t ram_size;
440     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
441     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
442     ram_addr_t ddr_low_size, ddr_high_size;
443     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
444     Error *err = NULL;
445 
446     ram_size = memory_region_size(s->ddr_ram);
447 
448     /*
449      * Create the DDR Memory Regions. User friendly checks should happen at
450      * the board level
451      */
452     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
453         /*
454          * The RAM size is above the maximum available for the low DDR.
455          * Create the high DDR memory region as well.
456          */
457         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
458         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
459         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
460 
461         memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
462                                  "ddr-ram-high", s->ddr_ram, ddr_low_size,
463                                  ddr_high_size);
464         memory_region_add_subregion(get_system_memory(),
465                                     XLNX_ZYNQMP_HIGH_RAM_START,
466                                     &s->ddr_ram_high);
467     } else {
468         /* RAM must be non-zero */
469         assert(ram_size);
470         ddr_low_size = ram_size;
471     }
472 
473     memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
474                              s->ddr_ram, 0, ddr_low_size);
475     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
476 
477     /* Create the four OCM banks */
478     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
479         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
480 
481         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
482                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
483         memory_region_add_subregion(get_system_memory(),
484                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
485                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
486                                     &s->ocm_ram[i]);
487 
488         g_free(ocm_name);
489     }
490 
491     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
492     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
493     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
494     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
495     qdev_prop_set_bit(DEVICE(&s->gic),
496                       "has-virtualization-extensions", s->virt);
497 
498     qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
499 
500     /* Realize APUs before realizing the GIC. KVM requires this.  */
501     for (i = 0; i < num_apus; i++) {
502         const char *name;
503 
504         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
505         if (strcmp(name, boot_cpu)) {
506             /*
507              * Secondary CPUs start in powered-down state.
508              */
509             object_property_set_bool(OBJECT(&s->apu_cpu[i]),
510                                      "start-powered-off", true, &error_abort);
511         } else {
512             s->boot_cpu_ptr = &s->apu_cpu[i];
513         }
514 
515         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
516                                  NULL);
517         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
518                                  NULL);
519         object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
520                                 GIC_BASE_ADDR, &error_abort);
521         object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
522                                 num_apus, &error_abort);
523         if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
524             return;
525         }
526     }
527 
528     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
529         return;
530     }
531 
532     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
533     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
534         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
535         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
536         MemoryRegion *mr;
537         uint32_t addr = r->address;
538         int j;
539 
540         if (r->virt && !s->virt) {
541             continue;
542         }
543 
544         mr = sysbus_mmio_get_region(gic, r->region_index);
545         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
546             MemoryRegion *alias = &s->gic_mr[i][j];
547 
548             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
549                                      r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
550             memory_region_add_subregion(system_memory, addr, alias);
551 
552             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
553         }
554     }
555 
556     for (i = 0; i < num_apus; i++) {
557         qemu_irq irq;
558 
559         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
560                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
561                                             ARM_CPU_IRQ));
562         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
563                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
564                                             ARM_CPU_FIQ));
565         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
566                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
567                                             ARM_CPU_VIRQ));
568         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
569                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
570                                             ARM_CPU_VFIQ));
571         irq = qdev_get_gpio_in(DEVICE(&s->gic),
572                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
573         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
574         irq = qdev_get_gpio_in(DEVICE(&s->gic),
575                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
576         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
577         irq = qdev_get_gpio_in(DEVICE(&s->gic),
578                                arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
579         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
580         irq = qdev_get_gpio_in(DEVICE(&s->gic),
581                                arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
582         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
583 
584         if (s->virt) {
585             irq = qdev_get_gpio_in(DEVICE(&s->gic),
586                                    arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
587             sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
588         }
589     }
590 
591     xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
592     if (err) {
593         error_propagate(errp, err);
594         return;
595     }
596 
597     if (!s->boot_cpu_ptr) {
598         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
599         return;
600     }
601 
602     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
603         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
604     }
605 
606     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
607         NICInfo *nd = &nd_table[i];
608 
609         /* FIXME use qdev NIC properties instead of nd_table[] */
610         if (nd->used) {
611             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
612             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
613         }
614         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
615                                 &error_abort);
616         object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
617                                 &error_abort);
618         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
619                                 &error_abort);
620         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
621             return;
622         }
623         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
624         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
625                            gic_spi[gem_intr[i]]);
626     }
627 
628     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
629         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
630         if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
631             return;
632         }
633         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
634         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
635                            gic_spi[uart_intr[i]]);
636     }
637 
638     for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
639         object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
640                                 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
641 
642         object_property_set_link(OBJECT(&s->can[i]), "canbus",
643                                  OBJECT(s->canbus[i]), &error_fatal);
644 
645         sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
646         if (err) {
647             error_propagate(errp, err);
648             return;
649         }
650         sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
651         sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
652                            gic_spi[can_intr[i]]);
653     }
654 
655     object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
656                             &error_abort);
657     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
658         return;
659     }
660 
661     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
662     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
663 
664     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
665         char *bus_name;
666         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
667         Object *sdhci = OBJECT(&s->sdhci[i]);
668 
669         /*
670          * Compatible with:
671          * - SD Host Controller Specification Version 3.00
672          * - SDIO Specification Version 3.0
673          * - eMMC Specification Version 4.51
674          */
675         if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
676             return;
677         }
678         if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
679                                       errp)) {
680             return;
681         }
682         if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
683             return;
684         }
685         if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
686             return;
687         }
688         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
689         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
690 
691         /* Alias controller SD bus to the SoC itself */
692         bus_name = g_strdup_printf("sd-bus%d", i);
693         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
694         g_free(bus_name);
695     }
696 
697     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
698         gchar *bus_name;
699 
700         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
701             return;
702         }
703 
704         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
705         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
706                            gic_spi[spi_intr[i]]);
707 
708         /* Alias controller SPI bus to the SoC itself */
709         bus_name = g_strdup_printf("spi%d", i);
710         object_property_add_alias(OBJECT(s), bus_name,
711                                   OBJECT(&s->spi[i]), "spi0");
712         g_free(bus_name);
713     }
714 
715     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
716         return;
717     }
718     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
719     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
720 
721     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
722         return;
723     }
724     object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
725                              &error_abort);
726     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
727     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
728 
729     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
730         return;
731     }
732     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
733     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
734 
735     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
736         return;
737     }
738     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
739     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
740 
741     xlnx_zynqmp_create_bbram(s, gic_spi);
742     xlnx_zynqmp_create_efuse(s, gic_spi);
743     xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
744     xlnx_zynqmp_create_crf(s, gic_spi);
745     xlnx_zynqmp_create_ttc(s, gic_spi);
746     xlnx_zynqmp_create_unimp_mmio(s);
747 
748     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
749         if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
750                                       errp)) {
751             return;
752         }
753         if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma",
754                                       OBJECT(system_memory), errp)) {
755             return;
756         }
757         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
758             return;
759         }
760 
761         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
762         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
763                            gic_spi[gdma_ch_intr[i]]);
764     }
765 
766     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
767         if (!object_property_set_link(OBJECT(&s->adma[i]), "dma",
768                                       OBJECT(system_memory), errp)) {
769             return;
770         }
771         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
772             return;
773         }
774 
775         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
776         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
777                            gic_spi[adma_ch_intr[i]]);
778     }
779 
780     object_property_set_int(OBJECT(&s->qspi_irq_orgate),
781                             "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal);
782     qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal);
783     qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]);
784 
785     if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma",
786                                   OBJECT(system_memory), errp)) {
787         return;
788     }
789     if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
790         return;
791     }
792 
793     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
794     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0,
795                        qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0));
796 
797     if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
798                                   OBJECT(&s->qspi_dma), errp)) {
799          return;
800     }
801     if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
802         return;
803     }
804     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
805     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
806     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0,
807                        qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1));
808 
809     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
810         g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i);
811         g_autofree gchar *target_bus = g_strdup_printf("spi%d", i);
812 
813         /* Alias controller SPI bus to the SoC itself */
814         object_property_add_alias(OBJECT(s), bus_name,
815                                   OBJECT(&s->qspi), target_bus);
816     }
817 }
818 
819 static Property xlnx_zynqmp_props[] = {
820     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
821     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
822     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
823     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
824                      MemoryRegion *),
825     DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
826                      CanBusState *),
827     DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
828                      CanBusState *),
829     DEFINE_PROP_END_OF_LIST()
830 };
831 
832 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
833 {
834     DeviceClass *dc = DEVICE_CLASS(oc);
835 
836     device_class_set_props(dc, xlnx_zynqmp_props);
837     dc->realize = xlnx_zynqmp_realize;
838     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
839     dc->user_creatable = false;
840 }
841 
842 static const TypeInfo xlnx_zynqmp_type_info = {
843     .name = TYPE_XLNX_ZYNQMP,
844     .parent = TYPE_DEVICE,
845     .instance_size = sizeof(XlnxZynqMPState),
846     .instance_init = xlnx_zynqmp_init,
847     .class_init = xlnx_zynqmp_class_init,
848 };
849 
850 static void xlnx_zynqmp_register_types(void)
851 {
852     type_register_static(&xlnx_zynqmp_type_info);
853 }
854 
855 type_init(xlnx_zynqmp_register_types)
856