1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "hw/boards.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/sysemu.h" 28 #include "kvm_arm.h" 29 30 #define GIC_NUM_SPI_INTR 160 31 32 #define ARM_PHYS_TIMER_PPI 30 33 #define ARM_VIRT_TIMER_PPI 27 34 #define ARM_HYP_TIMER_PPI 26 35 #define ARM_SEC_TIMER_PPI 29 36 #define GIC_MAINTENANCE_PPI 25 37 38 #define GEM_REVISION 0x40070106 39 40 #define GIC_BASE_ADDR 0xf9000000 41 #define GIC_DIST_ADDR 0xf9010000 42 #define GIC_CPU_ADDR 0xf9020000 43 #define GIC_VIFACE_ADDR 0xf9040000 44 #define GIC_VCPU_ADDR 0xf9060000 45 46 #define SATA_INTR 133 47 #define SATA_ADDR 0xFD0C0000 48 #define SATA_NUM_PORTS 2 49 50 #define QSPI_ADDR 0xff0f0000 51 #define LQSPI_ADDR 0xc0000000 52 #define QSPI_IRQ 15 53 54 #define DP_ADDR 0xfd4a0000 55 #define DP_IRQ 113 56 57 #define DPDMA_ADDR 0xfd4c0000 58 #define DPDMA_IRQ 116 59 60 #define IPI_ADDR 0xFF300000 61 #define IPI_IRQ 64 62 63 #define RTC_ADDR 0xffa60000 64 #define RTC_IRQ 26 65 66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 67 68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 70 }; 71 72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 73 57, 59, 61, 63, 74 }; 75 76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 77 0xFF000000, 0xFF010000, 78 }; 79 80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 81 21, 22, 82 }; 83 84 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { 85 0xFF060000, 0xFF070000, 86 }; 87 88 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { 89 23, 24, 90 }; 91 92 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 93 0xFF160000, 0xFF170000, 94 }; 95 96 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 97 48, 49, 98 }; 99 100 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 101 0xFF040000, 0xFF050000, 102 }; 103 104 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 105 19, 20, 106 }; 107 108 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 109 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 110 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 111 }; 112 113 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 114 124, 125, 126, 127, 128, 129, 130, 131 115 }; 116 117 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 118 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 119 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 120 }; 121 122 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 123 77, 78, 79, 80, 81, 82, 83, 84 124 }; 125 126 typedef struct XlnxZynqMPGICRegion { 127 int region_index; 128 uint32_t address; 129 uint32_t offset; 130 bool virt; 131 } XlnxZynqMPGICRegion; 132 133 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 134 /* Distributor */ 135 { 136 .region_index = 0, 137 .address = GIC_DIST_ADDR, 138 .offset = 0, 139 .virt = false 140 }, 141 142 /* CPU interface */ 143 { 144 .region_index = 1, 145 .address = GIC_CPU_ADDR, 146 .offset = 0, 147 .virt = false 148 }, 149 { 150 .region_index = 1, 151 .address = GIC_CPU_ADDR + 0x10000, 152 .offset = 0x1000, 153 .virt = false 154 }, 155 156 /* Virtual interface */ 157 { 158 .region_index = 2, 159 .address = GIC_VIFACE_ADDR, 160 .offset = 0, 161 .virt = true 162 }, 163 164 /* Virtual CPU interface */ 165 { 166 .region_index = 3, 167 .address = GIC_VCPU_ADDR, 168 .offset = 0, 169 .virt = true 170 }, 171 { 172 .region_index = 3, 173 .address = GIC_VCPU_ADDR + 0x10000, 174 .offset = 0x1000, 175 .virt = true 176 }, 177 }; 178 179 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 180 { 181 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 182 } 183 184 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 185 const char *boot_cpu, Error **errp) 186 { 187 int i; 188 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 189 XLNX_ZYNQMP_NUM_RPU_CPUS); 190 191 if (num_rpus <= 0) { 192 /* Don't create rpu-cluster object if there's nothing to put in it */ 193 return; 194 } 195 196 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 197 TYPE_CPU_CLUSTER); 198 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 199 200 for (i = 0; i < num_rpus; i++) { 201 const char *name; 202 203 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 204 &s->rpu_cpu[i], 205 ARM_CPU_TYPE_NAME("cortex-r5f")); 206 207 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 208 if (strcmp(name, boot_cpu)) { 209 /* Secondary CPUs start in PSCI powered-down state */ 210 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 211 "start-powered-off", true, &error_abort); 212 } else { 213 s->boot_cpu_ptr = &s->rpu_cpu[i]; 214 } 215 216 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 217 &error_abort); 218 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { 219 return; 220 } 221 } 222 223 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 224 } 225 226 static void xlnx_zynqmp_init(Object *obj) 227 { 228 MachineState *ms = MACHINE(qdev_get_machine()); 229 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 230 int i; 231 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 232 233 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 234 TYPE_CPU_CLUSTER); 235 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 236 237 for (i = 0; i < num_apus; i++) { 238 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 239 &s->apu_cpu[i], 240 ARM_CPU_TYPE_NAME("cortex-a53")); 241 } 242 243 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 244 245 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 246 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 247 } 248 249 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 250 object_initialize_child(obj, "uart[*]", &s->uart[i], 251 TYPE_CADENCE_UART); 252 } 253 254 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 255 object_initialize_child(obj, "can[*]", &s->can[i], 256 TYPE_XLNX_ZYNQMP_CAN); 257 } 258 259 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 260 261 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 262 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 263 TYPE_SYSBUS_SDHCI); 264 } 265 266 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 267 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 268 } 269 270 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 271 272 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 273 274 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 275 276 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 277 278 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 279 280 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 281 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 282 } 283 284 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 285 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 286 } 287 } 288 289 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 290 { 291 MachineState *ms = MACHINE(qdev_get_machine()); 292 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 293 MemoryRegion *system_memory = get_system_memory(); 294 uint8_t i; 295 uint64_t ram_size; 296 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 297 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 298 ram_addr_t ddr_low_size, ddr_high_size; 299 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 300 Error *err = NULL; 301 302 ram_size = memory_region_size(s->ddr_ram); 303 304 /* Create the DDR Memory Regions. User friendly checks should happen at 305 * the board level 306 */ 307 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 308 /* The RAM size is above the maximum available for the low DDR. 309 * Create the high DDR memory region as well. 310 */ 311 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 312 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 313 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 314 315 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 316 "ddr-ram-high", s->ddr_ram, ddr_low_size, 317 ddr_high_size); 318 memory_region_add_subregion(get_system_memory(), 319 XLNX_ZYNQMP_HIGH_RAM_START, 320 &s->ddr_ram_high); 321 } else { 322 /* RAM must be non-zero */ 323 assert(ram_size); 324 ddr_low_size = ram_size; 325 } 326 327 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 328 s->ddr_ram, 0, ddr_low_size); 329 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 330 331 /* Create the four OCM banks */ 332 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 333 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 334 335 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 336 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 337 memory_region_add_subregion(get_system_memory(), 338 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 339 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 340 &s->ocm_ram[i]); 341 342 g_free(ocm_name); 343 } 344 345 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 346 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 347 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 348 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 349 qdev_prop_set_bit(DEVICE(&s->gic), 350 "has-virtualization-extensions", s->virt); 351 352 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 353 354 /* Realize APUs before realizing the GIC. KVM requires this. */ 355 for (i = 0; i < num_apus; i++) { 356 const char *name; 357 358 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit", 359 QEMU_PSCI_CONDUIT_SMC, &error_abort); 360 361 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 362 if (strcmp(name, boot_cpu)) { 363 /* Secondary CPUs start in PSCI powered-down state */ 364 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 365 "start-powered-off", true, &error_abort); 366 } else { 367 s->boot_cpu_ptr = &s->apu_cpu[i]; 368 } 369 370 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 371 NULL); 372 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 373 NULL); 374 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 375 GIC_BASE_ADDR, &error_abort); 376 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 377 num_apus, &error_abort); 378 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { 379 return; 380 } 381 } 382 383 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 384 return; 385 } 386 387 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 388 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 389 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 390 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 391 MemoryRegion *mr; 392 uint32_t addr = r->address; 393 int j; 394 395 if (r->virt && !s->virt) { 396 continue; 397 } 398 399 mr = sysbus_mmio_get_region(gic, r->region_index); 400 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 401 MemoryRegion *alias = &s->gic_mr[i][j]; 402 403 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 404 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 405 memory_region_add_subregion(system_memory, addr, alias); 406 407 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 408 } 409 } 410 411 for (i = 0; i < num_apus; i++) { 412 qemu_irq irq; 413 414 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 415 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 416 ARM_CPU_IRQ)); 417 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 418 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 419 ARM_CPU_FIQ)); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 421 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 422 ARM_CPU_VIRQ)); 423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 424 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 425 ARM_CPU_VFIQ)); 426 irq = qdev_get_gpio_in(DEVICE(&s->gic), 427 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 428 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 429 irq = qdev_get_gpio_in(DEVICE(&s->gic), 430 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 431 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 432 irq = qdev_get_gpio_in(DEVICE(&s->gic), 433 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 434 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 435 irq = qdev_get_gpio_in(DEVICE(&s->gic), 436 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 437 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 438 439 if (s->virt) { 440 irq = qdev_get_gpio_in(DEVICE(&s->gic), 441 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 443 } 444 } 445 446 if (s->has_rpu) { 447 info_report("The 'has_rpu' property is no longer required, to use the " 448 "RPUs just use -smp 6."); 449 } 450 451 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 452 if (err) { 453 error_propagate(errp, err); 454 return; 455 } 456 457 if (!s->boot_cpu_ptr) { 458 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 459 return; 460 } 461 462 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 463 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 464 } 465 466 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 467 NICInfo *nd = &nd_table[i]; 468 469 /* FIXME use qdev NIC properties instead of nd_table[] */ 470 if (nd->used) { 471 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 472 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 473 } 474 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 475 &error_abort); 476 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, 477 &error_abort); 478 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 479 &error_abort); 480 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { 481 return; 482 } 483 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 485 gic_spi[gem_intr[i]]); 486 } 487 488 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 489 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 491 return; 492 } 493 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 495 gic_spi[uart_intr[i]]); 496 } 497 498 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 499 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", 500 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); 501 502 object_property_set_link(OBJECT(&s->can[i]), "canbus", 503 OBJECT(s->canbus[i]), &error_fatal); 504 505 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); 506 if (err) { 507 error_propagate(errp, err); 508 return; 509 } 510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); 511 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, 512 gic_spi[can_intr[i]]); 513 } 514 515 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 516 &error_abort); 517 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 518 return; 519 } 520 521 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 522 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 523 524 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 525 char *bus_name; 526 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 527 Object *sdhci = OBJECT(&s->sdhci[i]); 528 529 /* Compatible with: 530 * - SD Host Controller Specification Version 3.00 531 * - SDIO Specification Version 3.0 532 * - eMMC Specification Version 4.51 533 */ 534 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { 535 return; 536 } 537 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, 538 errp)) { 539 return; 540 } 541 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { 542 return; 543 } 544 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { 545 return; 546 } 547 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 548 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 549 550 /* Alias controller SD bus to the SoC itself */ 551 bus_name = g_strdup_printf("sd-bus%d", i); 552 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 553 g_free(bus_name); 554 } 555 556 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 557 gchar *bus_name; 558 559 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 560 return; 561 } 562 563 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 564 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 565 gic_spi[spi_intr[i]]); 566 567 /* Alias controller SPI bus to the SoC itself */ 568 bus_name = g_strdup_printf("spi%d", i); 569 object_property_add_alias(OBJECT(s), bus_name, 570 OBJECT(&s->spi[i]), "spi0"); 571 g_free(bus_name); 572 } 573 574 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { 575 return; 576 } 577 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 578 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 579 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 580 581 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 582 gchar *bus_name; 583 gchar *target_bus; 584 585 /* Alias controller SPI bus to the SoC itself */ 586 bus_name = g_strdup_printf("qspi%d", i); 587 target_bus = g_strdup_printf("spi%d", i); 588 object_property_add_alias(OBJECT(s), bus_name, 589 OBJECT(&s->qspi), target_bus); 590 g_free(bus_name); 591 g_free(target_bus); 592 } 593 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { 595 return; 596 } 597 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 598 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 599 600 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { 601 return; 602 } 603 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 604 &error_abort); 605 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 606 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 607 608 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { 609 return; 610 } 611 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 612 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 613 614 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 615 return; 616 } 617 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 618 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 619 620 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 621 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, 622 errp)) { 623 return; 624 } 625 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { 626 return; 627 } 628 629 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 630 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 631 gic_spi[gdma_ch_intr[i]]); 632 } 633 634 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 635 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { 636 return; 637 } 638 639 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 640 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 641 gic_spi[adma_ch_intr[i]]); 642 } 643 } 644 645 static Property xlnx_zynqmp_props[] = { 646 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 647 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 648 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 649 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 650 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 651 MemoryRegion *), 652 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, 653 CanBusState *), 654 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, 655 CanBusState *), 656 DEFINE_PROP_END_OF_LIST() 657 }; 658 659 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 660 { 661 DeviceClass *dc = DEVICE_CLASS(oc); 662 663 device_class_set_props(dc, xlnx_zynqmp_props); 664 dc->realize = xlnx_zynqmp_realize; 665 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 666 dc->user_creatable = false; 667 } 668 669 static const TypeInfo xlnx_zynqmp_type_info = { 670 .name = TYPE_XLNX_ZYNQMP, 671 .parent = TYPE_DEVICE, 672 .instance_size = sizeof(XlnxZynqMPState), 673 .instance_init = xlnx_zynqmp_init, 674 .class_init = xlnx_zynqmp_class_init, 675 }; 676 677 static void xlnx_zynqmp_register_types(void) 678 { 679 type_register_static(&xlnx_zynqmp_type_info); 680 } 681 682 type_init(xlnx_zynqmp_register_types) 683