1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 33 #define GEM_REVISION 0x40070106 34 35 #define GIC_BASE_ADDR 0xf9000000 36 #define GIC_DIST_ADDR 0xf9010000 37 #define GIC_CPU_ADDR 0xf9020000 38 39 #define SATA_INTR 133 40 #define SATA_ADDR 0xFD0C0000 41 #define SATA_NUM_PORTS 2 42 43 #define QSPI_ADDR 0xff0f0000 44 #define LQSPI_ADDR 0xc0000000 45 #define QSPI_IRQ 15 46 47 #define DP_ADDR 0xfd4a0000 48 #define DP_IRQ 113 49 50 #define DPDMA_ADDR 0xfd4c0000 51 #define DPDMA_IRQ 116 52 53 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 54 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 55 }; 56 57 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 58 57, 59, 61, 63, 59 }; 60 61 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 62 0xFF000000, 0xFF010000, 63 }; 64 65 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 66 21, 22, 67 }; 68 69 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 70 0xFF160000, 0xFF170000, 71 }; 72 73 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 74 48, 49, 75 }; 76 77 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 78 0xFF040000, 0xFF050000, 79 }; 80 81 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 82 19, 20, 83 }; 84 85 typedef struct XlnxZynqMPGICRegion { 86 int region_index; 87 uint32_t address; 88 } XlnxZynqMPGICRegion; 89 90 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 91 { .region_index = 0, .address = GIC_DIST_ADDR, }, 92 { .region_index = 1, .address = GIC_CPU_ADDR, }, 93 }; 94 95 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 96 { 97 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 98 } 99 100 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 101 Error **errp) 102 { 103 Error *err = NULL; 104 int i; 105 int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); 106 107 for (i = 0; i < num_rpus; i++) { 108 char *name; 109 110 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 111 "cortex-r5-" TYPE_ARM_CPU); 112 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 113 OBJECT(&s->rpu_cpu[i]), &error_abort); 114 115 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 116 if (strcmp(name, boot_cpu)) { 117 /* Secondary CPUs start in PSCI powered-down state */ 118 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 119 "start-powered-off", &error_abort); 120 } else { 121 s->boot_cpu_ptr = &s->rpu_cpu[i]; 122 } 123 g_free(name); 124 125 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 126 &error_abort); 127 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 128 &err); 129 if (err) { 130 error_propagate(errp, err); 131 return; 132 } 133 } 134 } 135 136 static void xlnx_zynqmp_init(Object *obj) 137 { 138 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 139 int i; 140 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 141 142 for (i = 0; i < num_apus; i++) { 143 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 144 "cortex-a53-" TYPE_ARM_CPU); 145 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 146 &error_abort); 147 } 148 149 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 150 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 151 152 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 153 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 154 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 155 } 156 157 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 158 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 159 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 160 } 161 162 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 163 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 164 165 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 166 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 167 TYPE_SYSBUS_SDHCI); 168 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 169 sysbus_get_default()); 170 } 171 172 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 173 object_initialize(&s->spi[i], sizeof(s->spi[i]), 174 TYPE_XILINX_SPIPS); 175 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 176 } 177 178 object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); 179 qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); 180 181 object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); 182 qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); 183 184 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); 185 qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); 186 } 187 188 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 189 { 190 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 191 MemoryRegion *system_memory = get_system_memory(); 192 uint8_t i; 193 uint64_t ram_size; 194 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 195 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 196 ram_addr_t ddr_low_size, ddr_high_size; 197 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 198 Error *err = NULL; 199 200 ram_size = memory_region_size(s->ddr_ram); 201 202 /* Create the DDR Memory Regions. User friendly checks should happen at 203 * the board level 204 */ 205 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 206 /* The RAM size is above the maximum available for the low DDR. 207 * Create the high DDR memory region as well. 208 */ 209 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 210 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 211 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 212 213 memory_region_init_alias(&s->ddr_ram_high, NULL, 214 "ddr-ram-high", s->ddr_ram, 215 ddr_low_size, ddr_high_size); 216 memory_region_add_subregion(get_system_memory(), 217 XLNX_ZYNQMP_HIGH_RAM_START, 218 &s->ddr_ram_high); 219 } else { 220 /* RAM must be non-zero */ 221 assert(ram_size); 222 ddr_low_size = ram_size; 223 } 224 225 memory_region_init_alias(&s->ddr_ram_low, NULL, 226 "ddr-ram-low", s->ddr_ram, 227 0, ddr_low_size); 228 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 229 230 /* Create the four OCM banks */ 231 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 232 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 233 234 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 235 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 236 memory_region_add_subregion(get_system_memory(), 237 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 238 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 239 &s->ocm_ram[i]); 240 241 g_free(ocm_name); 242 } 243 244 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 245 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 246 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 247 248 /* Realize APUs before realizing the GIC. KVM requires this. */ 249 for (i = 0; i < num_apus; i++) { 250 char *name; 251 252 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 253 "psci-conduit", &error_abort); 254 255 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 256 if (strcmp(name, boot_cpu)) { 257 /* Secondary CPUs start in PSCI powered-down state */ 258 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 259 "start-powered-off", &error_abort); 260 } else { 261 s->boot_cpu_ptr = &s->apu_cpu[i]; 262 } 263 g_free(name); 264 265 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 266 s->secure, "has_el3", NULL); 267 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 268 s->virt, "has_el2", NULL); 269 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 270 "reset-cbar", &error_abort); 271 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 272 &err); 273 if (err) { 274 error_propagate(errp, err); 275 return; 276 } 277 } 278 279 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 280 if (err) { 281 error_propagate(errp, err); 282 return; 283 } 284 285 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 286 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 287 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 288 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 289 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 290 uint32_t addr = r->address; 291 int j; 292 293 sysbus_mmio_map(gic, r->region_index, addr); 294 295 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 296 MemoryRegion *alias = &s->gic_mr[i][j]; 297 298 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 299 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 300 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 301 memory_region_add_subregion(system_memory, addr, alias); 302 } 303 } 304 305 for (i = 0; i < num_apus; i++) { 306 qemu_irq irq; 307 308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 309 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 310 ARM_CPU_IRQ)); 311 irq = qdev_get_gpio_in(DEVICE(&s->gic), 312 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 313 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 314 irq = qdev_get_gpio_in(DEVICE(&s->gic), 315 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 316 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 317 } 318 319 if (s->has_rpu) { 320 info_report("The 'has_rpu' property is no longer required, to use the " 321 "RPUs just use -smp 6."); 322 } 323 324 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 325 if (err) { 326 error_propagate(errp, err); 327 return; 328 } 329 330 if (!s->boot_cpu_ptr) { 331 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 332 return; 333 } 334 335 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 336 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 337 } 338 339 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 340 NICInfo *nd = &nd_table[i]; 341 342 if (nd->used) { 343 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 344 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 345 } 346 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 347 &error_abort); 348 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 349 &error_abort); 350 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 351 if (err) { 352 error_propagate(errp, err); 353 return; 354 } 355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 356 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 357 gic_spi[gem_intr[i]]); 358 } 359 360 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 361 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); 362 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 363 if (err) { 364 error_propagate(errp, err); 365 return; 366 } 367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 368 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 369 gic_spi[uart_intr[i]]); 370 } 371 372 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 373 &error_abort); 374 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 375 if (err) { 376 error_propagate(errp, err); 377 return; 378 } 379 380 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 382 383 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 384 char *bus_name; 385 386 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 387 "realized", &err); 388 if (err) { 389 error_propagate(errp, err); 390 return; 391 } 392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 393 sdhci_addr[i]); 394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 395 gic_spi[sdhci_intr[i]]); 396 /* Alias controller SD bus to the SoC itself */ 397 bus_name = g_strdup_printf("sd-bus%d", i); 398 object_property_add_alias(OBJECT(s), bus_name, 399 OBJECT(&s->sdhci[i]), "sd-bus", 400 &error_abort); 401 g_free(bus_name); 402 } 403 404 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 405 gchar *bus_name; 406 407 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 408 409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 411 gic_spi[spi_intr[i]]); 412 413 /* Alias controller SPI bus to the SoC itself */ 414 bus_name = g_strdup_printf("spi%d", i); 415 object_property_add_alias(OBJECT(s), bus_name, 416 OBJECT(&s->spi[i]), "spi0", 417 &error_abort); 418 g_free(bus_name); 419 } 420 421 object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); 422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 423 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 424 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 425 426 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 427 gchar *bus_name; 428 gchar *target_bus; 429 430 /* Alias controller SPI bus to the SoC itself */ 431 bus_name = g_strdup_printf("qspi%d", i); 432 target_bus = g_strdup_printf("spi%d", i); 433 object_property_add_alias(OBJECT(s), bus_name, 434 OBJECT(&s->qspi), target_bus, 435 &error_abort); 436 g_free(bus_name); 437 g_free(target_bus); 438 } 439 440 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 441 if (err) { 442 error_propagate(errp, err); 443 return; 444 } 445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 447 448 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 449 if (err) { 450 error_propagate(errp, err); 451 return; 452 } 453 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 454 &error_abort); 455 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 457 } 458 459 static Property xlnx_zynqmp_props[] = { 460 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 461 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 462 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 463 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 464 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 465 MemoryRegion *), 466 DEFINE_PROP_END_OF_LIST() 467 }; 468 469 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 470 { 471 DeviceClass *dc = DEVICE_CLASS(oc); 472 473 dc->props = xlnx_zynqmp_props; 474 dc->realize = xlnx_zynqmp_realize; 475 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 476 dc->user_creatable = false; 477 } 478 479 static const TypeInfo xlnx_zynqmp_type_info = { 480 .name = TYPE_XLNX_ZYNQMP, 481 .parent = TYPE_DEVICE, 482 .instance_size = sizeof(XlnxZynqMPState), 483 .instance_init = xlnx_zynqmp_init, 484 .class_init = xlnx_zynqmp_class_init, 485 }; 486 487 static void xlnx_zynqmp_register_types(void) 488 { 489 type_register_static(&xlnx_zynqmp_type_info); 490 } 491 492 type_init(xlnx_zynqmp_register_types) 493