1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "hw/arm/xlnx-zynqmp.h" 22 #include "hw/intc/arm_gic_common.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/boards.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/sysemu.h" 27 #include "kvm_arm.h" 28 29 #define GIC_NUM_SPI_INTR 160 30 31 #define ARM_PHYS_TIMER_PPI 30 32 #define ARM_VIRT_TIMER_PPI 27 33 #define ARM_HYP_TIMER_PPI 26 34 #define ARM_SEC_TIMER_PPI 29 35 #define GIC_MAINTENANCE_PPI 25 36 37 #define GEM_REVISION 0x40070106 38 39 #define GIC_BASE_ADDR 0xf9000000 40 #define GIC_DIST_ADDR 0xf9010000 41 #define GIC_CPU_ADDR 0xf9020000 42 #define GIC_VIFACE_ADDR 0xf9040000 43 #define GIC_VCPU_ADDR 0xf9060000 44 45 #define SATA_INTR 133 46 #define SATA_ADDR 0xFD0C0000 47 #define SATA_NUM_PORTS 2 48 49 #define QSPI_ADDR 0xff0f0000 50 #define LQSPI_ADDR 0xc0000000 51 #define QSPI_IRQ 15 52 #define QSPI_DMA_ADDR 0xff0f0800 53 54 #define DP_ADDR 0xfd4a0000 55 #define DP_IRQ 113 56 57 #define DPDMA_ADDR 0xfd4c0000 58 #define DPDMA_IRQ 116 59 60 #define APU_ADDR 0xfd5c0000 61 #define APU_SIZE 0x100 62 63 #define IPI_ADDR 0xFF300000 64 #define IPI_IRQ 64 65 66 #define RTC_ADDR 0xffa60000 67 #define RTC_IRQ 26 68 69 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 70 71 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 72 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 73 }; 74 75 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 76 57, 59, 61, 63, 77 }; 78 79 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 80 0xFF000000, 0xFF010000, 81 }; 82 83 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 84 21, 22, 85 }; 86 87 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { 88 0xFF060000, 0xFF070000, 89 }; 90 91 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { 92 23, 24, 93 }; 94 95 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 96 0xFF160000, 0xFF170000, 97 }; 98 99 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 100 48, 49, 101 }; 102 103 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 104 0xFF040000, 0xFF050000, 105 }; 106 107 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 108 19, 20, 109 }; 110 111 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 112 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 113 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 114 }; 115 116 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 117 124, 125, 126, 127, 128, 129, 130, 131 118 }; 119 120 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 121 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 122 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 123 }; 124 125 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 126 77, 78, 79, 80, 81, 82, 83, 84 127 }; 128 129 typedef struct XlnxZynqMPGICRegion { 130 int region_index; 131 uint32_t address; 132 uint32_t offset; 133 bool virt; 134 } XlnxZynqMPGICRegion; 135 136 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 137 /* Distributor */ 138 { 139 .region_index = 0, 140 .address = GIC_DIST_ADDR, 141 .offset = 0, 142 .virt = false 143 }, 144 145 /* CPU interface */ 146 { 147 .region_index = 1, 148 .address = GIC_CPU_ADDR, 149 .offset = 0, 150 .virt = false 151 }, 152 { 153 .region_index = 1, 154 .address = GIC_CPU_ADDR + 0x10000, 155 .offset = 0x1000, 156 .virt = false 157 }, 158 159 /* Virtual interface */ 160 { 161 .region_index = 2, 162 .address = GIC_VIFACE_ADDR, 163 .offset = 0, 164 .virt = true 165 }, 166 167 /* Virtual CPU interface */ 168 { 169 .region_index = 3, 170 .address = GIC_VCPU_ADDR, 171 .offset = 0, 172 .virt = true 173 }, 174 { 175 .region_index = 3, 176 .address = GIC_VCPU_ADDR + 0x10000, 177 .offset = 0x1000, 178 .virt = true 179 }, 180 }; 181 182 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 183 { 184 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 185 } 186 187 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 188 const char *boot_cpu, Error **errp) 189 { 190 int i; 191 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 192 XLNX_ZYNQMP_NUM_RPU_CPUS); 193 194 if (num_rpus <= 0) { 195 /* Don't create rpu-cluster object if there's nothing to put in it */ 196 return; 197 } 198 199 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 200 TYPE_CPU_CLUSTER); 201 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 202 203 for (i = 0; i < num_rpus; i++) { 204 const char *name; 205 206 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 207 &s->rpu_cpu[i], 208 ARM_CPU_TYPE_NAME("cortex-r5f")); 209 210 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 211 if (strcmp(name, boot_cpu)) { 212 /* Secondary CPUs start in PSCI powered-down state */ 213 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 214 "start-powered-off", true, &error_abort); 215 } else { 216 s->boot_cpu_ptr = &s->rpu_cpu[i]; 217 } 218 219 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 220 &error_abort); 221 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { 222 return; 223 } 224 } 225 226 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 227 } 228 229 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) 230 { 231 static const struct UnimpInfo { 232 const char *name; 233 hwaddr base; 234 hwaddr size; 235 } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { 236 { .name = "apu", APU_ADDR, APU_SIZE }, 237 }; 238 unsigned int nr; 239 240 for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) { 241 const struct UnimpInfo *info = &unimp_areas[nr]; 242 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 243 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 244 245 assert(info->name && info->base && info->size > 0); 246 qdev_prop_set_string(dev, "name", info->name); 247 qdev_prop_set_uint64(dev, "size", info->size); 248 object_property_add_child(OBJECT(s), info->name, OBJECT(dev)); 249 250 sysbus_realize_and_unref(sbd, &error_fatal); 251 sysbus_mmio_map(sbd, 0, info->base); 252 } 253 } 254 255 static void xlnx_zynqmp_init(Object *obj) 256 { 257 MachineState *ms = MACHINE(qdev_get_machine()); 258 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 259 int i; 260 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 261 262 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 263 TYPE_CPU_CLUSTER); 264 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 265 266 for (i = 0; i < num_apus; i++) { 267 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 268 &s->apu_cpu[i], 269 ARM_CPU_TYPE_NAME("cortex-a53")); 270 } 271 272 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 273 274 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 275 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 276 } 277 278 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 279 object_initialize_child(obj, "uart[*]", &s->uart[i], 280 TYPE_CADENCE_UART); 281 } 282 283 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 284 object_initialize_child(obj, "can[*]", &s->can[i], 285 TYPE_XLNX_ZYNQMP_CAN); 286 } 287 288 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 289 290 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 291 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 292 TYPE_SYSBUS_SDHCI); 293 } 294 295 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 296 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 297 } 298 299 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 300 301 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 302 303 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 304 305 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 306 307 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 308 309 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 310 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 311 } 312 313 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 314 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 315 } 316 317 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA); 318 } 319 320 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 321 { 322 MachineState *ms = MACHINE(qdev_get_machine()); 323 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 324 MemoryRegion *system_memory = get_system_memory(); 325 uint8_t i; 326 uint64_t ram_size; 327 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 328 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 329 ram_addr_t ddr_low_size, ddr_high_size; 330 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 331 Error *err = NULL; 332 333 ram_size = memory_region_size(s->ddr_ram); 334 335 /* 336 * Create the DDR Memory Regions. User friendly checks should happen at 337 * the board level 338 */ 339 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 340 /* 341 * The RAM size is above the maximum available for the low DDR. 342 * Create the high DDR memory region as well. 343 */ 344 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 345 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 346 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 347 348 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 349 "ddr-ram-high", s->ddr_ram, ddr_low_size, 350 ddr_high_size); 351 memory_region_add_subregion(get_system_memory(), 352 XLNX_ZYNQMP_HIGH_RAM_START, 353 &s->ddr_ram_high); 354 } else { 355 /* RAM must be non-zero */ 356 assert(ram_size); 357 ddr_low_size = ram_size; 358 } 359 360 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 361 s->ddr_ram, 0, ddr_low_size); 362 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 363 364 /* Create the four OCM banks */ 365 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 366 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 367 368 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 369 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 370 memory_region_add_subregion(get_system_memory(), 371 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 372 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 373 &s->ocm_ram[i]); 374 375 g_free(ocm_name); 376 } 377 378 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 379 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 380 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 381 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 382 qdev_prop_set_bit(DEVICE(&s->gic), 383 "has-virtualization-extensions", s->virt); 384 385 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 386 387 /* Realize APUs before realizing the GIC. KVM requires this. */ 388 for (i = 0; i < num_apus; i++) { 389 const char *name; 390 391 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit", 392 QEMU_PSCI_CONDUIT_SMC, &error_abort); 393 394 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 395 if (strcmp(name, boot_cpu)) { 396 /* Secondary CPUs start in PSCI powered-down state */ 397 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 398 "start-powered-off", true, &error_abort); 399 } else { 400 s->boot_cpu_ptr = &s->apu_cpu[i]; 401 } 402 403 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 404 NULL); 405 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 406 NULL); 407 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 408 GIC_BASE_ADDR, &error_abort); 409 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 410 num_apus, &error_abort); 411 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { 412 return; 413 } 414 } 415 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 417 return; 418 } 419 420 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 421 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 422 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 423 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 424 MemoryRegion *mr; 425 uint32_t addr = r->address; 426 int j; 427 428 if (r->virt && !s->virt) { 429 continue; 430 } 431 432 mr = sysbus_mmio_get_region(gic, r->region_index); 433 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 434 MemoryRegion *alias = &s->gic_mr[i][j]; 435 436 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 437 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 438 memory_region_add_subregion(system_memory, addr, alias); 439 440 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 441 } 442 } 443 444 for (i = 0; i < num_apus; i++) { 445 qemu_irq irq; 446 447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 448 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 449 ARM_CPU_IRQ)); 450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 451 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 452 ARM_CPU_FIQ)); 453 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 454 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 455 ARM_CPU_VIRQ)); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 457 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 458 ARM_CPU_VFIQ)); 459 irq = qdev_get_gpio_in(DEVICE(&s->gic), 460 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 461 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 462 irq = qdev_get_gpio_in(DEVICE(&s->gic), 463 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 464 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 465 irq = qdev_get_gpio_in(DEVICE(&s->gic), 466 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 467 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 468 irq = qdev_get_gpio_in(DEVICE(&s->gic), 469 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 470 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 471 472 if (s->virt) { 473 irq = qdev_get_gpio_in(DEVICE(&s->gic), 474 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 475 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 476 } 477 } 478 479 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 480 if (err) { 481 error_propagate(errp, err); 482 return; 483 } 484 485 if (!s->boot_cpu_ptr) { 486 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 487 return; 488 } 489 490 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 491 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 492 } 493 494 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 495 NICInfo *nd = &nd_table[i]; 496 497 /* FIXME use qdev NIC properties instead of nd_table[] */ 498 if (nd->used) { 499 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 500 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 501 } 502 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 503 &error_abort); 504 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, 505 &error_abort); 506 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 507 &error_abort); 508 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { 509 return; 510 } 511 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 512 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 513 gic_spi[gem_intr[i]]); 514 } 515 516 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 517 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 518 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 519 return; 520 } 521 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 522 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 523 gic_spi[uart_intr[i]]); 524 } 525 526 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 527 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", 528 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); 529 530 object_property_set_link(OBJECT(&s->can[i]), "canbus", 531 OBJECT(s->canbus[i]), &error_fatal); 532 533 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); 534 if (err) { 535 error_propagate(errp, err); 536 return; 537 } 538 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); 539 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, 540 gic_spi[can_intr[i]]); 541 } 542 543 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 544 &error_abort); 545 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 546 return; 547 } 548 549 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 550 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 551 552 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 553 char *bus_name; 554 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 555 Object *sdhci = OBJECT(&s->sdhci[i]); 556 557 /* 558 * Compatible with: 559 * - SD Host Controller Specification Version 3.00 560 * - SDIO Specification Version 3.0 561 * - eMMC Specification Version 4.51 562 */ 563 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { 564 return; 565 } 566 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, 567 errp)) { 568 return; 569 } 570 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { 571 return; 572 } 573 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { 574 return; 575 } 576 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 577 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 578 579 /* Alias controller SD bus to the SoC itself */ 580 bus_name = g_strdup_printf("sd-bus%d", i); 581 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 582 g_free(bus_name); 583 } 584 585 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 586 gchar *bus_name; 587 588 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 589 return; 590 } 591 592 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 593 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 594 gic_spi[spi_intr[i]]); 595 596 /* Alias controller SPI bus to the SoC itself */ 597 bus_name = g_strdup_printf("spi%d", i); 598 object_property_add_alias(OBJECT(s), bus_name, 599 OBJECT(&s->spi[i]), "spi0"); 600 g_free(bus_name); 601 } 602 603 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { 604 return; 605 } 606 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 607 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 608 609 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { 610 return; 611 } 612 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 613 &error_abort); 614 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 615 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 616 617 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { 618 return; 619 } 620 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 621 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 622 623 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 624 return; 625 } 626 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 627 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 628 629 xlnx_zynqmp_create_unimp_mmio(s); 630 631 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 632 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, 633 errp)) { 634 return; 635 } 636 if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", 637 OBJECT(system_memory), errp)) { 638 return; 639 } 640 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { 641 return; 642 } 643 644 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 645 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 646 gic_spi[gdma_ch_intr[i]]); 647 } 648 649 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 650 if (!object_property_set_link(OBJECT(&s->adma[i]), "dma", 651 OBJECT(system_memory), errp)) { 652 return; 653 } 654 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { 655 return; 656 } 657 658 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 659 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 660 gic_spi[adma_ch_intr[i]]); 661 } 662 663 if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma", 664 OBJECT(system_memory), errp)) { 665 return; 666 } 667 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { 668 return; 669 } 670 671 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); 672 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]); 673 674 if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", 675 OBJECT(&s->qspi_dma), errp)) { 676 return; 677 } 678 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { 679 return; 680 } 681 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 682 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 683 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 684 685 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 686 g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i); 687 g_autofree gchar *target_bus = g_strdup_printf("spi%d", i); 688 689 /* Alias controller SPI bus to the SoC itself */ 690 object_property_add_alias(OBJECT(s), bus_name, 691 OBJECT(&s->qspi), target_bus); 692 } 693 } 694 695 static Property xlnx_zynqmp_props[] = { 696 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 697 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 698 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 699 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 700 MemoryRegion *), 701 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, 702 CanBusState *), 703 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, 704 CanBusState *), 705 DEFINE_PROP_END_OF_LIST() 706 }; 707 708 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 709 { 710 DeviceClass *dc = DEVICE_CLASS(oc); 711 712 device_class_set_props(dc, xlnx_zynqmp_props); 713 dc->realize = xlnx_zynqmp_realize; 714 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 715 dc->user_creatable = false; 716 } 717 718 static const TypeInfo xlnx_zynqmp_type_info = { 719 .name = TYPE_XLNX_ZYNQMP, 720 .parent = TYPE_DEVICE, 721 .instance_size = sizeof(XlnxZynqMPState), 722 .instance_init = xlnx_zynqmp_init, 723 .class_init = xlnx_zynqmp_class_init, 724 }; 725 726 static void xlnx_zynqmp_register_types(void) 727 { 728 type_register_static(&xlnx_zynqmp_type_info); 729 } 730 731 type_init(xlnx_zynqmp_register_types) 732