1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/arm/xlnx-zynqmp.h" 20 #include "hw/intc/arm_gic_common.h" 21 #include "exec/address-spaces.h" 22 23 #define GIC_NUM_SPI_INTR 160 24 25 #define ARM_PHYS_TIMER_PPI 30 26 #define ARM_VIRT_TIMER_PPI 27 27 28 #define GIC_BASE_ADDR 0xf9000000 29 #define GIC_DIST_ADDR 0xf9010000 30 #define GIC_CPU_ADDR 0xf9020000 31 32 #define SATA_INTR 133 33 #define SATA_ADDR 0xFD0C0000 34 #define SATA_NUM_PORTS 2 35 36 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 37 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 38 }; 39 40 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 41 57, 59, 61, 63, 42 }; 43 44 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 45 0xFF000000, 0xFF010000, 46 }; 47 48 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 49 21, 22, 50 }; 51 52 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 53 0xFF160000, 0xFF170000, 54 }; 55 56 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 57 48, 49, 58 }; 59 60 typedef struct XlnxZynqMPGICRegion { 61 int region_index; 62 uint32_t address; 63 } XlnxZynqMPGICRegion; 64 65 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 66 { .region_index = 0, .address = GIC_DIST_ADDR, }, 67 { .region_index = 1, .address = GIC_CPU_ADDR, }, 68 }; 69 70 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 71 { 72 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 73 } 74 75 static void xlnx_zynqmp_init(Object *obj) 76 { 77 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 78 int i; 79 80 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 81 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 82 "cortex-a53-" TYPE_ARM_CPU); 83 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 84 &error_abort); 85 } 86 87 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 88 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 89 "cortex-r5-" TYPE_ARM_CPU); 90 object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), 91 &error_abort); 92 } 93 94 object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, 95 (Object **)&s->ddr_ram, 96 qdev_prop_allow_set_link_before_realize, 97 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 98 99 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 100 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 101 102 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 103 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 104 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 105 } 106 107 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 108 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 109 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 110 } 111 112 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 113 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 114 115 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 116 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 117 TYPE_SYSBUS_SDHCI); 118 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 119 sysbus_get_default()); 120 } 121 } 122 123 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 124 { 125 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 126 MemoryRegion *system_memory = get_system_memory(); 127 uint8_t i; 128 uint64_t ram_size; 129 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 130 ram_addr_t ddr_low_size, ddr_high_size; 131 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 132 Error *err = NULL; 133 134 ram_size = memory_region_size(s->ddr_ram); 135 136 /* Create the DDR Memory Regions. User friendly checks should happen at 137 * the board level 138 */ 139 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 140 /* The RAM size is above the maximum available for the low DDR. 141 * Create the high DDR memory region as well. 142 */ 143 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 144 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 145 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 146 147 memory_region_init_alias(&s->ddr_ram_high, NULL, 148 "ddr-ram-high", s->ddr_ram, 149 ddr_low_size, ddr_high_size); 150 memory_region_add_subregion(get_system_memory(), 151 XLNX_ZYNQMP_HIGH_RAM_START, 152 &s->ddr_ram_high); 153 } else { 154 /* RAM must be non-zero */ 155 assert(ram_size); 156 ddr_low_size = ram_size; 157 } 158 159 memory_region_init_alias(&s->ddr_ram_low, NULL, 160 "ddr-ram-low", s->ddr_ram, 161 0, ddr_low_size); 162 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 163 164 /* Create the four OCM banks */ 165 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 166 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 167 168 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 169 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 170 vmstate_register_ram_global(&s->ocm_ram[i]); 171 memory_region_add_subregion(get_system_memory(), 172 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 173 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 174 &s->ocm_ram[i]); 175 176 g_free(ocm_name); 177 } 178 179 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 180 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 181 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 182 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 183 if (err) { 184 error_propagate(errp, err); 185 return; 186 } 187 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 188 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 189 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 190 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 191 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 192 uint32_t addr = r->address; 193 int j; 194 195 sysbus_mmio_map(gic, r->region_index, addr); 196 197 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 198 MemoryRegion *alias = &s->gic_mr[i][j]; 199 200 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 201 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 202 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 203 memory_region_add_subregion(system_memory, addr, alias); 204 } 205 } 206 207 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 208 qemu_irq irq; 209 char *name; 210 211 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 212 "psci-conduit", &error_abort); 213 214 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 215 if (strcmp(name, boot_cpu)) { 216 /* Secondary CPUs start in PSCI powered-down state */ 217 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 218 "start-powered-off", &error_abort); 219 } else { 220 s->boot_cpu_ptr = &s->apu_cpu[i]; 221 } 222 g_free(name); 223 224 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 225 "reset-cbar", &error_abort); 226 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 227 &err); 228 if (err) { 229 error_propagate(errp, err); 230 return; 231 } 232 233 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 234 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 235 ARM_CPU_IRQ)); 236 irq = qdev_get_gpio_in(DEVICE(&s->gic), 237 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 238 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 239 irq = qdev_get_gpio_in(DEVICE(&s->gic), 240 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 241 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 242 } 243 244 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 245 char *name; 246 247 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 248 if (strcmp(name, boot_cpu)) { 249 /* Secondary CPUs start in PSCI powered-down state */ 250 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 251 "start-powered-off", &error_abort); 252 } else { 253 s->boot_cpu_ptr = &s->rpu_cpu[i]; 254 } 255 g_free(name); 256 257 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 258 &error_abort); 259 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 260 &err); 261 if (err) { 262 error_propagate(errp, err); 263 return; 264 } 265 } 266 267 if (!s->boot_cpu_ptr) { 268 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 269 return; 270 } 271 272 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 273 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 274 } 275 276 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 277 NICInfo *nd = &nd_table[i]; 278 279 if (nd->used) { 280 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 281 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 282 } 283 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 284 if (err) { 285 error_propagate(errp, err); 286 return; 287 } 288 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 289 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 290 gic_spi[gem_intr[i]]); 291 } 292 293 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 294 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 295 if (err) { 296 error_propagate(errp, err); 297 return; 298 } 299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 301 gic_spi[uart_intr[i]]); 302 } 303 304 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 305 &error_abort); 306 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 307 if (err) { 308 error_propagate(errp, err); 309 return; 310 } 311 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 314 315 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 316 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 317 "realized", &err); 318 if (err) { 319 error_propagate(errp, err); 320 return; 321 } 322 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 323 sdhci_addr[i]); 324 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 325 gic_spi[sdhci_intr[i]]); 326 } 327 } 328 329 static Property xlnx_zynqmp_props[] = { 330 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 331 DEFINE_PROP_END_OF_LIST() 332 }; 333 334 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 335 { 336 DeviceClass *dc = DEVICE_CLASS(oc); 337 338 dc->props = xlnx_zynqmp_props; 339 dc->realize = xlnx_zynqmp_realize; 340 341 /* 342 * Reason: creates an ARM CPU, thus use after free(), see 343 * arm_cpu_class_init() 344 */ 345 dc->cannot_destroy_with_object_finalize_yet = true; 346 } 347 348 static const TypeInfo xlnx_zynqmp_type_info = { 349 .name = TYPE_XLNX_ZYNQMP, 350 .parent = TYPE_DEVICE, 351 .instance_size = sizeof(XlnxZynqMPState), 352 .instance_init = xlnx_zynqmp_init, 353 .class_init = xlnx_zynqmp_class_init, 354 }; 355 356 static void xlnx_zynqmp_register_types(void) 357 { 358 type_register_static(&xlnx_zynqmp_type_info); 359 } 360 361 type_init(xlnx_zynqmp_register_types) 362