1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 #define ARM_HYP_TIMER_PPI 26 33 #define ARM_SEC_TIMER_PPI 29 34 #define GIC_MAINTENANCE_PPI 25 35 36 #define GEM_REVISION 0x40070106 37 38 #define GIC_BASE_ADDR 0xf9000000 39 #define GIC_DIST_ADDR 0xf9010000 40 #define GIC_CPU_ADDR 0xf9020000 41 #define GIC_VIFACE_ADDR 0xf9040000 42 #define GIC_VCPU_ADDR 0xf9060000 43 44 #define SATA_INTR 133 45 #define SATA_ADDR 0xFD0C0000 46 #define SATA_NUM_PORTS 2 47 48 #define QSPI_ADDR 0xff0f0000 49 #define LQSPI_ADDR 0xc0000000 50 #define QSPI_IRQ 15 51 52 #define DP_ADDR 0xfd4a0000 53 #define DP_IRQ 113 54 55 #define DPDMA_ADDR 0xfd4c0000 56 #define DPDMA_IRQ 116 57 58 #define IPI_ADDR 0xFF300000 59 #define IPI_IRQ 64 60 61 #define RTC_ADDR 0xffa60000 62 #define RTC_IRQ 26 63 64 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 65 66 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 67 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 68 }; 69 70 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 71 57, 59, 61, 63, 72 }; 73 74 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 75 0xFF000000, 0xFF010000, 76 }; 77 78 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 79 21, 22, 80 }; 81 82 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 83 0xFF160000, 0xFF170000, 84 }; 85 86 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 87 48, 49, 88 }; 89 90 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 91 0xFF040000, 0xFF050000, 92 }; 93 94 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 95 19, 20, 96 }; 97 98 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 99 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 100 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 101 }; 102 103 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 104 124, 125, 126, 127, 128, 129, 130, 131 105 }; 106 107 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 108 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 109 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 110 }; 111 112 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 113 77, 78, 79, 80, 81, 82, 83, 84 114 }; 115 116 typedef struct XlnxZynqMPGICRegion { 117 int region_index; 118 uint32_t address; 119 uint32_t offset; 120 bool virt; 121 } XlnxZynqMPGICRegion; 122 123 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 124 /* Distributor */ 125 { 126 .region_index = 0, 127 .address = GIC_DIST_ADDR, 128 .offset = 0, 129 .virt = false 130 }, 131 132 /* CPU interface */ 133 { 134 .region_index = 1, 135 .address = GIC_CPU_ADDR, 136 .offset = 0, 137 .virt = false 138 }, 139 { 140 .region_index = 1, 141 .address = GIC_CPU_ADDR + 0x10000, 142 .offset = 0x1000, 143 .virt = false 144 }, 145 146 /* Virtual interface */ 147 { 148 .region_index = 2, 149 .address = GIC_VIFACE_ADDR, 150 .offset = 0, 151 .virt = true 152 }, 153 154 /* Virtual CPU interface */ 155 { 156 .region_index = 3, 157 .address = GIC_VCPU_ADDR, 158 .offset = 0, 159 .virt = true 160 }, 161 { 162 .region_index = 3, 163 .address = GIC_VCPU_ADDR + 0x10000, 164 .offset = 0x1000, 165 .virt = true 166 }, 167 }; 168 169 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 170 { 171 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 172 } 173 174 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 175 Error **errp) 176 { 177 Error *err = NULL; 178 int i; 179 int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); 180 181 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 182 sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, 183 &error_abort, NULL); 184 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 185 186 qdev_init_nofail(DEVICE(&s->rpu_cluster)); 187 188 for (i = 0; i < num_rpus; i++) { 189 char *name; 190 191 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 192 "cortex-r5f-" TYPE_ARM_CPU); 193 object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 194 OBJECT(&s->rpu_cpu[i]), &error_abort); 195 196 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 197 if (strcmp(name, boot_cpu)) { 198 /* Secondary CPUs start in PSCI powered-down state */ 199 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 200 "start-powered-off", &error_abort); 201 } else { 202 s->boot_cpu_ptr = &s->rpu_cpu[i]; 203 } 204 g_free(name); 205 206 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 207 &error_abort); 208 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 209 &err); 210 if (err) { 211 error_propagate(errp, err); 212 return; 213 } 214 } 215 } 216 217 static void xlnx_zynqmp_init(Object *obj) 218 { 219 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 220 int i; 221 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 222 223 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 224 sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, 225 &error_abort, NULL); 226 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 227 228 for (i = 0; i < num_apus; i++) { 229 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 230 &s->apu_cpu[i], sizeof(s->apu_cpu[i]), 231 "cortex-a53-" TYPE_ARM_CPU, &error_abort, 232 NULL); 233 } 234 235 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), 236 gic_class_name()); 237 238 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 239 sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]), 240 TYPE_CADENCE_GEM); 241 } 242 243 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 244 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 245 TYPE_CADENCE_UART); 246 } 247 248 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 249 TYPE_SYSBUS_AHCI); 250 251 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 252 sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i], 253 sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI); 254 } 255 256 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 257 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), 258 TYPE_XILINX_SPIPS); 259 } 260 261 sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi), 262 TYPE_XLNX_ZYNQMP_QSPIPS); 263 264 sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP); 265 266 sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma), 267 TYPE_XLNX_DPDMA); 268 269 sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi), 270 TYPE_XLNX_ZYNQMP_IPI); 271 272 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), 273 TYPE_XLNX_ZYNQMP_RTC); 274 275 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 276 sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]), 277 TYPE_XLNX_ZDMA); 278 } 279 280 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 281 sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]), 282 TYPE_XLNX_ZDMA); 283 } 284 } 285 286 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 287 { 288 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 289 MemoryRegion *system_memory = get_system_memory(); 290 uint8_t i; 291 uint64_t ram_size; 292 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 293 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 294 ram_addr_t ddr_low_size, ddr_high_size; 295 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 296 Error *err = NULL; 297 298 ram_size = memory_region_size(s->ddr_ram); 299 300 /* Create the DDR Memory Regions. User friendly checks should happen at 301 * the board level 302 */ 303 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 304 /* The RAM size is above the maximum available for the low DDR. 305 * Create the high DDR memory region as well. 306 */ 307 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 308 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 309 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 310 311 memory_region_init_alias(&s->ddr_ram_high, NULL, 312 "ddr-ram-high", s->ddr_ram, 313 ddr_low_size, ddr_high_size); 314 memory_region_add_subregion(get_system_memory(), 315 XLNX_ZYNQMP_HIGH_RAM_START, 316 &s->ddr_ram_high); 317 } else { 318 /* RAM must be non-zero */ 319 assert(ram_size); 320 ddr_low_size = ram_size; 321 } 322 323 memory_region_init_alias(&s->ddr_ram_low, NULL, 324 "ddr-ram-low", s->ddr_ram, 325 0, ddr_low_size); 326 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 327 328 /* Create the four OCM banks */ 329 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 330 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 331 332 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 333 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 334 memory_region_add_subregion(get_system_memory(), 335 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 336 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 337 &s->ocm_ram[i]); 338 339 g_free(ocm_name); 340 } 341 342 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 343 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 344 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 345 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 346 qdev_prop_set_bit(DEVICE(&s->gic), 347 "has-virtualization-extensions", s->virt); 348 349 qdev_init_nofail(DEVICE(&s->apu_cluster)); 350 351 /* Realize APUs before realizing the GIC. KVM requires this. */ 352 for (i = 0; i < num_apus; i++) { 353 char *name; 354 355 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 356 "psci-conduit", &error_abort); 357 358 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 359 if (strcmp(name, boot_cpu)) { 360 /* Secondary CPUs start in PSCI powered-down state */ 361 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 362 "start-powered-off", &error_abort); 363 } else { 364 s->boot_cpu_ptr = &s->apu_cpu[i]; 365 } 366 g_free(name); 367 368 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 369 s->secure, "has_el3", NULL); 370 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 371 s->virt, "has_el2", NULL); 372 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 373 "reset-cbar", &error_abort); 374 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 375 "core-count", &error_abort); 376 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 377 &err); 378 if (err) { 379 error_propagate(errp, err); 380 return; 381 } 382 } 383 384 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 385 if (err) { 386 error_propagate(errp, err); 387 return; 388 } 389 390 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 391 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 392 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 393 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 394 MemoryRegion *mr; 395 uint32_t addr = r->address; 396 int j; 397 398 if (r->virt && !s->virt) { 399 continue; 400 } 401 402 mr = sysbus_mmio_get_region(gic, r->region_index); 403 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 404 MemoryRegion *alias = &s->gic_mr[i][j]; 405 406 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 407 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 408 memory_region_add_subregion(system_memory, addr, alias); 409 410 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 411 } 412 } 413 414 for (i = 0; i < num_apus; i++) { 415 qemu_irq irq; 416 417 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 418 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 419 ARM_CPU_IRQ)); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 421 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 422 ARM_CPU_FIQ)); 423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 424 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 425 ARM_CPU_VIRQ)); 426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 427 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 428 ARM_CPU_VFIQ)); 429 irq = qdev_get_gpio_in(DEVICE(&s->gic), 430 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 431 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 432 irq = qdev_get_gpio_in(DEVICE(&s->gic), 433 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 434 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 435 irq = qdev_get_gpio_in(DEVICE(&s->gic), 436 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 437 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 438 irq = qdev_get_gpio_in(DEVICE(&s->gic), 439 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 440 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 441 442 if (s->virt) { 443 irq = qdev_get_gpio_in(DEVICE(&s->gic), 444 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 446 } 447 } 448 449 if (s->has_rpu) { 450 info_report("The 'has_rpu' property is no longer required, to use the " 451 "RPUs just use -smp 6."); 452 } 453 454 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 455 if (err) { 456 error_propagate(errp, err); 457 return; 458 } 459 460 if (!s->boot_cpu_ptr) { 461 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 462 return; 463 } 464 465 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 466 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 467 } 468 469 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 470 NICInfo *nd = &nd_table[i]; 471 472 if (nd->used) { 473 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 474 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 475 } 476 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 477 &error_abort); 478 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 479 &error_abort); 480 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 481 if (err) { 482 error_propagate(errp, err); 483 return; 484 } 485 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 487 gic_spi[gem_intr[i]]); 488 } 489 490 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 491 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 492 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 493 if (err) { 494 error_propagate(errp, err); 495 return; 496 } 497 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 499 gic_spi[uart_intr[i]]); 500 } 501 502 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 503 &error_abort); 504 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 505 if (err) { 506 error_propagate(errp, err); 507 return; 508 } 509 510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 511 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 512 513 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 514 char *bus_name = g_strdup_printf("sd-bus%d", i); 515 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 516 Object *sdhci = OBJECT(&s->sdhci[i]); 517 518 /* Compatible with: 519 * - SD Host Controller Specification Version 3.00 520 * - SDIO Specification Version 3.0 521 * - eMMC Specification Version 4.51 522 */ 523 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 524 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 525 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 526 object_property_set_bool(sdhci, true, "realized", &err); 527 if (err) { 528 error_propagate(errp, err); 529 return; 530 } 531 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 532 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 533 534 /* Alias controller SD bus to the SoC itself */ 535 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus", 536 &error_abort); 537 g_free(bus_name); 538 } 539 540 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 541 gchar *bus_name; 542 543 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 544 545 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 546 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 547 gic_spi[spi_intr[i]]); 548 549 /* Alias controller SPI bus to the SoC itself */ 550 bus_name = g_strdup_printf("spi%d", i); 551 object_property_add_alias(OBJECT(s), bus_name, 552 OBJECT(&s->spi[i]), "spi0", 553 &error_abort); 554 g_free(bus_name); 555 } 556 557 object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); 558 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 559 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 560 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 561 562 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 563 gchar *bus_name; 564 gchar *target_bus; 565 566 /* Alias controller SPI bus to the SoC itself */ 567 bus_name = g_strdup_printf("qspi%d", i); 568 target_bus = g_strdup_printf("spi%d", i); 569 object_property_add_alias(OBJECT(s), bus_name, 570 OBJECT(&s->qspi), target_bus, 571 &error_abort); 572 g_free(bus_name); 573 g_free(target_bus); 574 } 575 576 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 577 if (err) { 578 error_propagate(errp, err); 579 return; 580 } 581 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 582 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 583 584 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 585 if (err) { 586 error_propagate(errp, err); 587 return; 588 } 589 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 590 &error_abort); 591 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 592 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 593 594 object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err); 595 if (err) { 596 error_propagate(errp, err); 597 return; 598 } 599 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 600 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 601 602 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 603 if (err) { 604 error_propagate(errp, err); 605 return; 606 } 607 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 608 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 609 610 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 611 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 612 object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err); 613 if (err) { 614 error_propagate(errp, err); 615 return; 616 } 617 618 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 619 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 620 gic_spi[gdma_ch_intr[i]]); 621 } 622 623 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 624 object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err); 625 if (err) { 626 error_propagate(errp, err); 627 return; 628 } 629 630 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 631 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 632 gic_spi[adma_ch_intr[i]]); 633 } 634 } 635 636 static Property xlnx_zynqmp_props[] = { 637 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 638 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 639 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 640 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 641 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 642 MemoryRegion *), 643 DEFINE_PROP_END_OF_LIST() 644 }; 645 646 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 647 { 648 DeviceClass *dc = DEVICE_CLASS(oc); 649 650 dc->props = xlnx_zynqmp_props; 651 dc->realize = xlnx_zynqmp_realize; 652 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 653 dc->user_creatable = false; 654 } 655 656 static const TypeInfo xlnx_zynqmp_type_info = { 657 .name = TYPE_XLNX_ZYNQMP, 658 .parent = TYPE_DEVICE, 659 .instance_size = sizeof(XlnxZynqMPState), 660 .instance_init = xlnx_zynqmp_init, 661 .class_init = xlnx_zynqmp_class_init, 662 }; 663 664 static void xlnx_zynqmp_register_types(void) 665 { 666 type_register_static(&xlnx_zynqmp_type_info); 667 } 668 669 type_init(xlnx_zynqmp_register_types) 670