1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 #include "sysemu/kvm.h" 26 #include "kvm_arm.h" 27 28 #define GIC_NUM_SPI_INTR 160 29 30 #define ARM_PHYS_TIMER_PPI 30 31 #define ARM_VIRT_TIMER_PPI 27 32 33 #define GEM_REVISION 0x40070106 34 35 #define GIC_BASE_ADDR 0xf9000000 36 #define GIC_DIST_ADDR 0xf9010000 37 #define GIC_CPU_ADDR 0xf9020000 38 39 #define SATA_INTR 133 40 #define SATA_ADDR 0xFD0C0000 41 #define SATA_NUM_PORTS 2 42 43 #define QSPI_ADDR 0xff0f0000 44 #define LQSPI_ADDR 0xc0000000 45 #define QSPI_IRQ 15 46 47 #define DP_ADDR 0xfd4a0000 48 #define DP_IRQ 113 49 50 #define DPDMA_ADDR 0xfd4c0000 51 #define DPDMA_IRQ 116 52 53 #define IPI_ADDR 0xFF300000 54 #define IPI_IRQ 64 55 56 #define RTC_ADDR 0xffa60000 57 #define RTC_IRQ 26 58 59 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 60 61 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 62 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 63 }; 64 65 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 66 57, 59, 61, 63, 67 }; 68 69 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 70 0xFF000000, 0xFF010000, 71 }; 72 73 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 74 21, 22, 75 }; 76 77 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 78 0xFF160000, 0xFF170000, 79 }; 80 81 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 82 48, 49, 83 }; 84 85 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 86 0xFF040000, 0xFF050000, 87 }; 88 89 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 90 19, 20, 91 }; 92 93 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 94 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 95 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 96 }; 97 98 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 99 124, 125, 126, 127, 128, 129, 130, 131 100 }; 101 102 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 103 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 104 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 105 }; 106 107 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 108 77, 78, 79, 80, 81, 82, 83, 84 109 }; 110 111 typedef struct XlnxZynqMPGICRegion { 112 int region_index; 113 uint32_t address; 114 } XlnxZynqMPGICRegion; 115 116 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 117 { .region_index = 0, .address = GIC_DIST_ADDR, }, 118 { .region_index = 1, .address = GIC_CPU_ADDR, }, 119 }; 120 121 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 122 { 123 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 124 } 125 126 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 127 Error **errp) 128 { 129 Error *err = NULL; 130 int i; 131 int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); 132 133 for (i = 0; i < num_rpus; i++) { 134 char *name; 135 136 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 137 "cortex-r5-" TYPE_ARM_CPU); 138 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 139 OBJECT(&s->rpu_cpu[i]), &error_abort); 140 141 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 142 if (strcmp(name, boot_cpu)) { 143 /* Secondary CPUs start in PSCI powered-down state */ 144 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 145 "start-powered-off", &error_abort); 146 } else { 147 s->boot_cpu_ptr = &s->rpu_cpu[i]; 148 } 149 g_free(name); 150 151 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 152 &error_abort); 153 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 154 &err); 155 if (err) { 156 error_propagate(errp, err); 157 return; 158 } 159 } 160 } 161 162 static void xlnx_zynqmp_init(Object *obj) 163 { 164 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 165 int i; 166 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 167 168 for (i = 0; i < num_apus; i++) { 169 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 170 "cortex-a53-" TYPE_ARM_CPU); 171 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 172 &error_abort); 173 } 174 175 object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); 176 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 177 178 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 179 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 180 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 181 } 182 183 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 184 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 185 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 186 } 187 188 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 189 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 190 191 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 192 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 193 TYPE_SYSBUS_SDHCI); 194 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 195 sysbus_get_default()); 196 } 197 198 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 199 object_initialize(&s->spi[i], sizeof(s->spi[i]), 200 TYPE_XILINX_SPIPS); 201 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 202 } 203 204 object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); 205 qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); 206 207 object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); 208 qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); 209 210 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); 211 qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); 212 213 object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); 214 qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); 215 216 object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); 217 qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); 218 219 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 220 object_initialize(&s->gdma[i], sizeof(s->gdma[i]), TYPE_XLNX_ZDMA); 221 qdev_set_parent_bus(DEVICE(&s->gdma[i]), sysbus_get_default()); 222 } 223 224 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 225 object_initialize(&s->adma[i], sizeof(s->adma[i]), TYPE_XLNX_ZDMA); 226 qdev_set_parent_bus(DEVICE(&s->adma[i]), sysbus_get_default()); 227 } 228 } 229 230 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 231 { 232 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 233 MemoryRegion *system_memory = get_system_memory(); 234 uint8_t i; 235 uint64_t ram_size; 236 int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 237 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 238 ram_addr_t ddr_low_size, ddr_high_size; 239 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 240 Error *err = NULL; 241 242 ram_size = memory_region_size(s->ddr_ram); 243 244 /* Create the DDR Memory Regions. User friendly checks should happen at 245 * the board level 246 */ 247 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 248 /* The RAM size is above the maximum available for the low DDR. 249 * Create the high DDR memory region as well. 250 */ 251 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 252 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 253 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 254 255 memory_region_init_alias(&s->ddr_ram_high, NULL, 256 "ddr-ram-high", s->ddr_ram, 257 ddr_low_size, ddr_high_size); 258 memory_region_add_subregion(get_system_memory(), 259 XLNX_ZYNQMP_HIGH_RAM_START, 260 &s->ddr_ram_high); 261 } else { 262 /* RAM must be non-zero */ 263 assert(ram_size); 264 ddr_low_size = ram_size; 265 } 266 267 memory_region_init_alias(&s->ddr_ram_low, NULL, 268 "ddr-ram-low", s->ddr_ram, 269 0, ddr_low_size); 270 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 271 272 /* Create the four OCM banks */ 273 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 274 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 275 276 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 277 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 278 memory_region_add_subregion(get_system_memory(), 279 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 280 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 281 &s->ocm_ram[i]); 282 283 g_free(ocm_name); 284 } 285 286 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 287 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 288 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 289 290 /* Realize APUs before realizing the GIC. KVM requires this. */ 291 for (i = 0; i < num_apus; i++) { 292 char *name; 293 294 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 295 "psci-conduit", &error_abort); 296 297 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 298 if (strcmp(name, boot_cpu)) { 299 /* Secondary CPUs start in PSCI powered-down state */ 300 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 301 "start-powered-off", &error_abort); 302 } else { 303 s->boot_cpu_ptr = &s->apu_cpu[i]; 304 } 305 g_free(name); 306 307 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 308 s->secure, "has_el3", NULL); 309 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 310 s->virt, "has_el2", NULL); 311 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 312 "reset-cbar", &error_abort); 313 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 314 "core-count", &error_abort); 315 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 316 &err); 317 if (err) { 318 error_propagate(errp, err); 319 return; 320 } 321 } 322 323 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 324 if (err) { 325 error_propagate(errp, err); 326 return; 327 } 328 329 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 330 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 331 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 332 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 333 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 334 uint32_t addr = r->address; 335 int j; 336 337 sysbus_mmio_map(gic, r->region_index, addr); 338 339 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 340 MemoryRegion *alias = &s->gic_mr[i][j]; 341 342 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 343 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 344 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 345 memory_region_add_subregion(system_memory, addr, alias); 346 } 347 } 348 349 for (i = 0; i < num_apus; i++) { 350 qemu_irq irq; 351 352 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 353 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 354 ARM_CPU_IRQ)); 355 irq = qdev_get_gpio_in(DEVICE(&s->gic), 356 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 357 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 358 irq = qdev_get_gpio_in(DEVICE(&s->gic), 359 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 360 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 361 } 362 363 if (s->has_rpu) { 364 info_report("The 'has_rpu' property is no longer required, to use the " 365 "RPUs just use -smp 6."); 366 } 367 368 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 369 if (err) { 370 error_propagate(errp, err); 371 return; 372 } 373 374 if (!s->boot_cpu_ptr) { 375 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 376 return; 377 } 378 379 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 380 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 381 } 382 383 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 384 NICInfo *nd = &nd_table[i]; 385 386 if (nd->used) { 387 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 388 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 389 } 390 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 391 &error_abort); 392 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 393 &error_abort); 394 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 395 if (err) { 396 error_propagate(errp, err); 397 return; 398 } 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 401 gic_spi[gem_intr[i]]); 402 } 403 404 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 405 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 406 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 407 if (err) { 408 error_propagate(errp, err); 409 return; 410 } 411 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 413 gic_spi[uart_intr[i]]); 414 } 415 416 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 417 &error_abort); 418 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 419 if (err) { 420 error_propagate(errp, err); 421 return; 422 } 423 424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 426 427 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 428 char *bus_name = g_strdup_printf("sd-bus%d", i); 429 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 430 Object *sdhci = OBJECT(&s->sdhci[i]); 431 432 /* Compatible with: 433 * - SD Host Controller Specification Version 3.00 434 * - SDIO Specification Version 3.0 435 * - eMMC Specification Version 4.51 436 */ 437 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 438 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 439 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 440 object_property_set_bool(sdhci, true, "realized", &err); 441 if (err) { 442 error_propagate(errp, err); 443 return; 444 } 445 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 446 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 447 448 /* Alias controller SD bus to the SoC itself */ 449 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus", 450 &error_abort); 451 g_free(bus_name); 452 } 453 454 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 455 gchar *bus_name; 456 457 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 458 459 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 460 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 461 gic_spi[spi_intr[i]]); 462 463 /* Alias controller SPI bus to the SoC itself */ 464 bus_name = g_strdup_printf("spi%d", i); 465 object_property_add_alias(OBJECT(s), bus_name, 466 OBJECT(&s->spi[i]), "spi0", 467 &error_abort); 468 g_free(bus_name); 469 } 470 471 object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); 472 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 473 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 474 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 475 476 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 477 gchar *bus_name; 478 gchar *target_bus; 479 480 /* Alias controller SPI bus to the SoC itself */ 481 bus_name = g_strdup_printf("qspi%d", i); 482 target_bus = g_strdup_printf("spi%d", i); 483 object_property_add_alias(OBJECT(s), bus_name, 484 OBJECT(&s->qspi), target_bus, 485 &error_abort); 486 g_free(bus_name); 487 g_free(target_bus); 488 } 489 490 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 491 if (err) { 492 error_propagate(errp, err); 493 return; 494 } 495 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 496 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 497 498 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 499 if (err) { 500 error_propagate(errp, err); 501 return; 502 } 503 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 504 &error_abort); 505 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 507 508 object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err); 509 if (err) { 510 error_propagate(errp, err); 511 return; 512 } 513 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 514 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 515 516 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 517 if (err) { 518 error_propagate(errp, err); 519 return; 520 } 521 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 522 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 523 524 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 525 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 526 object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err); 527 if (err) { 528 error_propagate(errp, err); 529 return; 530 } 531 532 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 533 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 534 gic_spi[gdma_ch_intr[i]]); 535 } 536 537 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 538 object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err); 539 if (err) { 540 error_propagate(errp, err); 541 return; 542 } 543 544 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 545 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 546 gic_spi[adma_ch_intr[i]]); 547 } 548 } 549 550 static Property xlnx_zynqmp_props[] = { 551 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 552 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 553 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 554 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 555 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 556 MemoryRegion *), 557 DEFINE_PROP_END_OF_LIST() 558 }; 559 560 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 561 { 562 DeviceClass *dc = DEVICE_CLASS(oc); 563 564 dc->props = xlnx_zynqmp_props; 565 dc->realize = xlnx_zynqmp_realize; 566 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 567 dc->user_creatable = false; 568 } 569 570 static const TypeInfo xlnx_zynqmp_type_info = { 571 .name = TYPE_XLNX_ZYNQMP, 572 .parent = TYPE_DEVICE, 573 .instance_size = sizeof(XlnxZynqMPState), 574 .instance_init = xlnx_zynqmp_init, 575 .class_init = xlnx_zynqmp_class_init, 576 }; 577 578 static void xlnx_zynqmp_register_types(void) 579 { 580 type_register_static(&xlnx_zynqmp_type_info); 581 } 582 583 type_init(xlnx_zynqmp_register_types) 584