1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "hw/arm/xlnx-zynqmp.h" 21 #include "hw/intc/arm_gic_common.h" 22 #include "exec/address-spaces.h" 23 24 #define GIC_NUM_SPI_INTR 160 25 26 #define ARM_PHYS_TIMER_PPI 30 27 #define ARM_VIRT_TIMER_PPI 27 28 29 #define GIC_BASE_ADDR 0xf9000000 30 #define GIC_DIST_ADDR 0xf9010000 31 #define GIC_CPU_ADDR 0xf9020000 32 33 #define SATA_INTR 133 34 #define SATA_ADDR 0xFD0C0000 35 #define SATA_NUM_PORTS 2 36 37 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 38 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 39 }; 40 41 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 42 57, 59, 61, 63, 43 }; 44 45 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 46 0xFF000000, 0xFF010000, 47 }; 48 49 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 50 21, 22, 51 }; 52 53 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 54 0xFF160000, 0xFF170000, 55 }; 56 57 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 58 48, 49, 59 }; 60 61 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 62 0xFF040000, 0xFF050000, 63 }; 64 65 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 66 19, 20, 67 }; 68 69 typedef struct XlnxZynqMPGICRegion { 70 int region_index; 71 uint32_t address; 72 } XlnxZynqMPGICRegion; 73 74 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 75 { .region_index = 0, .address = GIC_DIST_ADDR, }, 76 { .region_index = 1, .address = GIC_CPU_ADDR, }, 77 }; 78 79 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 80 { 81 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 82 } 83 84 static void xlnx_zynqmp_init(Object *obj) 85 { 86 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 87 int i; 88 89 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 90 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 91 "cortex-a53-" TYPE_ARM_CPU); 92 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 93 &error_abort); 94 } 95 96 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 97 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 98 "cortex-r5-" TYPE_ARM_CPU); 99 object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), 100 &error_abort); 101 } 102 103 object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, 104 (Object **)&s->ddr_ram, 105 qdev_prop_allow_set_link_before_realize, 106 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 107 108 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 109 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 110 111 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 112 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 113 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 114 } 115 116 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 117 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 118 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 119 } 120 121 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 122 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 123 124 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 125 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 126 TYPE_SYSBUS_SDHCI); 127 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 128 sysbus_get_default()); 129 } 130 131 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 132 object_initialize(&s->spi[i], sizeof(s->spi[i]), 133 TYPE_XILINX_SPIPS); 134 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 135 } 136 } 137 138 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 139 { 140 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 141 MemoryRegion *system_memory = get_system_memory(); 142 uint8_t i; 143 uint64_t ram_size; 144 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 145 ram_addr_t ddr_low_size, ddr_high_size; 146 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 147 Error *err = NULL; 148 149 ram_size = memory_region_size(s->ddr_ram); 150 151 /* Create the DDR Memory Regions. User friendly checks should happen at 152 * the board level 153 */ 154 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 155 /* The RAM size is above the maximum available for the low DDR. 156 * Create the high DDR memory region as well. 157 */ 158 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 159 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 160 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 161 162 memory_region_init_alias(&s->ddr_ram_high, NULL, 163 "ddr-ram-high", s->ddr_ram, 164 ddr_low_size, ddr_high_size); 165 memory_region_add_subregion(get_system_memory(), 166 XLNX_ZYNQMP_HIGH_RAM_START, 167 &s->ddr_ram_high); 168 } else { 169 /* RAM must be non-zero */ 170 assert(ram_size); 171 ddr_low_size = ram_size; 172 } 173 174 memory_region_init_alias(&s->ddr_ram_low, NULL, 175 "ddr-ram-low", s->ddr_ram, 176 0, ddr_low_size); 177 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 178 179 /* Create the four OCM banks */ 180 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 181 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 182 183 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 184 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 185 vmstate_register_ram_global(&s->ocm_ram[i]); 186 memory_region_add_subregion(get_system_memory(), 187 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 188 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 189 &s->ocm_ram[i]); 190 191 g_free(ocm_name); 192 } 193 194 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 195 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 196 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 197 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 198 if (err) { 199 error_propagate(errp, err); 200 return; 201 } 202 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 203 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 204 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 205 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 206 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 207 uint32_t addr = r->address; 208 int j; 209 210 sysbus_mmio_map(gic, r->region_index, addr); 211 212 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 213 MemoryRegion *alias = &s->gic_mr[i][j]; 214 215 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 216 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 217 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 218 memory_region_add_subregion(system_memory, addr, alias); 219 } 220 } 221 222 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 223 qemu_irq irq; 224 char *name; 225 226 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 227 "psci-conduit", &error_abort); 228 229 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 230 if (strcmp(name, boot_cpu)) { 231 /* Secondary CPUs start in PSCI powered-down state */ 232 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 233 "start-powered-off", &error_abort); 234 } else { 235 s->boot_cpu_ptr = &s->apu_cpu[i]; 236 } 237 g_free(name); 238 239 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 240 "reset-cbar", &error_abort); 241 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 242 &err); 243 if (err) { 244 error_propagate(errp, err); 245 return; 246 } 247 248 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 249 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 250 ARM_CPU_IRQ)); 251 irq = qdev_get_gpio_in(DEVICE(&s->gic), 252 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 253 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 254 irq = qdev_get_gpio_in(DEVICE(&s->gic), 255 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 256 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 257 } 258 259 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 260 char *name; 261 262 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 263 if (strcmp(name, boot_cpu)) { 264 /* Secondary CPUs start in PSCI powered-down state */ 265 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 266 "start-powered-off", &error_abort); 267 } else { 268 s->boot_cpu_ptr = &s->rpu_cpu[i]; 269 } 270 g_free(name); 271 272 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 273 &error_abort); 274 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 275 &err); 276 if (err) { 277 error_propagate(errp, err); 278 return; 279 } 280 } 281 282 if (!s->boot_cpu_ptr) { 283 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 284 return; 285 } 286 287 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 288 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 289 } 290 291 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 292 NICInfo *nd = &nd_table[i]; 293 294 if (nd->used) { 295 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 296 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 297 } 298 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 299 if (err) { 300 error_propagate(errp, err); 301 return; 302 } 303 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 305 gic_spi[gem_intr[i]]); 306 } 307 308 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 309 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 310 if (err) { 311 error_propagate(errp, err); 312 return; 313 } 314 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 316 gic_spi[uart_intr[i]]); 317 } 318 319 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 320 &error_abort); 321 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 322 if (err) { 323 error_propagate(errp, err); 324 return; 325 } 326 327 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 329 330 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 331 char *bus_name; 332 333 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 334 "realized", &err); 335 if (err) { 336 error_propagate(errp, err); 337 return; 338 } 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 340 sdhci_addr[i]); 341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 342 gic_spi[sdhci_intr[i]]); 343 /* Alias controller SD bus to the SoC itself */ 344 bus_name = g_strdup_printf("sd-bus%d", i); 345 object_property_add_alias(OBJECT(s), bus_name, 346 OBJECT(&s->sdhci[i]), "sd-bus", 347 &error_abort); 348 g_free(bus_name); 349 } 350 351 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 352 gchar *bus_name; 353 354 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 355 356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 357 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 358 gic_spi[spi_intr[i]]); 359 360 /* Alias controller SPI bus to the SoC itself */ 361 bus_name = g_strdup_printf("spi%d", i); 362 object_property_add_alias(OBJECT(s), bus_name, 363 OBJECT(&s->spi[i]), "spi0", 364 &error_abort); 365 g_free(bus_name); 366 } 367 } 368 369 static Property xlnx_zynqmp_props[] = { 370 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 371 DEFINE_PROP_END_OF_LIST() 372 }; 373 374 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 375 { 376 DeviceClass *dc = DEVICE_CLASS(oc); 377 378 dc->props = xlnx_zynqmp_props; 379 dc->realize = xlnx_zynqmp_realize; 380 381 /* 382 * Reason: creates an ARM CPU, thus use after free(), see 383 * arm_cpu_class_init() 384 */ 385 dc->cannot_destroy_with_object_finalize_yet = true; 386 } 387 388 static const TypeInfo xlnx_zynqmp_type_info = { 389 .name = TYPE_XLNX_ZYNQMP, 390 .parent = TYPE_DEVICE, 391 .instance_size = sizeof(XlnxZynqMPState), 392 .instance_init = xlnx_zynqmp_init, 393 .class_init = xlnx_zynqmp_class_init, 394 }; 395 396 static void xlnx_zynqmp_register_types(void) 397 { 398 type_register_static(&xlnx_zynqmp_type_info); 399 } 400 401 type_init(xlnx_zynqmp_register_types) 402