1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "hw/boards.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/kvm.h" 27 #include "kvm_arm.h" 28 29 #define GIC_NUM_SPI_INTR 160 30 31 #define ARM_PHYS_TIMER_PPI 30 32 #define ARM_VIRT_TIMER_PPI 27 33 #define ARM_HYP_TIMER_PPI 26 34 #define ARM_SEC_TIMER_PPI 29 35 #define GIC_MAINTENANCE_PPI 25 36 37 #define GEM_REVISION 0x40070106 38 39 #define GIC_BASE_ADDR 0xf9000000 40 #define GIC_DIST_ADDR 0xf9010000 41 #define GIC_CPU_ADDR 0xf9020000 42 #define GIC_VIFACE_ADDR 0xf9040000 43 #define GIC_VCPU_ADDR 0xf9060000 44 45 #define SATA_INTR 133 46 #define SATA_ADDR 0xFD0C0000 47 #define SATA_NUM_PORTS 2 48 49 #define QSPI_ADDR 0xff0f0000 50 #define LQSPI_ADDR 0xc0000000 51 #define QSPI_IRQ 15 52 53 #define DP_ADDR 0xfd4a0000 54 #define DP_IRQ 113 55 56 #define DPDMA_ADDR 0xfd4c0000 57 #define DPDMA_IRQ 116 58 59 #define IPI_ADDR 0xFF300000 60 #define IPI_IRQ 64 61 62 #define RTC_ADDR 0xffa60000 63 #define RTC_IRQ 26 64 65 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 66 67 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 68 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 69 }; 70 71 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 72 57, 59, 61, 63, 73 }; 74 75 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 76 0xFF000000, 0xFF010000, 77 }; 78 79 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 80 21, 22, 81 }; 82 83 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 84 0xFF160000, 0xFF170000, 85 }; 86 87 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 88 48, 49, 89 }; 90 91 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 92 0xFF040000, 0xFF050000, 93 }; 94 95 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 96 19, 20, 97 }; 98 99 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 100 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 101 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 102 }; 103 104 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 105 124, 125, 126, 127, 128, 129, 130, 131 106 }; 107 108 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 109 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 110 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 111 }; 112 113 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 114 77, 78, 79, 80, 81, 82, 83, 84 115 }; 116 117 typedef struct XlnxZynqMPGICRegion { 118 int region_index; 119 uint32_t address; 120 uint32_t offset; 121 bool virt; 122 } XlnxZynqMPGICRegion; 123 124 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 125 /* Distributor */ 126 { 127 .region_index = 0, 128 .address = GIC_DIST_ADDR, 129 .offset = 0, 130 .virt = false 131 }, 132 133 /* CPU interface */ 134 { 135 .region_index = 1, 136 .address = GIC_CPU_ADDR, 137 .offset = 0, 138 .virt = false 139 }, 140 { 141 .region_index = 1, 142 .address = GIC_CPU_ADDR + 0x10000, 143 .offset = 0x1000, 144 .virt = false 145 }, 146 147 /* Virtual interface */ 148 { 149 .region_index = 2, 150 .address = GIC_VIFACE_ADDR, 151 .offset = 0, 152 .virt = true 153 }, 154 155 /* Virtual CPU interface */ 156 { 157 .region_index = 3, 158 .address = GIC_VCPU_ADDR, 159 .offset = 0, 160 .virt = true 161 }, 162 { 163 .region_index = 3, 164 .address = GIC_VCPU_ADDR + 0x10000, 165 .offset = 0x1000, 166 .virt = true 167 }, 168 }; 169 170 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 171 { 172 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 173 } 174 175 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 176 const char *boot_cpu, Error **errp) 177 { 178 Error *err = NULL; 179 int i; 180 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 181 XLNX_ZYNQMP_NUM_RPU_CPUS); 182 183 if (num_rpus <= 0) { 184 /* Don't create rpu-cluster object if there's nothing to put in it */ 185 return; 186 } 187 188 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 189 sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, 190 &error_abort, NULL); 191 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 192 193 for (i = 0; i < num_rpus; i++) { 194 char *name; 195 196 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 197 &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 198 "cortex-r5f-" TYPE_ARM_CPU, &error_abort, 199 NULL); 200 201 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 202 if (strcmp(name, boot_cpu)) { 203 /* Secondary CPUs start in PSCI powered-down state */ 204 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 205 "start-powered-off", &error_abort); 206 } else { 207 s->boot_cpu_ptr = &s->rpu_cpu[i]; 208 } 209 g_free(name); 210 211 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 212 &error_abort); 213 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 214 &err); 215 if (err) { 216 error_propagate(errp, err); 217 return; 218 } 219 } 220 221 qdev_init_nofail(DEVICE(&s->rpu_cluster)); 222 } 223 224 static void xlnx_zynqmp_init(Object *obj) 225 { 226 MachineState *ms = MACHINE(qdev_get_machine()); 227 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 228 int i; 229 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 230 231 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 232 sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, 233 &error_abort, NULL); 234 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 235 236 for (i = 0; i < num_apus; i++) { 237 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 238 &s->apu_cpu[i], sizeof(s->apu_cpu[i]), 239 "cortex-a53-" TYPE_ARM_CPU, &error_abort, 240 NULL); 241 } 242 243 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), 244 gic_class_name()); 245 246 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 247 sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]), 248 TYPE_CADENCE_GEM); 249 } 250 251 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 252 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 253 TYPE_CADENCE_UART); 254 } 255 256 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 257 TYPE_SYSBUS_AHCI); 258 259 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 260 sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i], 261 sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI); 262 } 263 264 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 265 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), 266 TYPE_XILINX_SPIPS); 267 } 268 269 sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi), 270 TYPE_XLNX_ZYNQMP_QSPIPS); 271 272 sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP); 273 274 sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma), 275 TYPE_XLNX_DPDMA); 276 277 sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi), 278 TYPE_XLNX_ZYNQMP_IPI); 279 280 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), 281 TYPE_XLNX_ZYNQMP_RTC); 282 283 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 284 sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]), 285 TYPE_XLNX_ZDMA); 286 } 287 288 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 289 sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]), 290 TYPE_XLNX_ZDMA); 291 } 292 } 293 294 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 295 { 296 MachineState *ms = MACHINE(qdev_get_machine()); 297 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 298 MemoryRegion *system_memory = get_system_memory(); 299 uint8_t i; 300 uint64_t ram_size; 301 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 302 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 303 ram_addr_t ddr_low_size, ddr_high_size; 304 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 305 Error *err = NULL; 306 307 ram_size = memory_region_size(s->ddr_ram); 308 309 /* Create the DDR Memory Regions. User friendly checks should happen at 310 * the board level 311 */ 312 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 313 /* The RAM size is above the maximum available for the low DDR. 314 * Create the high DDR memory region as well. 315 */ 316 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 317 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 318 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 319 320 memory_region_init_alias(&s->ddr_ram_high, NULL, 321 "ddr-ram-high", s->ddr_ram, 322 ddr_low_size, ddr_high_size); 323 memory_region_add_subregion(get_system_memory(), 324 XLNX_ZYNQMP_HIGH_RAM_START, 325 &s->ddr_ram_high); 326 } else { 327 /* RAM must be non-zero */ 328 assert(ram_size); 329 ddr_low_size = ram_size; 330 } 331 332 memory_region_init_alias(&s->ddr_ram_low, NULL, 333 "ddr-ram-low", s->ddr_ram, 334 0, ddr_low_size); 335 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 336 337 /* Create the four OCM banks */ 338 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 339 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 340 341 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 342 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 343 memory_region_add_subregion(get_system_memory(), 344 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 345 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 346 &s->ocm_ram[i]); 347 348 g_free(ocm_name); 349 } 350 351 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 352 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 353 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 354 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 355 qdev_prop_set_bit(DEVICE(&s->gic), 356 "has-virtualization-extensions", s->virt); 357 358 qdev_init_nofail(DEVICE(&s->apu_cluster)); 359 360 /* Realize APUs before realizing the GIC. KVM requires this. */ 361 for (i = 0; i < num_apus; i++) { 362 char *name; 363 364 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 365 "psci-conduit", &error_abort); 366 367 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 368 if (strcmp(name, boot_cpu)) { 369 /* Secondary CPUs start in PSCI powered-down state */ 370 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 371 "start-powered-off", &error_abort); 372 } else { 373 s->boot_cpu_ptr = &s->apu_cpu[i]; 374 } 375 g_free(name); 376 377 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 378 s->secure, "has_el3", NULL); 379 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 380 s->virt, "has_el2", NULL); 381 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 382 "reset-cbar", &error_abort); 383 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 384 "core-count", &error_abort); 385 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 386 &err); 387 if (err) { 388 error_propagate(errp, err); 389 return; 390 } 391 } 392 393 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 394 if (err) { 395 error_propagate(errp, err); 396 return; 397 } 398 399 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 400 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 401 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 402 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 403 MemoryRegion *mr; 404 uint32_t addr = r->address; 405 int j; 406 407 if (r->virt && !s->virt) { 408 continue; 409 } 410 411 mr = sysbus_mmio_get_region(gic, r->region_index); 412 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 413 MemoryRegion *alias = &s->gic_mr[i][j]; 414 415 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 416 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 417 memory_region_add_subregion(system_memory, addr, alias); 418 419 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 420 } 421 } 422 423 for (i = 0; i < num_apus; i++) { 424 qemu_irq irq; 425 426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 427 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 428 ARM_CPU_IRQ)); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 430 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 431 ARM_CPU_FIQ)); 432 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 433 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 434 ARM_CPU_VIRQ)); 435 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 436 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 437 ARM_CPU_VFIQ)); 438 irq = qdev_get_gpio_in(DEVICE(&s->gic), 439 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 440 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 441 irq = qdev_get_gpio_in(DEVICE(&s->gic), 442 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 443 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 444 irq = qdev_get_gpio_in(DEVICE(&s->gic), 445 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 446 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 447 irq = qdev_get_gpio_in(DEVICE(&s->gic), 448 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 449 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 450 451 if (s->virt) { 452 irq = qdev_get_gpio_in(DEVICE(&s->gic), 453 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 455 } 456 } 457 458 if (s->has_rpu) { 459 info_report("The 'has_rpu' property is no longer required, to use the " 460 "RPUs just use -smp 6."); 461 } 462 463 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 464 if (err) { 465 error_propagate(errp, err); 466 return; 467 } 468 469 if (!s->boot_cpu_ptr) { 470 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 471 return; 472 } 473 474 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 475 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 476 } 477 478 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 479 NICInfo *nd = &nd_table[i]; 480 481 if (nd->used) { 482 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 483 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 484 } 485 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 486 &error_abort); 487 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 488 &error_abort); 489 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 490 if (err) { 491 error_propagate(errp, err); 492 return; 493 } 494 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 495 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 496 gic_spi[gem_intr[i]]); 497 } 498 499 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 500 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 501 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 502 if (err) { 503 error_propagate(errp, err); 504 return; 505 } 506 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 507 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 508 gic_spi[uart_intr[i]]); 509 } 510 511 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 512 &error_abort); 513 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 514 if (err) { 515 error_propagate(errp, err); 516 return; 517 } 518 519 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 521 522 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 523 char *bus_name = g_strdup_printf("sd-bus%d", i); 524 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 525 Object *sdhci = OBJECT(&s->sdhci[i]); 526 527 /* Compatible with: 528 * - SD Host Controller Specification Version 3.00 529 * - SDIO Specification Version 3.0 530 * - eMMC Specification Version 4.51 531 */ 532 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 533 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 534 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 535 object_property_set_bool(sdhci, true, "realized", &err); 536 if (err) { 537 error_propagate(errp, err); 538 return; 539 } 540 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 541 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 542 543 /* Alias controller SD bus to the SoC itself */ 544 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus", 545 &error_abort); 546 g_free(bus_name); 547 } 548 549 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 550 gchar *bus_name; 551 552 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 553 554 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 555 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 556 gic_spi[spi_intr[i]]); 557 558 /* Alias controller SPI bus to the SoC itself */ 559 bus_name = g_strdup_printf("spi%d", i); 560 object_property_add_alias(OBJECT(s), bus_name, 561 OBJECT(&s->spi[i]), "spi0", 562 &error_abort); 563 g_free(bus_name); 564 } 565 566 object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); 567 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 568 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 569 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 570 571 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 572 gchar *bus_name; 573 gchar *target_bus; 574 575 /* Alias controller SPI bus to the SoC itself */ 576 bus_name = g_strdup_printf("qspi%d", i); 577 target_bus = g_strdup_printf("spi%d", i); 578 object_property_add_alias(OBJECT(s), bus_name, 579 OBJECT(&s->qspi), target_bus, 580 &error_abort); 581 g_free(bus_name); 582 g_free(target_bus); 583 } 584 585 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 586 if (err) { 587 error_propagate(errp, err); 588 return; 589 } 590 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 591 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 592 593 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 594 if (err) { 595 error_propagate(errp, err); 596 return; 597 } 598 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 599 &error_abort); 600 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 601 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 602 603 object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err); 604 if (err) { 605 error_propagate(errp, err); 606 return; 607 } 608 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 609 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 610 611 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 612 if (err) { 613 error_propagate(errp, err); 614 return; 615 } 616 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 617 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 618 619 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 620 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 621 object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err); 622 if (err) { 623 error_propagate(errp, err); 624 return; 625 } 626 627 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 628 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 629 gic_spi[gdma_ch_intr[i]]); 630 } 631 632 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 633 object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err); 634 if (err) { 635 error_propagate(errp, err); 636 return; 637 } 638 639 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 640 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 641 gic_spi[adma_ch_intr[i]]); 642 } 643 } 644 645 static Property xlnx_zynqmp_props[] = { 646 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 647 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 648 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 649 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 650 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 651 MemoryRegion *), 652 DEFINE_PROP_END_OF_LIST() 653 }; 654 655 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 656 { 657 DeviceClass *dc = DEVICE_CLASS(oc); 658 659 dc->props = xlnx_zynqmp_props; 660 dc->realize = xlnx_zynqmp_realize; 661 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 662 dc->user_creatable = false; 663 } 664 665 static const TypeInfo xlnx_zynqmp_type_info = { 666 .name = TYPE_XLNX_ZYNQMP, 667 .parent = TYPE_DEVICE, 668 .instance_size = sizeof(XlnxZynqMPState), 669 .instance_init = xlnx_zynqmp_init, 670 .class_init = xlnx_zynqmp_class_init, 671 }; 672 673 static void xlnx_zynqmp_register_types(void) 674 { 675 type_register_static(&xlnx_zynqmp_type_info); 676 } 677 678 type_init(xlnx_zynqmp_register_types) 679