1 /* 2 * Xilinx ZynqMP ZCU102 board 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "hw/arm/xlnx-zynqmp.h" 21 #include "hw/boards.h" 22 #include "qemu/error-report.h" 23 #include "qemu/log.h" 24 #include "sysemu/device_tree.h" 25 #include "qom/object.h" 26 #include "net/can_emu.h" 27 28 struct XlnxZCU102 { 29 MachineState parent_obj; 30 31 XlnxZynqMPState soc; 32 33 bool secure; 34 bool virt; 35 36 CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; 37 38 struct arm_boot_info binfo; 39 }; 40 41 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") 42 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZCU102, ZCU102_MACHINE) 43 44 45 static bool zcu102_get_secure(Object *obj, Error **errp) 46 { 47 XlnxZCU102 *s = ZCU102_MACHINE(obj); 48 49 return s->secure; 50 } 51 52 static void zcu102_set_secure(Object *obj, bool value, Error **errp) 53 { 54 XlnxZCU102 *s = ZCU102_MACHINE(obj); 55 56 s->secure = value; 57 } 58 59 static bool zcu102_get_virt(Object *obj, Error **errp) 60 { 61 XlnxZCU102 *s = ZCU102_MACHINE(obj); 62 63 return s->virt; 64 } 65 66 static void zcu102_set_virt(Object *obj, bool value, Error **errp) 67 { 68 XlnxZCU102 *s = ZCU102_MACHINE(obj); 69 70 s->virt = value; 71 } 72 73 static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt) 74 { 75 XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo); 76 bool method_is_hvc; 77 char **node_path; 78 const char *r; 79 int prop_len; 80 int i; 81 82 /* If EL3 is enabled, we keep all firmware nodes active. */ 83 if (!s->secure) { 84 node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware", 85 &error_fatal); 86 87 for (i = 0; node_path && node_path[i]; i++) { 88 r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL); 89 method_is_hvc = r && !strcmp("hvc", r); 90 91 /* Allow HVC based firmware if EL2 is enabled. */ 92 if (method_is_hvc && s->virt) { 93 continue; 94 } 95 qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled"); 96 } 97 g_strfreev(node_path); 98 } 99 } 100 101 static void bbram_attach_drive(XlnxBBRam *dev) 102 { 103 DriveInfo *dinfo; 104 BlockBackend *blk; 105 106 dinfo = drive_get_by_index(IF_PFLASH, 2); 107 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 108 if (blk) { 109 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 110 } 111 } 112 113 static void efuse_attach_drive(XlnxEFuse *dev) 114 { 115 DriveInfo *dinfo; 116 BlockBackend *blk; 117 118 dinfo = drive_get_by_index(IF_PFLASH, 3); 119 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 120 if (blk) { 121 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 122 } 123 } 124 125 static void xlnx_zcu102_init(MachineState *machine) 126 { 127 XlnxZCU102 *s = ZCU102_MACHINE(machine); 128 int i; 129 uint64_t ram_size = machine->ram_size; 130 131 /* Create the memory region to pass to the SoC */ 132 if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) { 133 error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of " 134 "0x%llx", ram_size, 135 XLNX_ZYNQMP_MAX_RAM_SIZE); 136 exit(1); 137 } 138 139 if (ram_size < 0x08000000) { 140 qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102", 141 ram_size); 142 } 143 144 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP); 145 146 object_property_set_link(OBJECT(&s->soc), "ddr-ram", OBJECT(machine->ram), 147 &error_abort); 148 object_property_set_bool(OBJECT(&s->soc), "secure", s->secure, 149 &error_fatal); 150 object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, 151 &error_fatal); 152 153 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 154 gchar *bus_name = g_strdup_printf("canbus%d", i); 155 156 object_property_set_link(OBJECT(&s->soc), bus_name, 157 OBJECT(s->canbus[i]), &error_fatal); 158 g_free(bus_name); 159 } 160 161 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 162 163 /* Attach bbram backend, if given */ 164 bbram_attach_drive(&s->soc.bbram); 165 166 /* Attach efuse backend, if given */ 167 efuse_attach_drive(&s->soc.efuse); 168 169 /* Create and plug in the SD cards */ 170 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 171 BusState *bus; 172 DriveInfo *di = drive_get(IF_SD, 0, i); 173 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 174 DeviceState *carddev; 175 char *bus_name; 176 177 bus_name = g_strdup_printf("sd-bus%d", i); 178 bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name); 179 g_free(bus_name); 180 if (!bus) { 181 error_report("No SD bus found for SD card %d", i); 182 exit(1); 183 } 184 carddev = qdev_new(TYPE_SD_CARD); 185 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 186 qdev_realize_and_unref(carddev, bus, &error_fatal); 187 } 188 189 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 190 BusState *spi_bus; 191 DeviceState *flash_dev; 192 qemu_irq cs_line; 193 DriveInfo *dinfo = drive_get(IF_MTD, 0, i); 194 gchar *bus_name = g_strdup_printf("spi%d", i); 195 196 spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name); 197 g_free(bus_name); 198 199 flash_dev = qdev_new("sst25wf080"); 200 if (dinfo) { 201 qdev_prop_set_drive_err(flash_dev, "drive", 202 blk_by_legacy_dinfo(dinfo), &error_fatal); 203 } 204 qdev_prop_set_uint8(flash_dev, "cs", i); 205 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); 206 207 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 208 209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); 210 } 211 212 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { 213 BusState *spi_bus; 214 DeviceState *flash_dev; 215 qemu_irq cs_line; 216 DriveInfo *dinfo = drive_get(IF_MTD, 0, XLNX_ZYNQMP_NUM_SPIS + i); 217 int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; 218 gchar *bus_name = g_strdup_printf("qspi%d", bus); 219 220 spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name); 221 g_free(bus_name); 222 223 flash_dev = qdev_new("n25q512a11"); 224 if (dinfo) { 225 qdev_prop_set_drive_err(flash_dev, "drive", 226 blk_by_legacy_dinfo(dinfo), &error_fatal); 227 } 228 qdev_prop_set_uint8(flash_dev, "cs", i); 229 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); 230 231 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 232 233 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); 234 } 235 236 /* TODO create and connect IDE devices for ide_drive_get() */ 237 238 s->binfo.ram_size = ram_size; 239 s->binfo.loader_start = 0; 240 s->binfo.modify_dtb = zcu102_modify_dtb; 241 s->binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; 242 arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); 243 } 244 245 static void xlnx_zcu102_machine_instance_init(Object *obj) 246 { 247 XlnxZCU102 *s = ZCU102_MACHINE(obj); 248 249 /* Default to secure mode being disabled */ 250 s->secure = false; 251 /* Default to virt (EL2) being disabled */ 252 s->virt = false; 253 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 254 (Object **)&s->canbus[0], 255 object_property_allow_set_link, 256 0); 257 258 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 259 (Object **)&s->canbus[1], 260 object_property_allow_set_link, 261 0); 262 } 263 264 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) 265 { 266 MachineClass *mc = MACHINE_CLASS(oc); 267 268 mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \ 269 "the value of smp"; 270 mc->init = xlnx_zcu102_init; 271 mc->block_default_type = IF_IDE; 272 mc->units_per_default_bus = 1; 273 mc->ignore_memory_transaction_failures = true; 274 mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; 275 mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; 276 mc->default_ram_id = "ddr-ram"; 277 278 object_class_property_add_bool(oc, "secure", zcu102_get_secure, 279 zcu102_set_secure); 280 object_class_property_set_description(oc, "secure", 281 "Set on/off to enable/disable the ARM " 282 "Security Extensions (TrustZone)"); 283 284 object_class_property_add_bool(oc, "virtualization", zcu102_get_virt, 285 zcu102_set_virt); 286 object_class_property_set_description(oc, "virtualization", 287 "Set on/off to enable/disable emulating a " 288 "guest CPU which implements the ARM " 289 "Virtualization Extensions"); 290 } 291 292 static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { 293 .name = TYPE_ZCU102_MACHINE, 294 .parent = TYPE_MACHINE, 295 .class_init = xlnx_zcu102_machine_class_init, 296 .instance_init = xlnx_zcu102_machine_instance_init, 297 .instance_size = sizeof(XlnxZCU102), 298 }; 299 300 static void xlnx_zcu102_machine_init_register_types(void) 301 { 302 type_register_static(&xlnx_zcu102_machine_init_typeinfo); 303 } 304 305 type_init(xlnx_zcu102_machine_init_register_types) 306