1 /* 2 * Xilinx Versal SoC model. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/units.h" 14 #include "qapi/error.h" 15 #include "qapi/qmp/qlist.h" 16 #include "qemu/module.h" 17 #include "hw/sysbus.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 #include "sysemu/kvm.h" 21 #include "hw/arm/boot.h" 22 #include "kvm_arm.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/arm/xlnx-versal.h" 25 #include "qemu/log.h" 26 #include "target/arm/cpu-qom.h" 27 #include "target/arm/gtimer.h" 28 29 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") 30 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") 31 #define GEM_REVISION 0x40070106 32 33 #define VERSAL_NUM_PMC_APB_IRQS 18 34 #define NUM_OSPI_IRQ_LINES 3 35 36 static void versal_create_apu_cpus(Versal *s) 37 { 38 int i; 39 40 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, 41 TYPE_CPU_CLUSTER); 42 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); 43 44 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { 45 Object *obj; 46 47 object_initialize_child(OBJECT(&s->fpd.apu.cluster), 48 "apu-cpu[*]", &s->fpd.apu.cpu[i], 49 XLNX_VERSAL_ACPU_TYPE); 50 obj = OBJECT(&s->fpd.apu.cpu[i]); 51 if (i) { 52 /* Secondary CPUs start in powered-down state */ 53 object_property_set_bool(obj, "start-powered-off", true, 54 &error_abort); 55 } 56 57 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), 58 &error_abort); 59 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr), 60 &error_abort); 61 qdev_realize(DEVICE(obj), NULL, &error_fatal); 62 } 63 64 qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); 65 } 66 67 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) 68 { 69 static const uint64_t addrs[] = { 70 MM_GIC_APU_DIST_MAIN, 71 MM_GIC_APU_REDIST_0 72 }; 73 SysBusDevice *gicbusdev; 74 DeviceState *gicdev; 75 QList *redist_region_count; 76 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); 77 int i; 78 79 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, 80 gicv3_class_name()); 81 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); 82 gicdev = DEVICE(&s->fpd.apu.gic); 83 qdev_prop_set_uint32(gicdev, "revision", 3); 84 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus); 85 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); 86 87 redist_region_count = qlist_new(); 88 qlist_append_int(redist_region_count, nr_apu_cpus); 89 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 90 91 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 92 93 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); 94 95 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 96 MemoryRegion *mr; 97 98 mr = sysbus_mmio_get_region(gicbusdev, i); 99 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); 100 } 101 102 for (i = 0; i < nr_apu_cpus; i++) { 103 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); 104 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 105 qemu_irq maint_irq; 106 int ti; 107 /* Mapping from the output timer irq lines from the CPU to the 108 * GIC PPI inputs. 109 */ 110 const int timer_irq[] = { 111 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, 112 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, 113 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, 114 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, 115 }; 116 117 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { 118 qdev_connect_gpio_out(cpudev, ti, 119 qdev_get_gpio_in(gicdev, 120 ppibase + timer_irq[ti])); 121 } 122 maint_irq = qdev_get_gpio_in(gicdev, 123 ppibase + VERSAL_GIC_MAINT_IRQ); 124 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 125 0, maint_irq); 126 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 127 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, 128 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 129 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, 130 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 131 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, 132 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 133 } 134 135 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { 136 pic[i] = qdev_get_gpio_in(gicdev, i); 137 } 138 } 139 140 static void versal_create_rpu_cpus(Versal *s) 141 { 142 int i; 143 144 object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, 145 TYPE_CPU_CLUSTER); 146 qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); 147 148 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 149 Object *obj; 150 151 object_initialize_child(OBJECT(&s->lpd.rpu.cluster), 152 "rpu-cpu[*]", &s->lpd.rpu.cpu[i], 153 XLNX_VERSAL_RCPU_TYPE); 154 obj = OBJECT(&s->lpd.rpu.cpu[i]); 155 object_property_set_bool(obj, "start-powered-off", true, 156 &error_abort); 157 158 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); 159 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), 160 &error_abort); 161 object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), 162 &error_abort); 163 qdev_realize(DEVICE(obj), NULL, &error_fatal); 164 } 165 166 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); 167 } 168 169 static void versal_create_uarts(Versal *s, qemu_irq *pic) 170 { 171 int i; 172 173 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 174 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; 175 static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; 176 char *name = g_strdup_printf("uart%d", i); 177 DeviceState *dev; 178 MemoryRegion *mr; 179 180 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], 181 TYPE_PL011); 182 dev = DEVICE(&s->lpd.iou.uart[i]); 183 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 184 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 185 186 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 187 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 188 189 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 190 g_free(name); 191 } 192 } 193 194 static void versal_create_canfds(Versal *s, qemu_irq *pic) 195 { 196 int i; 197 uint32_t irqs[] = { VERSAL_CANFD0_IRQ_0, VERSAL_CANFD1_IRQ_0}; 198 uint64_t addrs[] = { MM_CANFD0, MM_CANFD1 }; 199 200 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.canfd); i++) { 201 char *name = g_strdup_printf("canfd%d", i); 202 SysBusDevice *sbd; 203 MemoryRegion *mr; 204 205 object_initialize_child(OBJECT(s), name, &s->lpd.iou.canfd[i], 206 TYPE_XILINX_CANFD); 207 sbd = SYS_BUS_DEVICE(&s->lpd.iou.canfd[i]); 208 209 object_property_set_int(OBJECT(&s->lpd.iou.canfd[i]), "ext_clk_freq", 210 XLNX_VERSAL_CANFD_REF_CLK , &error_abort); 211 212 object_property_set_link(OBJECT(&s->lpd.iou.canfd[i]), "canfdbus", 213 OBJECT(s->lpd.iou.canbus[i]), 214 &error_abort); 215 216 sysbus_realize(sbd, &error_fatal); 217 218 mr = sysbus_mmio_get_region(sbd, 0); 219 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 220 221 sysbus_connect_irq(sbd, 0, pic[irqs[i]]); 222 g_free(name); 223 } 224 } 225 226 static void versal_create_usbs(Versal *s, qemu_irq *pic) 227 { 228 DeviceState *dev; 229 MemoryRegion *mr; 230 231 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, 232 TYPE_XILINX_VERSAL_USB2); 233 dev = DEVICE(&s->lpd.iou.usb); 234 235 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 236 &error_abort); 237 qdev_prop_set_uint32(dev, "intrs", 1); 238 qdev_prop_set_uint32(dev, "slots", 2); 239 240 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 241 242 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 243 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); 244 245 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); 246 247 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 248 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); 249 } 250 251 static void versal_create_gems(Versal *s, qemu_irq *pic) 252 { 253 int i; 254 255 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 256 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; 257 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; 258 char *name = g_strdup_printf("gem%d", i); 259 NICInfo *nd = &nd_table[i]; 260 DeviceState *dev; 261 MemoryRegion *mr; 262 263 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], 264 TYPE_CADENCE_GEM); 265 dev = DEVICE(&s->lpd.iou.gem[i]); 266 /* FIXME use qdev NIC properties instead of nd_table[] */ 267 if (nd->used) { 268 qemu_check_nic_model(nd, "cadence_gem"); 269 qdev_set_nic_properties(dev, nd); 270 } 271 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); 272 object_property_set_int(OBJECT(dev), "num-priority-queues", 2, 273 &error_abort); 274 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 275 &error_abort); 276 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 277 278 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 279 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 280 281 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 282 g_free(name); 283 } 284 } 285 286 static void versal_create_admas(Versal *s, qemu_irq *pic) 287 { 288 int i; 289 290 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 291 char *name = g_strdup_printf("adma%d", i); 292 DeviceState *dev; 293 MemoryRegion *mr; 294 295 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 296 TYPE_XLNX_ZDMA); 297 dev = DEVICE(&s->lpd.iou.adma[i]); 298 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort); 299 object_property_set_link(OBJECT(dev), "dma", 300 OBJECT(get_system_memory()), &error_fatal); 301 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 302 303 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 304 memory_region_add_subregion(&s->mr_ps, 305 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); 306 307 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); 308 g_free(name); 309 } 310 } 311 312 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ 313 static void versal_create_sds(Versal *s, qemu_irq *pic) 314 { 315 int i; 316 317 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { 318 DeviceState *dev; 319 MemoryRegion *mr; 320 321 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], 322 TYPE_SYSBUS_SDHCI); 323 dev = DEVICE(&s->pmc.iou.sd[i]); 324 325 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3, 326 &error_fatal); 327 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES, 328 &error_fatal); 329 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal); 330 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 331 332 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 333 memory_region_add_subregion(&s->mr_ps, 334 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); 335 336 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 337 pic[VERSAL_SD0_IRQ_0 + i * 2]); 338 } 339 } 340 341 static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) 342 { 343 DeviceState *orgate; 344 345 /* 346 * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following 347 * models: 348 * - RTC 349 * - BBRAM 350 * - PMC SLCR 351 * - CFRAME regs (input 3 - 17 to the orgate) 352 */ 353 object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", 354 &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); 355 orgate = DEVICE(&s->pmc.apb_irq_orgate); 356 object_property_set_int(OBJECT(orgate), 357 "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal); 358 qdev_realize(orgate, NULL, &error_fatal); 359 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); 360 } 361 362 static void versal_create_rtc(Versal *s, qemu_irq *pic) 363 { 364 SysBusDevice *sbd; 365 MemoryRegion *mr; 366 367 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, 368 TYPE_XLNX_ZYNQMP_RTC); 369 sbd = SYS_BUS_DEVICE(&s->pmc.rtc); 370 sysbus_realize(sbd, &error_fatal); 371 372 mr = sysbus_mmio_get_region(sbd, 0); 373 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); 374 375 /* 376 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model 377 * supports them. 378 */ 379 sysbus_connect_irq(sbd, 1, 380 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); 381 } 382 383 static void versal_create_trng(Versal *s, qemu_irq *pic) 384 { 385 SysBusDevice *sbd; 386 MemoryRegion *mr; 387 388 object_initialize_child(OBJECT(s), "trng", &s->pmc.trng, 389 TYPE_XLNX_VERSAL_TRNG); 390 sbd = SYS_BUS_DEVICE(&s->pmc.trng); 391 sysbus_realize(sbd, &error_fatal); 392 393 mr = sysbus_mmio_get_region(sbd, 0); 394 memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr); 395 sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]); 396 } 397 398 static void versal_create_xrams(Versal *s, qemu_irq *pic) 399 { 400 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); 401 DeviceState *orgate; 402 int i; 403 404 /* XRAM IRQs get ORed into a single line. */ 405 object_initialize_child(OBJECT(s), "xram-irq-orgate", 406 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); 407 orgate = DEVICE(&s->lpd.xram.irq_orgate); 408 object_property_set_int(OBJECT(orgate), 409 "num-lines", nr_xrams, &error_fatal); 410 qdev_realize(orgate, NULL, &error_fatal); 411 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); 412 413 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { 414 SysBusDevice *sbd; 415 MemoryRegion *mr; 416 417 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], 418 TYPE_XLNX_XRAM_CTRL); 419 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); 420 sysbus_realize(sbd, &error_fatal); 421 422 mr = sysbus_mmio_get_region(sbd, 0); 423 memory_region_add_subregion(&s->mr_ps, 424 MM_XRAMC + i * MM_XRAMC_SIZE, mr); 425 mr = sysbus_mmio_get_region(sbd, 1); 426 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); 427 428 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); 429 } 430 } 431 432 static void versal_create_bbram(Versal *s, qemu_irq *pic) 433 { 434 SysBusDevice *sbd; 435 436 object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, 437 sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, 438 &error_fatal, 439 "crc-zpads", "0", 440 NULL); 441 sbd = SYS_BUS_DEVICE(&s->pmc.bbram); 442 443 sysbus_realize(sbd, &error_fatal); 444 memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, 445 sysbus_mmio_get_region(sbd, 0)); 446 sysbus_connect_irq(sbd, 0, 447 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1)); 448 } 449 450 static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) 451 { 452 SysBusDevice *part = SYS_BUS_DEVICE(dev); 453 454 object_property_set_link(OBJECT(part), "efuse", 455 OBJECT(&s->pmc.efuse), &error_abort); 456 457 sysbus_realize(part, &error_abort); 458 memory_region_add_subregion(&s->mr_ps, base, 459 sysbus_mmio_get_region(part, 0)); 460 } 461 462 static void versal_create_efuse(Versal *s, qemu_irq *pic) 463 { 464 Object *bits = OBJECT(&s->pmc.efuse); 465 Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); 466 Object *cache = OBJECT(&s->pmc.efuse_cache); 467 468 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, 469 TYPE_XLNX_VERSAL_EFUSE_CTRL); 470 471 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, 472 TYPE_XLNX_VERSAL_EFUSE_CACHE); 473 474 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 475 sizeof(s->pmc.efuse), 476 TYPE_XLNX_EFUSE, &error_abort, 477 "efuse-nr", "3", 478 "efuse-size", "8192", 479 NULL); 480 481 qdev_realize(DEVICE(bits), NULL, &error_abort); 482 versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); 483 versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); 484 485 sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); 486 } 487 488 static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) 489 { 490 SysBusDevice *sbd; 491 492 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, 493 TYPE_XILINX_VERSAL_PMC_IOU_SLCR); 494 495 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); 496 sysbus_realize(sbd, &error_fatal); 497 498 memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, 499 sysbus_mmio_get_region(sbd, 0)); 500 501 sysbus_connect_irq(sbd, 0, 502 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); 503 } 504 505 static void versal_create_ospi(Versal *s, qemu_irq *pic) 506 { 507 SysBusDevice *sbd; 508 MemoryRegion *mr_dac; 509 qemu_irq ospi_mux_sel; 510 DeviceState *orgate; 511 512 memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), 513 "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); 514 515 object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi, 516 TYPE_XILINX_VERSAL_OSPI); 517 518 mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1); 519 memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); 520 521 /* Create the OSPI destination DMA */ 522 object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", 523 &s->pmc.iou.ospi.dma_dst, 524 TYPE_XLNX_CSU_DMA); 525 526 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), 527 "dma", OBJECT(get_system_memory()), 528 &error_abort); 529 530 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); 531 sysbus_realize(sbd, &error_fatal); 532 533 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, 534 sysbus_mmio_get_region(sbd, 0)); 535 536 /* Create the OSPI source DMA */ 537 object_initialize_child(OBJECT(s), "versal-ospi-dma-src", 538 &s->pmc.iou.ospi.dma_src, 539 TYPE_XLNX_CSU_DMA); 540 541 object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", 542 false, &error_abort); 543 544 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 545 "dma", OBJECT(mr_dac), &error_abort); 546 547 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 548 "stream-connected-dma", 549 OBJECT(&s->pmc.iou.ospi.dma_dst), 550 &error_abort); 551 552 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); 553 sysbus_realize(sbd, &error_fatal); 554 555 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, 556 sysbus_mmio_get_region(sbd, 0)); 557 558 /* Realize the OSPI */ 559 object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", 560 OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort); 561 562 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); 563 sysbus_realize(sbd, &error_fatal); 564 565 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, 566 sysbus_mmio_get_region(sbd, 0)); 567 568 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, 569 &s->pmc.iou.ospi.linear_mr); 570 571 /* ospi_mux_sel */ 572 ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi), 573 "ospi-mux-sel", 0); 574 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, 575 ospi_mux_sel); 576 577 /* OSPI irq */ 578 object_initialize_child(OBJECT(s), "ospi-irq-orgate", 579 &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ); 580 object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate), 581 "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); 582 583 orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate); 584 qdev_realize(orgate, NULL, &error_fatal); 585 586 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, 587 qdev_get_gpio_in(orgate, 0)); 588 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, 589 qdev_get_gpio_in(orgate, 1)); 590 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, 591 qdev_get_gpio_in(orgate, 2)); 592 593 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); 594 } 595 596 static void versal_create_cfu(Versal *s, qemu_irq *pic) 597 { 598 SysBusDevice *sbd; 599 DeviceState *dev; 600 int i; 601 const struct { 602 uint64_t reg_base; 603 uint64_t fdri_base; 604 } cframe_addr[] = { 605 { MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI }, 606 { MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI }, 607 { MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI }, 608 { MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI }, 609 { MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI }, 610 { MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI }, 611 { MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI }, 612 { MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI }, 613 { MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI }, 614 { MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI }, 615 { MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI }, 616 { MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI }, 617 { MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI }, 618 { MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI }, 619 { MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI }, 620 }; 621 const struct { 622 uint32_t blktype0_frames; 623 uint32_t blktype1_frames; 624 uint32_t blktype2_frames; 625 uint32_t blktype3_frames; 626 uint32_t blktype4_frames; 627 uint32_t blktype5_frames; 628 uint32_t blktype6_frames; 629 } cframe_cfg[] = { 630 [0] = { 34111, 3528, 12800, 11, 5, 1, 1 }, 631 [1] = { 38498, 3841, 15361, 13, 7, 3, 1 }, 632 [2] = { 38498, 3841, 15361, 13, 7, 3, 1 }, 633 [3] = { 38498, 3841, 15361, 13, 7, 3, 1 }, 634 }; 635 636 /* CFU FDRO */ 637 object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro, 638 TYPE_XLNX_VERSAL_CFU_FDRO); 639 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro); 640 641 sysbus_realize(sbd, &error_fatal); 642 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO, 643 sysbus_mmio_get_region(sbd, 0)); 644 645 /* CFRAME REG */ 646 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { 647 g_autofree char *name = g_strdup_printf("cframe%d", i); 648 649 object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i], 650 TYPE_XLNX_VERSAL_CFRAME_REG); 651 652 sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]); 653 dev = DEVICE(&s->pmc.cframe[i]); 654 655 if (i < ARRAY_SIZE(cframe_cfg)) { 656 object_property_set_int(OBJECT(dev), "blktype0-frames", 657 cframe_cfg[i].blktype0_frames, 658 &error_abort); 659 object_property_set_int(OBJECT(dev), "blktype1-frames", 660 cframe_cfg[i].blktype1_frames, 661 &error_abort); 662 object_property_set_int(OBJECT(dev), "blktype2-frames", 663 cframe_cfg[i].blktype2_frames, 664 &error_abort); 665 object_property_set_int(OBJECT(dev), "blktype3-frames", 666 cframe_cfg[i].blktype3_frames, 667 &error_abort); 668 object_property_set_int(OBJECT(dev), "blktype4-frames", 669 cframe_cfg[i].blktype4_frames, 670 &error_abort); 671 object_property_set_int(OBJECT(dev), "blktype5-frames", 672 cframe_cfg[i].blktype5_frames, 673 &error_abort); 674 object_property_set_int(OBJECT(dev), "blktype6-frames", 675 cframe_cfg[i].blktype6_frames, 676 &error_abort); 677 } 678 object_property_set_link(OBJECT(dev), "cfu-fdro", 679 OBJECT(&s->pmc.cfu_fdro), &error_fatal); 680 681 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 682 683 memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base, 684 sysbus_mmio_get_region(sbd, 0)); 685 memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base, 686 sysbus_mmio_get_region(sbd, 1)); 687 sysbus_connect_irq(sbd, 0, 688 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 689 3 + i)); 690 } 691 692 /* CFRAME BCAST */ 693 object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast, 694 TYPE_XLNX_VERSAL_CFRAME_BCAST_REG); 695 696 sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast); 697 dev = DEVICE(&s->pmc.cframe_bcast); 698 699 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { 700 g_autofree char *propname = g_strdup_printf("cframe%d", i); 701 object_property_set_link(OBJECT(dev), propname, 702 OBJECT(&s->pmc.cframe[i]), &error_fatal); 703 } 704 705 sysbus_realize(sbd, &error_fatal); 706 707 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG, 708 sysbus_mmio_get_region(sbd, 0)); 709 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI, 710 sysbus_mmio_get_region(sbd, 1)); 711 712 /* CFU APB */ 713 object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb, 714 TYPE_XLNX_VERSAL_CFU_APB); 715 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb); 716 dev = DEVICE(&s->pmc.cfu_apb); 717 718 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { 719 g_autofree char *propname = g_strdup_printf("cframe%d", i); 720 object_property_set_link(OBJECT(dev), propname, 721 OBJECT(&s->pmc.cframe[i]), &error_fatal); 722 } 723 724 sysbus_realize(sbd, &error_fatal); 725 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB, 726 sysbus_mmio_get_region(sbd, 0)); 727 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM, 728 sysbus_mmio_get_region(sbd, 1)); 729 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2, 730 sysbus_mmio_get_region(sbd, 2)); 731 sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]); 732 733 /* CFU SFR */ 734 object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr, 735 TYPE_XLNX_VERSAL_CFU_SFR); 736 737 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr); 738 739 object_property_set_link(OBJECT(&s->pmc.cfu_sfr), 740 "cfu", OBJECT(&s->pmc.cfu_apb), &error_abort); 741 742 sysbus_realize(sbd, &error_fatal); 743 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR, 744 sysbus_mmio_get_region(sbd, 0)); 745 } 746 747 static void versal_create_crl(Versal *s, qemu_irq *pic) 748 { 749 SysBusDevice *sbd; 750 int i; 751 752 object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, 753 TYPE_XLNX_VERSAL_CRL); 754 sbd = SYS_BUS_DEVICE(&s->lpd.crl); 755 756 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 757 g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); 758 759 object_property_set_link(OBJECT(&s->lpd.crl), 760 name, OBJECT(&s->lpd.rpu.cpu[i]), 761 &error_abort); 762 } 763 764 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 765 g_autofree gchar *name = g_strdup_printf("gem[%d]", i); 766 767 object_property_set_link(OBJECT(&s->lpd.crl), 768 name, OBJECT(&s->lpd.iou.gem[i]), 769 &error_abort); 770 } 771 772 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 773 g_autofree gchar *name = g_strdup_printf("adma[%d]", i); 774 775 object_property_set_link(OBJECT(&s->lpd.crl), 776 name, OBJECT(&s->lpd.iou.adma[i]), 777 &error_abort); 778 } 779 780 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 781 g_autofree gchar *name = g_strdup_printf("uart[%d]", i); 782 783 object_property_set_link(OBJECT(&s->lpd.crl), 784 name, OBJECT(&s->lpd.iou.uart[i]), 785 &error_abort); 786 } 787 788 object_property_set_link(OBJECT(&s->lpd.crl), 789 "usb", OBJECT(&s->lpd.iou.usb), 790 &error_abort); 791 792 sysbus_realize(sbd, &error_fatal); 793 memory_region_add_subregion(&s->mr_ps, MM_CRL, 794 sysbus_mmio_get_region(sbd, 0)); 795 sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); 796 } 797 798 /* This takes the board allocated linear DDR memory and creates aliases 799 * for each split DDR range/aperture on the Versal address map. 800 */ 801 static void versal_map_ddr(Versal *s) 802 { 803 uint64_t size = memory_region_size(s->cfg.mr_ddr); 804 /* Describes the various split DDR access regions. */ 805 static const struct { 806 uint64_t base; 807 uint64_t size; 808 } addr_ranges[] = { 809 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 810 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 811 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 812 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 813 }; 814 uint64_t offset = 0; 815 int i; 816 817 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); 818 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 819 char *name; 820 uint64_t mapsize; 821 822 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 823 name = g_strdup_printf("noc-ddr-range%d", i); 824 /* Create the MR alias. */ 825 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), 826 name, s->cfg.mr_ddr, 827 offset, mapsize); 828 829 /* Map it onto the NoC MR. */ 830 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, 831 &s->noc.mr_ddr_ranges[i]); 832 offset += mapsize; 833 size -= mapsize; 834 g_free(name); 835 } 836 } 837 838 static void versal_unimp_area(Versal *s, const char *name, 839 MemoryRegion *mr, 840 hwaddr base, hwaddr size) 841 { 842 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 843 MemoryRegion *mr_dev; 844 845 qdev_prop_set_string(dev, "name", name); 846 qdev_prop_set_uint64(dev, "size", size); 847 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 848 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 849 850 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 851 memory_region_add_subregion(mr, base, mr_dev); 852 } 853 854 static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level) 855 { 856 qemu_log_mask(LOG_UNIMP, 857 "Selecting between enabling SD mode or eMMC mode on " 858 "controller %d is not yet implemented\n", n); 859 } 860 861 static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level) 862 { 863 qemu_log_mask(LOG_UNIMP, 864 "Selecting between enabling the QSPI or OSPI linear address " 865 "region is not yet implemented\n"); 866 } 867 868 static void versal_unimp_irq_parity_imr(void *opaque, int n, int level) 869 { 870 qemu_log_mask(LOG_UNIMP, 871 "PMC SLCR parity interrupt behaviour " 872 "is not yet implemented\n"); 873 } 874 875 static void versal_unimp(Versal *s) 876 { 877 qemu_irq gpio_in; 878 879 versal_unimp_area(s, "psm", &s->mr_ps, 880 MM_PSM_START, MM_PSM_END - MM_PSM_START); 881 versal_unimp_area(s, "crf", &s->mr_ps, 882 MM_FPD_CRF, MM_FPD_CRF_SIZE); 883 versal_unimp_area(s, "apu", &s->mr_ps, 884 MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE); 885 versal_unimp_area(s, "crp", &s->mr_ps, 886 MM_PMC_CRP, MM_PMC_CRP_SIZE); 887 versal_unimp_area(s, "iou-scntr", &s->mr_ps, 888 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); 889 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, 890 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); 891 892 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, 893 "sd-emmc-sel-dummy", 2); 894 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel, 895 "qspi-ospi-mux-sel-dummy", 1); 896 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr, 897 "irq-parity-imr-dummy", 1); 898 899 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0); 900 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, 901 gpio_in); 902 903 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1); 904 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, 905 gpio_in); 906 907 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); 908 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 909 "qspi-ospi-mux-sel", 0, 910 gpio_in); 911 912 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); 913 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 914 SYSBUS_DEVICE_GPIO_IRQ, 0, 915 gpio_in); 916 } 917 918 static void versal_realize(DeviceState *dev, Error **errp) 919 { 920 Versal *s = XLNX_VERSAL(dev); 921 qemu_irq pic[XLNX_VERSAL_NR_IRQS]; 922 923 versal_create_apu_cpus(s); 924 versal_create_apu_gic(s, pic); 925 versal_create_rpu_cpus(s); 926 versal_create_uarts(s, pic); 927 versal_create_canfds(s, pic); 928 versal_create_usbs(s, pic); 929 versal_create_gems(s, pic); 930 versal_create_admas(s, pic); 931 versal_create_sds(s, pic); 932 versal_create_pmc_apb_irq_orgate(s, pic); 933 versal_create_rtc(s, pic); 934 versal_create_trng(s, pic); 935 versal_create_xrams(s, pic); 936 versal_create_bbram(s, pic); 937 versal_create_efuse(s, pic); 938 versal_create_pmc_iou_slcr(s, pic); 939 versal_create_ospi(s, pic); 940 versal_create_crl(s, pic); 941 versal_create_cfu(s, pic); 942 versal_map_ddr(s); 943 versal_unimp(s); 944 945 /* Create the On Chip Memory (OCM). */ 946 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", 947 MM_OCM_SIZE, &error_fatal); 948 949 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); 950 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); 951 memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, 952 &s->lpd.rpu.mr_ps_alias, 0); 953 } 954 955 static void versal_init(Object *obj) 956 { 957 Versal *s = XLNX_VERSAL(obj); 958 959 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); 960 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); 961 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); 962 memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), 963 "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); 964 } 965 966 static Property versal_properties[] = { 967 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, 968 MemoryRegion *), 969 DEFINE_PROP_LINK("canbus0", Versal, lpd.iou.canbus[0], 970 TYPE_CAN_BUS, CanBusState *), 971 DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1], 972 TYPE_CAN_BUS, CanBusState *), 973 DEFINE_PROP_END_OF_LIST() 974 }; 975 976 static void versal_class_init(ObjectClass *klass, void *data) 977 { 978 DeviceClass *dc = DEVICE_CLASS(klass); 979 980 dc->realize = versal_realize; 981 device_class_set_props(dc, versal_properties); 982 /* No VMSD since we haven't got any top-level SoC state to save. */ 983 } 984 985 static const TypeInfo versal_info = { 986 .name = TYPE_XLNX_VERSAL, 987 .parent = TYPE_SYS_BUS_DEVICE, 988 .instance_size = sizeof(Versal), 989 .instance_init = versal_init, 990 .class_init = versal_class_init, 991 }; 992 993 static void versal_register_types(void) 994 { 995 type_register_static(&versal_info); 996 } 997 998 type_init(versal_register_types); 999