1 /* 2 * Xilinx Versal SoC model. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/log.h" 15 #include "qemu/module.h" 16 #include "hw/sysbus.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/kvm.h" 20 #include "hw/arm/boot.h" 21 #include "kvm_arm.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/arm/xlnx-versal.h" 24 25 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") 26 #define GEM_REVISION 0x40070106 27 28 static void versal_create_apu_cpus(Versal *s) 29 { 30 int i; 31 32 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { 33 Object *obj; 34 35 object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], 36 XLNX_VERSAL_ACPU_TYPE); 37 obj = OBJECT(&s->fpd.apu.cpu[i]); 38 object_property_set_int(obj, s->cfg.psci_conduit, 39 "psci-conduit", &error_abort); 40 if (i) { 41 /* Secondary CPUs start in PSCI powered-down state */ 42 object_property_set_bool(obj, true, 43 "start-powered-off", &error_abort); 44 } 45 46 object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu), 47 "core-count", &error_abort); 48 object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory", 49 &error_abort); 50 qdev_realize(DEVICE(obj), NULL, &error_fatal); 51 } 52 } 53 54 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) 55 { 56 static const uint64_t addrs[] = { 57 MM_GIC_APU_DIST_MAIN, 58 MM_GIC_APU_REDIST_0 59 }; 60 SysBusDevice *gicbusdev; 61 DeviceState *gicdev; 62 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); 63 int i; 64 65 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, 66 gicv3_class_name()); 67 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); 68 gicdev = DEVICE(&s->fpd.apu.gic); 69 qdev_prop_set_uint32(gicdev, "revision", 3); 70 qdev_prop_set_uint32(gicdev, "num-cpu", 2); 71 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); 72 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); 73 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2); 74 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 75 76 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); 77 78 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 79 MemoryRegion *mr; 80 81 mr = sysbus_mmio_get_region(gicbusdev, i); 82 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); 83 } 84 85 for (i = 0; i < nr_apu_cpus; i++) { 86 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); 87 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 88 qemu_irq maint_irq; 89 int ti; 90 /* Mapping from the output timer irq lines from the CPU to the 91 * GIC PPI inputs. 92 */ 93 const int timer_irq[] = { 94 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, 95 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, 96 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, 97 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, 98 }; 99 100 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { 101 qdev_connect_gpio_out(cpudev, ti, 102 qdev_get_gpio_in(gicdev, 103 ppibase + timer_irq[ti])); 104 } 105 maint_irq = qdev_get_gpio_in(gicdev, 106 ppibase + VERSAL_GIC_MAINT_IRQ); 107 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 108 0, maint_irq); 109 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 110 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, 111 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 112 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, 113 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 114 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, 115 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 116 } 117 118 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { 119 pic[i] = qdev_get_gpio_in(gicdev, i); 120 } 121 } 122 123 static void versal_create_uarts(Versal *s, qemu_irq *pic) 124 { 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 128 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; 129 static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; 130 char *name = g_strdup_printf("uart%d", i); 131 DeviceState *dev; 132 MemoryRegion *mr; 133 134 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], 135 TYPE_PL011); 136 dev = DEVICE(&s->lpd.iou.uart[i]); 137 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 138 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 139 140 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 141 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 142 143 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 144 g_free(name); 145 } 146 } 147 148 static void versal_create_gems(Versal *s, qemu_irq *pic) 149 { 150 int i; 151 152 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 153 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; 154 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; 155 char *name = g_strdup_printf("gem%d", i); 156 NICInfo *nd = &nd_table[i]; 157 DeviceState *dev; 158 MemoryRegion *mr; 159 160 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], 161 TYPE_CADENCE_GEM); 162 dev = DEVICE(&s->lpd.iou.gem[i]); 163 if (nd->used) { 164 qemu_check_nic_model(nd, "cadence_gem"); 165 qdev_set_nic_properties(dev, nd); 166 } 167 object_property_set_int(OBJECT(dev), 168 2, "num-priority-queues", 169 &error_abort); 170 object_property_set_link(OBJECT(dev), 171 OBJECT(&s->mr_ps), "dma", 172 &error_abort); 173 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 174 175 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 176 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 177 178 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 179 g_free(name); 180 } 181 } 182 183 static void versal_create_admas(Versal *s, qemu_irq *pic) 184 { 185 int i; 186 187 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 188 char *name = g_strdup_printf("adma%d", i); 189 DeviceState *dev; 190 MemoryRegion *mr; 191 192 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 193 TYPE_XLNX_ZDMA); 194 dev = DEVICE(&s->lpd.iou.adma[i]); 195 object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort); 196 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 197 198 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 199 memory_region_add_subregion(&s->mr_ps, 200 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); 201 202 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); 203 g_free(name); 204 } 205 } 206 207 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ 208 static void versal_create_sds(Versal *s, qemu_irq *pic) 209 { 210 int i; 211 212 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { 213 DeviceState *dev; 214 MemoryRegion *mr; 215 216 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], 217 TYPE_SYSBUS_SDHCI); 218 dev = DEVICE(&s->pmc.iou.sd[i]); 219 220 object_property_set_uint(OBJECT(dev), 221 3, "sd-spec-version", &error_fatal); 222 object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg", 223 &error_fatal); 224 object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal); 225 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 226 227 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 228 memory_region_add_subregion(&s->mr_ps, 229 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); 230 231 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 232 pic[VERSAL_SD0_IRQ_0 + i * 2]); 233 } 234 } 235 236 static void versal_create_rtc(Versal *s, qemu_irq *pic) 237 { 238 SysBusDevice *sbd; 239 MemoryRegion *mr; 240 241 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, 242 TYPE_XLNX_ZYNQMP_RTC); 243 sbd = SYS_BUS_DEVICE(&s->pmc.rtc); 244 sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal); 245 246 mr = sysbus_mmio_get_region(sbd, 0); 247 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); 248 249 /* 250 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model 251 * supports them. 252 */ 253 sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]); 254 } 255 256 /* This takes the board allocated linear DDR memory and creates aliases 257 * for each split DDR range/aperture on the Versal address map. 258 */ 259 static void versal_map_ddr(Versal *s) 260 { 261 uint64_t size = memory_region_size(s->cfg.mr_ddr); 262 /* Describes the various split DDR access regions. */ 263 static const struct { 264 uint64_t base; 265 uint64_t size; 266 } addr_ranges[] = { 267 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 268 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 269 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 270 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 271 }; 272 uint64_t offset = 0; 273 int i; 274 275 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); 276 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 277 char *name; 278 uint64_t mapsize; 279 280 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 281 name = g_strdup_printf("noc-ddr-range%d", i); 282 /* Create the MR alias. */ 283 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), 284 name, s->cfg.mr_ddr, 285 offset, mapsize); 286 287 /* Map it onto the NoC MR. */ 288 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, 289 &s->noc.mr_ddr_ranges[i]); 290 offset += mapsize; 291 size -= mapsize; 292 g_free(name); 293 } 294 } 295 296 static void versal_unimp_area(Versal *s, const char *name, 297 MemoryRegion *mr, 298 hwaddr base, hwaddr size) 299 { 300 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 301 MemoryRegion *mr_dev; 302 303 qdev_prop_set_string(dev, "name", name); 304 qdev_prop_set_uint64(dev, "size", size); 305 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 306 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 307 308 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 309 memory_region_add_subregion(mr, base, mr_dev); 310 } 311 312 static void versal_unimp(Versal *s) 313 { 314 versal_unimp_area(s, "psm", &s->mr_ps, 315 MM_PSM_START, MM_PSM_END - MM_PSM_START); 316 versal_unimp_area(s, "crl", &s->mr_ps, 317 MM_CRL, MM_CRL_SIZE); 318 versal_unimp_area(s, "crf", &s->mr_ps, 319 MM_FPD_CRF, MM_FPD_CRF_SIZE); 320 versal_unimp_area(s, "crp", &s->mr_ps, 321 MM_PMC_CRP, MM_PMC_CRP_SIZE); 322 versal_unimp_area(s, "iou-scntr", &s->mr_ps, 323 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); 324 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, 325 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); 326 } 327 328 static void versal_realize(DeviceState *dev, Error **errp) 329 { 330 Versal *s = XLNX_VERSAL(dev); 331 qemu_irq pic[XLNX_VERSAL_NR_IRQS]; 332 333 versal_create_apu_cpus(s); 334 versal_create_apu_gic(s, pic); 335 versal_create_uarts(s, pic); 336 versal_create_gems(s, pic); 337 versal_create_admas(s, pic); 338 versal_create_sds(s, pic); 339 versal_create_rtc(s, pic); 340 versal_map_ddr(s); 341 versal_unimp(s); 342 343 /* Create the On Chip Memory (OCM). */ 344 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", 345 MM_OCM_SIZE, &error_fatal); 346 347 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); 348 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); 349 } 350 351 static void versal_init(Object *obj) 352 { 353 Versal *s = XLNX_VERSAL(obj); 354 355 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); 356 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); 357 } 358 359 static Property versal_properties[] = { 360 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, 361 MemoryRegion *), 362 DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0), 363 DEFINE_PROP_END_OF_LIST() 364 }; 365 366 static void versal_class_init(ObjectClass *klass, void *data) 367 { 368 DeviceClass *dc = DEVICE_CLASS(klass); 369 370 dc->realize = versal_realize; 371 device_class_set_props(dc, versal_properties); 372 /* No VMSD since we haven't got any top-level SoC state to save. */ 373 } 374 375 static const TypeInfo versal_info = { 376 .name = TYPE_XLNX_VERSAL, 377 .parent = TYPE_SYS_BUS_DEVICE, 378 .instance_size = sizeof(Versal), 379 .instance_init = versal_init, 380 .class_init = versal_class_init, 381 }; 382 383 static void versal_register_types(void) 384 { 385 type_register_static(&versal_info); 386 } 387 388 type_init(versal_register_types); 389