1 /* 2 * Xilinx Versal SoC model. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/units.h" 14 #include "qapi/error.h" 15 #include "qemu/module.h" 16 #include "hw/sysbus.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/kvm.h" 20 #include "hw/arm/boot.h" 21 #include "kvm_arm.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/arm/xlnx-versal.h" 24 #include "qemu/log.h" 25 26 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") 27 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") 28 #define GEM_REVISION 0x40070106 29 30 #define VERSAL_NUM_PMC_APB_IRQS 3 31 #define NUM_OSPI_IRQ_LINES 3 32 33 static void versal_create_apu_cpus(Versal *s) 34 { 35 int i; 36 37 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, 38 TYPE_CPU_CLUSTER); 39 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); 40 41 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { 42 Object *obj; 43 44 object_initialize_child(OBJECT(&s->fpd.apu.cluster), 45 "apu-cpu[*]", &s->fpd.apu.cpu[i], 46 XLNX_VERSAL_ACPU_TYPE); 47 obj = OBJECT(&s->fpd.apu.cpu[i]); 48 if (i) { 49 /* Secondary CPUs start in powered-down state */ 50 object_property_set_bool(obj, "start-powered-off", true, 51 &error_abort); 52 } 53 54 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), 55 &error_abort); 56 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr), 57 &error_abort); 58 qdev_realize(DEVICE(obj), NULL, &error_fatal); 59 } 60 61 qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); 62 } 63 64 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) 65 { 66 static const uint64_t addrs[] = { 67 MM_GIC_APU_DIST_MAIN, 68 MM_GIC_APU_REDIST_0 69 }; 70 SysBusDevice *gicbusdev; 71 DeviceState *gicdev; 72 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); 73 int i; 74 75 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, 76 gicv3_class_name()); 77 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); 78 gicdev = DEVICE(&s->fpd.apu.gic); 79 qdev_prop_set_uint32(gicdev, "revision", 3); 80 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus); 81 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); 82 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); 83 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", nr_apu_cpus); 84 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 85 86 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); 87 88 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 89 MemoryRegion *mr; 90 91 mr = sysbus_mmio_get_region(gicbusdev, i); 92 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); 93 } 94 95 for (i = 0; i < nr_apu_cpus; i++) { 96 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); 97 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 98 qemu_irq maint_irq; 99 int ti; 100 /* Mapping from the output timer irq lines from the CPU to the 101 * GIC PPI inputs. 102 */ 103 const int timer_irq[] = { 104 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, 105 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, 106 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, 107 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, 108 }; 109 110 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { 111 qdev_connect_gpio_out(cpudev, ti, 112 qdev_get_gpio_in(gicdev, 113 ppibase + timer_irq[ti])); 114 } 115 maint_irq = qdev_get_gpio_in(gicdev, 116 ppibase + VERSAL_GIC_MAINT_IRQ); 117 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 118 0, maint_irq); 119 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 120 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, 121 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 122 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, 123 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 124 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, 125 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 126 } 127 128 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { 129 pic[i] = qdev_get_gpio_in(gicdev, i); 130 } 131 } 132 133 static void versal_create_rpu_cpus(Versal *s) 134 { 135 int i; 136 137 object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, 138 TYPE_CPU_CLUSTER); 139 qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); 140 141 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 142 Object *obj; 143 144 object_initialize_child(OBJECT(&s->lpd.rpu.cluster), 145 "rpu-cpu[*]", &s->lpd.rpu.cpu[i], 146 XLNX_VERSAL_RCPU_TYPE); 147 obj = OBJECT(&s->lpd.rpu.cpu[i]); 148 object_property_set_bool(obj, "start-powered-off", true, 149 &error_abort); 150 151 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); 152 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), 153 &error_abort); 154 object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), 155 &error_abort); 156 qdev_realize(DEVICE(obj), NULL, &error_fatal); 157 } 158 159 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); 160 } 161 162 static void versal_create_uarts(Versal *s, qemu_irq *pic) 163 { 164 int i; 165 166 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 167 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; 168 static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; 169 char *name = g_strdup_printf("uart%d", i); 170 DeviceState *dev; 171 MemoryRegion *mr; 172 173 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], 174 TYPE_PL011); 175 dev = DEVICE(&s->lpd.iou.uart[i]); 176 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 177 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 178 179 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 180 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 181 182 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 183 g_free(name); 184 } 185 } 186 187 static void versal_create_canfds(Versal *s, qemu_irq *pic) 188 { 189 int i; 190 uint32_t irqs[] = { VERSAL_CANFD0_IRQ_0, VERSAL_CANFD1_IRQ_0}; 191 uint64_t addrs[] = { MM_CANFD0, MM_CANFD1 }; 192 193 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.canfd); i++) { 194 char *name = g_strdup_printf("canfd%d", i); 195 SysBusDevice *sbd; 196 MemoryRegion *mr; 197 198 object_initialize_child(OBJECT(s), name, &s->lpd.iou.canfd[i], 199 TYPE_XILINX_CANFD); 200 sbd = SYS_BUS_DEVICE(&s->lpd.iou.canfd[i]); 201 202 object_property_set_int(OBJECT(&s->lpd.iou.canfd[i]), "ext_clk_freq", 203 XLNX_VERSAL_CANFD_REF_CLK , &error_abort); 204 205 object_property_set_link(OBJECT(&s->lpd.iou.canfd[i]), "canfdbus", 206 OBJECT(s->lpd.iou.canbus[i]), 207 &error_abort); 208 209 sysbus_realize(sbd, &error_fatal); 210 211 mr = sysbus_mmio_get_region(sbd, 0); 212 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 213 214 sysbus_connect_irq(sbd, 0, pic[irqs[i]]); 215 g_free(name); 216 } 217 } 218 219 static void versal_create_usbs(Versal *s, qemu_irq *pic) 220 { 221 DeviceState *dev; 222 MemoryRegion *mr; 223 224 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, 225 TYPE_XILINX_VERSAL_USB2); 226 dev = DEVICE(&s->lpd.iou.usb); 227 228 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 229 &error_abort); 230 qdev_prop_set_uint32(dev, "intrs", 1); 231 qdev_prop_set_uint32(dev, "slots", 2); 232 233 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 234 235 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 236 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); 237 238 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); 239 240 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 241 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); 242 } 243 244 static void versal_create_gems(Versal *s, qemu_irq *pic) 245 { 246 int i; 247 248 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 249 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; 250 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; 251 char *name = g_strdup_printf("gem%d", i); 252 NICInfo *nd = &nd_table[i]; 253 DeviceState *dev; 254 MemoryRegion *mr; 255 256 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], 257 TYPE_CADENCE_GEM); 258 dev = DEVICE(&s->lpd.iou.gem[i]); 259 /* FIXME use qdev NIC properties instead of nd_table[] */ 260 if (nd->used) { 261 qemu_check_nic_model(nd, "cadence_gem"); 262 qdev_set_nic_properties(dev, nd); 263 } 264 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); 265 object_property_set_int(OBJECT(dev), "num-priority-queues", 2, 266 &error_abort); 267 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 268 &error_abort); 269 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 270 271 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 272 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 273 274 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 275 g_free(name); 276 } 277 } 278 279 static void versal_create_admas(Versal *s, qemu_irq *pic) 280 { 281 int i; 282 283 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 284 char *name = g_strdup_printf("adma%d", i); 285 DeviceState *dev; 286 MemoryRegion *mr; 287 288 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 289 TYPE_XLNX_ZDMA); 290 dev = DEVICE(&s->lpd.iou.adma[i]); 291 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort); 292 object_property_set_link(OBJECT(dev), "dma", 293 OBJECT(get_system_memory()), &error_fatal); 294 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 295 296 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 297 memory_region_add_subregion(&s->mr_ps, 298 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); 299 300 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); 301 g_free(name); 302 } 303 } 304 305 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ 306 static void versal_create_sds(Versal *s, qemu_irq *pic) 307 { 308 int i; 309 310 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { 311 DeviceState *dev; 312 MemoryRegion *mr; 313 314 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], 315 TYPE_SYSBUS_SDHCI); 316 dev = DEVICE(&s->pmc.iou.sd[i]); 317 318 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3, 319 &error_fatal); 320 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES, 321 &error_fatal); 322 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal); 323 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 324 325 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 326 memory_region_add_subregion(&s->mr_ps, 327 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); 328 329 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 330 pic[VERSAL_SD0_IRQ_0 + i * 2]); 331 } 332 } 333 334 static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) 335 { 336 DeviceState *orgate; 337 338 /* 339 * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following 340 * models: 341 * - RTC 342 * - BBRAM 343 * - PMC SLCR 344 */ 345 object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", 346 &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); 347 orgate = DEVICE(&s->pmc.apb_irq_orgate); 348 object_property_set_int(OBJECT(orgate), 349 "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal); 350 qdev_realize(orgate, NULL, &error_fatal); 351 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); 352 } 353 354 static void versal_create_rtc(Versal *s, qemu_irq *pic) 355 { 356 SysBusDevice *sbd; 357 MemoryRegion *mr; 358 359 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, 360 TYPE_XLNX_ZYNQMP_RTC); 361 sbd = SYS_BUS_DEVICE(&s->pmc.rtc); 362 sysbus_realize(sbd, &error_fatal); 363 364 mr = sysbus_mmio_get_region(sbd, 0); 365 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); 366 367 /* 368 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model 369 * supports them. 370 */ 371 sysbus_connect_irq(sbd, 1, 372 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); 373 } 374 375 static void versal_create_xrams(Versal *s, qemu_irq *pic) 376 { 377 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); 378 DeviceState *orgate; 379 int i; 380 381 /* XRAM IRQs get ORed into a single line. */ 382 object_initialize_child(OBJECT(s), "xram-irq-orgate", 383 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); 384 orgate = DEVICE(&s->lpd.xram.irq_orgate); 385 object_property_set_int(OBJECT(orgate), 386 "num-lines", nr_xrams, &error_fatal); 387 qdev_realize(orgate, NULL, &error_fatal); 388 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); 389 390 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { 391 SysBusDevice *sbd; 392 MemoryRegion *mr; 393 394 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], 395 TYPE_XLNX_XRAM_CTRL); 396 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); 397 sysbus_realize(sbd, &error_fatal); 398 399 mr = sysbus_mmio_get_region(sbd, 0); 400 memory_region_add_subregion(&s->mr_ps, 401 MM_XRAMC + i * MM_XRAMC_SIZE, mr); 402 mr = sysbus_mmio_get_region(sbd, 1); 403 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); 404 405 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); 406 } 407 } 408 409 static void versal_create_bbram(Versal *s, qemu_irq *pic) 410 { 411 SysBusDevice *sbd; 412 413 object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, 414 sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, 415 &error_fatal, 416 "crc-zpads", "0", 417 NULL); 418 sbd = SYS_BUS_DEVICE(&s->pmc.bbram); 419 420 sysbus_realize(sbd, &error_fatal); 421 memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, 422 sysbus_mmio_get_region(sbd, 0)); 423 sysbus_connect_irq(sbd, 0, 424 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1)); 425 } 426 427 static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) 428 { 429 SysBusDevice *part = SYS_BUS_DEVICE(dev); 430 431 object_property_set_link(OBJECT(part), "efuse", 432 OBJECT(&s->pmc.efuse), &error_abort); 433 434 sysbus_realize(part, &error_abort); 435 memory_region_add_subregion(&s->mr_ps, base, 436 sysbus_mmio_get_region(part, 0)); 437 } 438 439 static void versal_create_efuse(Versal *s, qemu_irq *pic) 440 { 441 Object *bits = OBJECT(&s->pmc.efuse); 442 Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); 443 Object *cache = OBJECT(&s->pmc.efuse_cache); 444 445 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, 446 TYPE_XLNX_VERSAL_EFUSE_CTRL); 447 448 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, 449 TYPE_XLNX_VERSAL_EFUSE_CACHE); 450 451 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 452 sizeof(s->pmc.efuse), 453 TYPE_XLNX_EFUSE, &error_abort, 454 "efuse-nr", "3", 455 "efuse-size", "8192", 456 NULL); 457 458 qdev_realize(DEVICE(bits), NULL, &error_abort); 459 versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); 460 versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); 461 462 sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); 463 } 464 465 static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) 466 { 467 SysBusDevice *sbd; 468 469 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, 470 TYPE_XILINX_VERSAL_PMC_IOU_SLCR); 471 472 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); 473 sysbus_realize(sbd, &error_fatal); 474 475 memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, 476 sysbus_mmio_get_region(sbd, 0)); 477 478 sysbus_connect_irq(sbd, 0, 479 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); 480 } 481 482 static void versal_create_ospi(Versal *s, qemu_irq *pic) 483 { 484 SysBusDevice *sbd; 485 MemoryRegion *mr_dac; 486 qemu_irq ospi_mux_sel; 487 DeviceState *orgate; 488 489 memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), 490 "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); 491 492 object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi, 493 TYPE_XILINX_VERSAL_OSPI); 494 495 mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1); 496 memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); 497 498 /* Create the OSPI destination DMA */ 499 object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", 500 &s->pmc.iou.ospi.dma_dst, 501 TYPE_XLNX_CSU_DMA); 502 503 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), 504 "dma", OBJECT(get_system_memory()), 505 &error_abort); 506 507 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); 508 sysbus_realize(sbd, &error_fatal); 509 510 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, 511 sysbus_mmio_get_region(sbd, 0)); 512 513 /* Create the OSPI source DMA */ 514 object_initialize_child(OBJECT(s), "versal-ospi-dma-src", 515 &s->pmc.iou.ospi.dma_src, 516 TYPE_XLNX_CSU_DMA); 517 518 object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", 519 false, &error_abort); 520 521 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 522 "dma", OBJECT(mr_dac), &error_abort); 523 524 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 525 "stream-connected-dma", 526 OBJECT(&s->pmc.iou.ospi.dma_dst), 527 &error_abort); 528 529 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); 530 sysbus_realize(sbd, &error_fatal); 531 532 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, 533 sysbus_mmio_get_region(sbd, 0)); 534 535 /* Realize the OSPI */ 536 object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", 537 OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort); 538 539 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); 540 sysbus_realize(sbd, &error_fatal); 541 542 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, 543 sysbus_mmio_get_region(sbd, 0)); 544 545 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, 546 &s->pmc.iou.ospi.linear_mr); 547 548 /* ospi_mux_sel */ 549 ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi), 550 "ospi-mux-sel", 0); 551 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, 552 ospi_mux_sel); 553 554 /* OSPI irq */ 555 object_initialize_child(OBJECT(s), "ospi-irq-orgate", 556 &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ); 557 object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate), 558 "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); 559 560 orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate); 561 qdev_realize(orgate, NULL, &error_fatal); 562 563 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, 564 qdev_get_gpio_in(orgate, 0)); 565 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, 566 qdev_get_gpio_in(orgate, 1)); 567 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, 568 qdev_get_gpio_in(orgate, 2)); 569 570 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); 571 } 572 573 static void versal_create_crl(Versal *s, qemu_irq *pic) 574 { 575 SysBusDevice *sbd; 576 int i; 577 578 object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, 579 TYPE_XLNX_VERSAL_CRL); 580 sbd = SYS_BUS_DEVICE(&s->lpd.crl); 581 582 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 583 g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); 584 585 object_property_set_link(OBJECT(&s->lpd.crl), 586 name, OBJECT(&s->lpd.rpu.cpu[i]), 587 &error_abort); 588 } 589 590 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 591 g_autofree gchar *name = g_strdup_printf("gem[%d]", i); 592 593 object_property_set_link(OBJECT(&s->lpd.crl), 594 name, OBJECT(&s->lpd.iou.gem[i]), 595 &error_abort); 596 } 597 598 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 599 g_autofree gchar *name = g_strdup_printf("adma[%d]", i); 600 601 object_property_set_link(OBJECT(&s->lpd.crl), 602 name, OBJECT(&s->lpd.iou.adma[i]), 603 &error_abort); 604 } 605 606 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 607 g_autofree gchar *name = g_strdup_printf("uart[%d]", i); 608 609 object_property_set_link(OBJECT(&s->lpd.crl), 610 name, OBJECT(&s->lpd.iou.uart[i]), 611 &error_abort); 612 } 613 614 object_property_set_link(OBJECT(&s->lpd.crl), 615 "usb", OBJECT(&s->lpd.iou.usb), 616 &error_abort); 617 618 sysbus_realize(sbd, &error_fatal); 619 memory_region_add_subregion(&s->mr_ps, MM_CRL, 620 sysbus_mmio_get_region(sbd, 0)); 621 sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); 622 } 623 624 /* This takes the board allocated linear DDR memory and creates aliases 625 * for each split DDR range/aperture on the Versal address map. 626 */ 627 static void versal_map_ddr(Versal *s) 628 { 629 uint64_t size = memory_region_size(s->cfg.mr_ddr); 630 /* Describes the various split DDR access regions. */ 631 static const struct { 632 uint64_t base; 633 uint64_t size; 634 } addr_ranges[] = { 635 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 636 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 637 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 638 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 639 }; 640 uint64_t offset = 0; 641 int i; 642 643 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); 644 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 645 char *name; 646 uint64_t mapsize; 647 648 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 649 name = g_strdup_printf("noc-ddr-range%d", i); 650 /* Create the MR alias. */ 651 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), 652 name, s->cfg.mr_ddr, 653 offset, mapsize); 654 655 /* Map it onto the NoC MR. */ 656 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, 657 &s->noc.mr_ddr_ranges[i]); 658 offset += mapsize; 659 size -= mapsize; 660 g_free(name); 661 } 662 } 663 664 static void versal_unimp_area(Versal *s, const char *name, 665 MemoryRegion *mr, 666 hwaddr base, hwaddr size) 667 { 668 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 669 MemoryRegion *mr_dev; 670 671 qdev_prop_set_string(dev, "name", name); 672 qdev_prop_set_uint64(dev, "size", size); 673 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 674 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 675 676 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 677 memory_region_add_subregion(mr, base, mr_dev); 678 } 679 680 static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level) 681 { 682 qemu_log_mask(LOG_UNIMP, 683 "Selecting between enabling SD mode or eMMC mode on " 684 "controller %d is not yet implemented\n", n); 685 } 686 687 static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level) 688 { 689 qemu_log_mask(LOG_UNIMP, 690 "Selecting between enabling the QSPI or OSPI linear address " 691 "region is not yet implemented\n"); 692 } 693 694 static void versal_unimp_irq_parity_imr(void *opaque, int n, int level) 695 { 696 qemu_log_mask(LOG_UNIMP, 697 "PMC SLCR parity interrupt behaviour " 698 "is not yet implemented\n"); 699 } 700 701 static void versal_unimp(Versal *s) 702 { 703 qemu_irq gpio_in; 704 705 versal_unimp_area(s, "psm", &s->mr_ps, 706 MM_PSM_START, MM_PSM_END - MM_PSM_START); 707 versal_unimp_area(s, "crf", &s->mr_ps, 708 MM_FPD_CRF, MM_FPD_CRF_SIZE); 709 versal_unimp_area(s, "apu", &s->mr_ps, 710 MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE); 711 versal_unimp_area(s, "crp", &s->mr_ps, 712 MM_PMC_CRP, MM_PMC_CRP_SIZE); 713 versal_unimp_area(s, "iou-scntr", &s->mr_ps, 714 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); 715 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, 716 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); 717 718 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, 719 "sd-emmc-sel-dummy", 2); 720 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel, 721 "qspi-ospi-mux-sel-dummy", 1); 722 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr, 723 "irq-parity-imr-dummy", 1); 724 725 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0); 726 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, 727 gpio_in); 728 729 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1); 730 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, 731 gpio_in); 732 733 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); 734 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 735 "qspi-ospi-mux-sel", 0, 736 gpio_in); 737 738 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); 739 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 740 SYSBUS_DEVICE_GPIO_IRQ, 0, 741 gpio_in); 742 } 743 744 static void versal_realize(DeviceState *dev, Error **errp) 745 { 746 Versal *s = XLNX_VERSAL(dev); 747 qemu_irq pic[XLNX_VERSAL_NR_IRQS]; 748 749 versal_create_apu_cpus(s); 750 versal_create_apu_gic(s, pic); 751 versal_create_rpu_cpus(s); 752 versal_create_uarts(s, pic); 753 versal_create_canfds(s, pic); 754 versal_create_usbs(s, pic); 755 versal_create_gems(s, pic); 756 versal_create_admas(s, pic); 757 versal_create_sds(s, pic); 758 versal_create_pmc_apb_irq_orgate(s, pic); 759 versal_create_rtc(s, pic); 760 versal_create_xrams(s, pic); 761 versal_create_bbram(s, pic); 762 versal_create_efuse(s, pic); 763 versal_create_pmc_iou_slcr(s, pic); 764 versal_create_ospi(s, pic); 765 versal_create_crl(s, pic); 766 versal_map_ddr(s); 767 versal_unimp(s); 768 769 /* Create the On Chip Memory (OCM). */ 770 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", 771 MM_OCM_SIZE, &error_fatal); 772 773 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); 774 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); 775 memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, 776 &s->lpd.rpu.mr_ps_alias, 0); 777 } 778 779 static void versal_init(Object *obj) 780 { 781 Versal *s = XLNX_VERSAL(obj); 782 783 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); 784 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); 785 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); 786 memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), 787 "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); 788 } 789 790 static Property versal_properties[] = { 791 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, 792 MemoryRegion *), 793 DEFINE_PROP_LINK("canbus0", Versal, lpd.iou.canbus[0], 794 TYPE_CAN_BUS, CanBusState *), 795 DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1], 796 TYPE_CAN_BUS, CanBusState *), 797 DEFINE_PROP_END_OF_LIST() 798 }; 799 800 static void versal_class_init(ObjectClass *klass, void *data) 801 { 802 DeviceClass *dc = DEVICE_CLASS(klass); 803 804 dc->realize = versal_realize; 805 device_class_set_props(dc, versal_properties); 806 /* No VMSD since we haven't got any top-level SoC state to save. */ 807 } 808 809 static const TypeInfo versal_info = { 810 .name = TYPE_XLNX_VERSAL, 811 .parent = TYPE_SYS_BUS_DEVICE, 812 .instance_size = sizeof(Versal), 813 .instance_init = versal_init, 814 .class_init = versal_class_init, 815 }; 816 817 static void versal_register_types(void) 818 { 819 type_register_static(&versal_info); 820 } 821 822 type_init(versal_register_types); 823