1 /* 2 * Xilinx Versal SoC model. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/units.h" 14 #include "qapi/error.h" 15 #include "qapi/qmp/qlist.h" 16 #include "qemu/module.h" 17 #include "hw/sysbus.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 #include "sysemu/kvm.h" 21 #include "hw/arm/boot.h" 22 #include "kvm_arm.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/arm/xlnx-versal.h" 25 #include "qemu/log.h" 26 #include "target/arm/cpu-qom.h" 27 #include "target/arm/gtimer.h" 28 29 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") 30 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") 31 #define GEM_REVISION 0x40070106 32 33 #define VERSAL_NUM_PMC_APB_IRQS 18 34 #define NUM_OSPI_IRQ_LINES 3 35 36 static void versal_create_apu_cpus(Versal *s) 37 { 38 int i; 39 40 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, 41 TYPE_CPU_CLUSTER); 42 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); 43 44 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { 45 Object *obj; 46 47 object_initialize_child(OBJECT(&s->fpd.apu.cluster), 48 "apu-cpu[*]", &s->fpd.apu.cpu[i], 49 XLNX_VERSAL_ACPU_TYPE); 50 obj = OBJECT(&s->fpd.apu.cpu[i]); 51 if (i) { 52 /* Secondary CPUs start in powered-down state */ 53 object_property_set_bool(obj, "start-powered-off", true, 54 &error_abort); 55 } 56 57 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), 58 &error_abort); 59 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr), 60 &error_abort); 61 qdev_realize(DEVICE(obj), NULL, &error_fatal); 62 } 63 64 qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); 65 } 66 67 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) 68 { 69 static const uint64_t addrs[] = { 70 MM_GIC_APU_DIST_MAIN, 71 MM_GIC_APU_REDIST_0 72 }; 73 SysBusDevice *gicbusdev; 74 DeviceState *gicdev; 75 QList *redist_region_count; 76 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); 77 int i; 78 79 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, 80 gicv3_class_name()); 81 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); 82 gicdev = DEVICE(&s->fpd.apu.gic); 83 qdev_prop_set_uint32(gicdev, "revision", 3); 84 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus); 85 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); 86 87 redist_region_count = qlist_new(); 88 qlist_append_int(redist_region_count, nr_apu_cpus); 89 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 90 91 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 92 93 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); 94 95 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 96 MemoryRegion *mr; 97 98 mr = sysbus_mmio_get_region(gicbusdev, i); 99 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); 100 } 101 102 for (i = 0; i < nr_apu_cpus; i++) { 103 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); 104 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 105 qemu_irq maint_irq; 106 int ti; 107 /* Mapping from the output timer irq lines from the CPU to the 108 * GIC PPI inputs. 109 */ 110 const int timer_irq[] = { 111 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, 112 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, 113 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, 114 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, 115 }; 116 117 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { 118 qdev_connect_gpio_out(cpudev, ti, 119 qdev_get_gpio_in(gicdev, 120 ppibase + timer_irq[ti])); 121 } 122 maint_irq = qdev_get_gpio_in(gicdev, 123 ppibase + VERSAL_GIC_MAINT_IRQ); 124 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 125 0, maint_irq); 126 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 127 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, 128 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 129 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, 130 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 131 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, 132 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 133 } 134 135 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { 136 pic[i] = qdev_get_gpio_in(gicdev, i); 137 } 138 } 139 140 static void versal_create_rpu_cpus(Versal *s) 141 { 142 int i; 143 144 object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, 145 TYPE_CPU_CLUSTER); 146 qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); 147 148 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 149 Object *obj; 150 151 object_initialize_child(OBJECT(&s->lpd.rpu.cluster), 152 "rpu-cpu[*]", &s->lpd.rpu.cpu[i], 153 XLNX_VERSAL_RCPU_TYPE); 154 obj = OBJECT(&s->lpd.rpu.cpu[i]); 155 object_property_set_bool(obj, "start-powered-off", true, 156 &error_abort); 157 158 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); 159 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), 160 &error_abort); 161 object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), 162 &error_abort); 163 qdev_realize(DEVICE(obj), NULL, &error_fatal); 164 } 165 166 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); 167 } 168 169 static void versal_create_uarts(Versal *s, qemu_irq *pic) 170 { 171 int i; 172 173 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 174 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; 175 static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; 176 char *name = g_strdup_printf("uart%d", i); 177 DeviceState *dev; 178 MemoryRegion *mr; 179 180 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], 181 TYPE_PL011); 182 dev = DEVICE(&s->lpd.iou.uart[i]); 183 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 184 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 185 186 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 187 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 188 189 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 190 g_free(name); 191 } 192 } 193 194 static void versal_create_canfds(Versal *s, qemu_irq *pic) 195 { 196 int i; 197 uint32_t irqs[] = { VERSAL_CANFD0_IRQ_0, VERSAL_CANFD1_IRQ_0}; 198 uint64_t addrs[] = { MM_CANFD0, MM_CANFD1 }; 199 200 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.canfd); i++) { 201 char *name = g_strdup_printf("canfd%d", i); 202 SysBusDevice *sbd; 203 MemoryRegion *mr; 204 205 object_initialize_child(OBJECT(s), name, &s->lpd.iou.canfd[i], 206 TYPE_XILINX_CANFD); 207 sbd = SYS_BUS_DEVICE(&s->lpd.iou.canfd[i]); 208 209 object_property_set_int(OBJECT(&s->lpd.iou.canfd[i]), "ext_clk_freq", 210 XLNX_VERSAL_CANFD_REF_CLK , &error_abort); 211 212 object_property_set_link(OBJECT(&s->lpd.iou.canfd[i]), "canfdbus", 213 OBJECT(s->lpd.iou.canbus[i]), 214 &error_abort); 215 216 sysbus_realize(sbd, &error_fatal); 217 218 mr = sysbus_mmio_get_region(sbd, 0); 219 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 220 221 sysbus_connect_irq(sbd, 0, pic[irqs[i]]); 222 g_free(name); 223 } 224 } 225 226 static void versal_create_usbs(Versal *s, qemu_irq *pic) 227 { 228 DeviceState *dev; 229 MemoryRegion *mr; 230 231 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, 232 TYPE_XILINX_VERSAL_USB2); 233 dev = DEVICE(&s->lpd.iou.usb); 234 235 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 236 &error_abort); 237 qdev_prop_set_uint32(dev, "intrs", 1); 238 qdev_prop_set_uint32(dev, "slots", 2); 239 240 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 241 242 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 243 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); 244 245 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); 246 247 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 248 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); 249 } 250 251 static void versal_create_gems(Versal *s, qemu_irq *pic) 252 { 253 int i; 254 255 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 256 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; 257 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; 258 char *name = g_strdup_printf("gem%d", i); 259 DeviceState *dev; 260 MemoryRegion *mr; 261 262 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], 263 TYPE_CADENCE_GEM); 264 dev = DEVICE(&s->lpd.iou.gem[i]); 265 qemu_configure_nic_device(dev, true, NULL); 266 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); 267 object_property_set_int(OBJECT(dev), "num-priority-queues", 2, 268 &error_abort); 269 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 270 &error_abort); 271 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 272 273 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 274 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 275 276 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 277 g_free(name); 278 } 279 } 280 281 static void versal_create_admas(Versal *s, qemu_irq *pic) 282 { 283 int i; 284 285 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 286 char *name = g_strdup_printf("adma%d", i); 287 DeviceState *dev; 288 MemoryRegion *mr; 289 290 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 291 TYPE_XLNX_ZDMA); 292 dev = DEVICE(&s->lpd.iou.adma[i]); 293 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort); 294 object_property_set_link(OBJECT(dev), "dma", 295 OBJECT(get_system_memory()), &error_fatal); 296 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 297 298 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 299 memory_region_add_subregion(&s->mr_ps, 300 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); 301 302 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); 303 g_free(name); 304 } 305 } 306 307 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ 308 static void versal_create_sds(Versal *s, qemu_irq *pic) 309 { 310 int i; 311 312 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { 313 DeviceState *dev; 314 MemoryRegion *mr; 315 316 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], 317 TYPE_SYSBUS_SDHCI); 318 dev = DEVICE(&s->pmc.iou.sd[i]); 319 320 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3, 321 &error_fatal); 322 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES, 323 &error_fatal); 324 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal); 325 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 326 327 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 328 memory_region_add_subregion(&s->mr_ps, 329 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); 330 331 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 332 pic[VERSAL_SD0_IRQ_0 + i * 2]); 333 } 334 } 335 336 static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) 337 { 338 DeviceState *orgate; 339 340 /* 341 * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following 342 * models: 343 * - RTC 344 * - BBRAM 345 * - PMC SLCR 346 * - CFRAME regs (input 3 - 17 to the orgate) 347 */ 348 object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", 349 &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); 350 orgate = DEVICE(&s->pmc.apb_irq_orgate); 351 object_property_set_int(OBJECT(orgate), 352 "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal); 353 qdev_realize(orgate, NULL, &error_fatal); 354 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); 355 } 356 357 static void versal_create_rtc(Versal *s, qemu_irq *pic) 358 { 359 SysBusDevice *sbd; 360 MemoryRegion *mr; 361 362 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, 363 TYPE_XLNX_ZYNQMP_RTC); 364 sbd = SYS_BUS_DEVICE(&s->pmc.rtc); 365 sysbus_realize(sbd, &error_fatal); 366 367 mr = sysbus_mmio_get_region(sbd, 0); 368 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); 369 370 /* 371 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model 372 * supports them. 373 */ 374 sysbus_connect_irq(sbd, 1, 375 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); 376 } 377 378 static void versal_create_trng(Versal *s, qemu_irq *pic) 379 { 380 SysBusDevice *sbd; 381 MemoryRegion *mr; 382 383 object_initialize_child(OBJECT(s), "trng", &s->pmc.trng, 384 TYPE_XLNX_VERSAL_TRNG); 385 sbd = SYS_BUS_DEVICE(&s->pmc.trng); 386 sysbus_realize(sbd, &error_fatal); 387 388 mr = sysbus_mmio_get_region(sbd, 0); 389 memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr); 390 sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]); 391 } 392 393 static void versal_create_xrams(Versal *s, qemu_irq *pic) 394 { 395 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); 396 DeviceState *orgate; 397 int i; 398 399 /* XRAM IRQs get ORed into a single line. */ 400 object_initialize_child(OBJECT(s), "xram-irq-orgate", 401 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); 402 orgate = DEVICE(&s->lpd.xram.irq_orgate); 403 object_property_set_int(OBJECT(orgate), 404 "num-lines", nr_xrams, &error_fatal); 405 qdev_realize(orgate, NULL, &error_fatal); 406 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); 407 408 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { 409 SysBusDevice *sbd; 410 MemoryRegion *mr; 411 412 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], 413 TYPE_XLNX_XRAM_CTRL); 414 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); 415 sysbus_realize(sbd, &error_fatal); 416 417 mr = sysbus_mmio_get_region(sbd, 0); 418 memory_region_add_subregion(&s->mr_ps, 419 MM_XRAMC + i * MM_XRAMC_SIZE, mr); 420 mr = sysbus_mmio_get_region(sbd, 1); 421 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); 422 423 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); 424 } 425 } 426 427 static void versal_create_bbram(Versal *s, qemu_irq *pic) 428 { 429 SysBusDevice *sbd; 430 431 object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, 432 sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, 433 &error_fatal, 434 "crc-zpads", "0", 435 NULL); 436 sbd = SYS_BUS_DEVICE(&s->pmc.bbram); 437 438 sysbus_realize(sbd, &error_fatal); 439 memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, 440 sysbus_mmio_get_region(sbd, 0)); 441 sysbus_connect_irq(sbd, 0, 442 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1)); 443 } 444 445 static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) 446 { 447 SysBusDevice *part = SYS_BUS_DEVICE(dev); 448 449 object_property_set_link(OBJECT(part), "efuse", 450 OBJECT(&s->pmc.efuse), &error_abort); 451 452 sysbus_realize(part, &error_abort); 453 memory_region_add_subregion(&s->mr_ps, base, 454 sysbus_mmio_get_region(part, 0)); 455 } 456 457 static void versal_create_efuse(Versal *s, qemu_irq *pic) 458 { 459 Object *bits = OBJECT(&s->pmc.efuse); 460 Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); 461 Object *cache = OBJECT(&s->pmc.efuse_cache); 462 463 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, 464 TYPE_XLNX_VERSAL_EFUSE_CTRL); 465 466 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, 467 TYPE_XLNX_VERSAL_EFUSE_CACHE); 468 469 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 470 sizeof(s->pmc.efuse), 471 TYPE_XLNX_EFUSE, &error_abort, 472 "efuse-nr", "3", 473 "efuse-size", "8192", 474 NULL); 475 476 qdev_realize(DEVICE(bits), NULL, &error_abort); 477 versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); 478 versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); 479 480 sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); 481 } 482 483 static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) 484 { 485 SysBusDevice *sbd; 486 487 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, 488 TYPE_XILINX_VERSAL_PMC_IOU_SLCR); 489 490 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); 491 sysbus_realize(sbd, &error_fatal); 492 493 memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, 494 sysbus_mmio_get_region(sbd, 0)); 495 496 sysbus_connect_irq(sbd, 0, 497 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); 498 } 499 500 static void versal_create_ospi(Versal *s, qemu_irq *pic) 501 { 502 SysBusDevice *sbd; 503 MemoryRegion *mr_dac; 504 qemu_irq ospi_mux_sel; 505 DeviceState *orgate; 506 507 memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), 508 "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); 509 510 object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi, 511 TYPE_XILINX_VERSAL_OSPI); 512 513 mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1); 514 memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); 515 516 /* Create the OSPI destination DMA */ 517 object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", 518 &s->pmc.iou.ospi.dma_dst, 519 TYPE_XLNX_CSU_DMA); 520 521 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), 522 "dma", OBJECT(get_system_memory()), 523 &error_abort); 524 525 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); 526 sysbus_realize(sbd, &error_fatal); 527 528 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, 529 sysbus_mmio_get_region(sbd, 0)); 530 531 /* Create the OSPI source DMA */ 532 object_initialize_child(OBJECT(s), "versal-ospi-dma-src", 533 &s->pmc.iou.ospi.dma_src, 534 TYPE_XLNX_CSU_DMA); 535 536 object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", 537 false, &error_abort); 538 539 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 540 "dma", OBJECT(mr_dac), &error_abort); 541 542 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 543 "stream-connected-dma", 544 OBJECT(&s->pmc.iou.ospi.dma_dst), 545 &error_abort); 546 547 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); 548 sysbus_realize(sbd, &error_fatal); 549 550 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, 551 sysbus_mmio_get_region(sbd, 0)); 552 553 /* Realize the OSPI */ 554 object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", 555 OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort); 556 557 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); 558 sysbus_realize(sbd, &error_fatal); 559 560 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, 561 sysbus_mmio_get_region(sbd, 0)); 562 563 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, 564 &s->pmc.iou.ospi.linear_mr); 565 566 /* ospi_mux_sel */ 567 ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi), 568 "ospi-mux-sel", 0); 569 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, 570 ospi_mux_sel); 571 572 /* OSPI irq */ 573 object_initialize_child(OBJECT(s), "ospi-irq-orgate", 574 &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ); 575 object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate), 576 "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); 577 578 orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate); 579 qdev_realize(orgate, NULL, &error_fatal); 580 581 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, 582 qdev_get_gpio_in(orgate, 0)); 583 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, 584 qdev_get_gpio_in(orgate, 1)); 585 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, 586 qdev_get_gpio_in(orgate, 2)); 587 588 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); 589 } 590 591 static void versal_create_cfu(Versal *s, qemu_irq *pic) 592 { 593 SysBusDevice *sbd; 594 DeviceState *dev; 595 int i; 596 const struct { 597 uint64_t reg_base; 598 uint64_t fdri_base; 599 } cframe_addr[] = { 600 { MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI }, 601 { MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI }, 602 { MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI }, 603 { MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI }, 604 { MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI }, 605 { MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI }, 606 { MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI }, 607 { MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI }, 608 { MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI }, 609 { MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI }, 610 { MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI }, 611 { MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI }, 612 { MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI }, 613 { MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI }, 614 { MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI }, 615 }; 616 const struct { 617 uint32_t blktype0_frames; 618 uint32_t blktype1_frames; 619 uint32_t blktype2_frames; 620 uint32_t blktype3_frames; 621 uint32_t blktype4_frames; 622 uint32_t blktype5_frames; 623 uint32_t blktype6_frames; 624 } cframe_cfg[] = { 625 [0] = { 34111, 3528, 12800, 11, 5, 1, 1 }, 626 [1] = { 38498, 3841, 15361, 13, 7, 3, 1 }, 627 [2] = { 38498, 3841, 15361, 13, 7, 3, 1 }, 628 [3] = { 38498, 3841, 15361, 13, 7, 3, 1 }, 629 }; 630 631 /* CFU FDRO */ 632 object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro, 633 TYPE_XLNX_VERSAL_CFU_FDRO); 634 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro); 635 636 sysbus_realize(sbd, &error_fatal); 637 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO, 638 sysbus_mmio_get_region(sbd, 0)); 639 640 /* CFRAME REG */ 641 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { 642 g_autofree char *name = g_strdup_printf("cframe%d", i); 643 644 object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i], 645 TYPE_XLNX_VERSAL_CFRAME_REG); 646 647 sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]); 648 dev = DEVICE(&s->pmc.cframe[i]); 649 650 if (i < ARRAY_SIZE(cframe_cfg)) { 651 object_property_set_int(OBJECT(dev), "blktype0-frames", 652 cframe_cfg[i].blktype0_frames, 653 &error_abort); 654 object_property_set_int(OBJECT(dev), "blktype1-frames", 655 cframe_cfg[i].blktype1_frames, 656 &error_abort); 657 object_property_set_int(OBJECT(dev), "blktype2-frames", 658 cframe_cfg[i].blktype2_frames, 659 &error_abort); 660 object_property_set_int(OBJECT(dev), "blktype3-frames", 661 cframe_cfg[i].blktype3_frames, 662 &error_abort); 663 object_property_set_int(OBJECT(dev), "blktype4-frames", 664 cframe_cfg[i].blktype4_frames, 665 &error_abort); 666 object_property_set_int(OBJECT(dev), "blktype5-frames", 667 cframe_cfg[i].blktype5_frames, 668 &error_abort); 669 object_property_set_int(OBJECT(dev), "blktype6-frames", 670 cframe_cfg[i].blktype6_frames, 671 &error_abort); 672 } 673 object_property_set_link(OBJECT(dev), "cfu-fdro", 674 OBJECT(&s->pmc.cfu_fdro), &error_fatal); 675 676 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 677 678 memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base, 679 sysbus_mmio_get_region(sbd, 0)); 680 memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base, 681 sysbus_mmio_get_region(sbd, 1)); 682 sysbus_connect_irq(sbd, 0, 683 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 684 3 + i)); 685 } 686 687 /* CFRAME BCAST */ 688 object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast, 689 TYPE_XLNX_VERSAL_CFRAME_BCAST_REG); 690 691 sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast); 692 dev = DEVICE(&s->pmc.cframe_bcast); 693 694 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { 695 g_autofree char *propname = g_strdup_printf("cframe%d", i); 696 object_property_set_link(OBJECT(dev), propname, 697 OBJECT(&s->pmc.cframe[i]), &error_fatal); 698 } 699 700 sysbus_realize(sbd, &error_fatal); 701 702 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG, 703 sysbus_mmio_get_region(sbd, 0)); 704 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI, 705 sysbus_mmio_get_region(sbd, 1)); 706 707 /* CFU APB */ 708 object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb, 709 TYPE_XLNX_VERSAL_CFU_APB); 710 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb); 711 dev = DEVICE(&s->pmc.cfu_apb); 712 713 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { 714 g_autofree char *propname = g_strdup_printf("cframe%d", i); 715 object_property_set_link(OBJECT(dev), propname, 716 OBJECT(&s->pmc.cframe[i]), &error_fatal); 717 } 718 719 sysbus_realize(sbd, &error_fatal); 720 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB, 721 sysbus_mmio_get_region(sbd, 0)); 722 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM, 723 sysbus_mmio_get_region(sbd, 1)); 724 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2, 725 sysbus_mmio_get_region(sbd, 2)); 726 sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]); 727 728 /* CFU SFR */ 729 object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr, 730 TYPE_XLNX_VERSAL_CFU_SFR); 731 732 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr); 733 734 object_property_set_link(OBJECT(&s->pmc.cfu_sfr), 735 "cfu", OBJECT(&s->pmc.cfu_apb), &error_abort); 736 737 sysbus_realize(sbd, &error_fatal); 738 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR, 739 sysbus_mmio_get_region(sbd, 0)); 740 } 741 742 static void versal_create_crl(Versal *s, qemu_irq *pic) 743 { 744 SysBusDevice *sbd; 745 int i; 746 747 object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, 748 TYPE_XLNX_VERSAL_CRL); 749 sbd = SYS_BUS_DEVICE(&s->lpd.crl); 750 751 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 752 g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); 753 754 object_property_set_link(OBJECT(&s->lpd.crl), 755 name, OBJECT(&s->lpd.rpu.cpu[i]), 756 &error_abort); 757 } 758 759 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 760 g_autofree gchar *name = g_strdup_printf("gem[%d]", i); 761 762 object_property_set_link(OBJECT(&s->lpd.crl), 763 name, OBJECT(&s->lpd.iou.gem[i]), 764 &error_abort); 765 } 766 767 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 768 g_autofree gchar *name = g_strdup_printf("adma[%d]", i); 769 770 object_property_set_link(OBJECT(&s->lpd.crl), 771 name, OBJECT(&s->lpd.iou.adma[i]), 772 &error_abort); 773 } 774 775 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 776 g_autofree gchar *name = g_strdup_printf("uart[%d]", i); 777 778 object_property_set_link(OBJECT(&s->lpd.crl), 779 name, OBJECT(&s->lpd.iou.uart[i]), 780 &error_abort); 781 } 782 783 object_property_set_link(OBJECT(&s->lpd.crl), 784 "usb", OBJECT(&s->lpd.iou.usb), 785 &error_abort); 786 787 sysbus_realize(sbd, &error_fatal); 788 memory_region_add_subregion(&s->mr_ps, MM_CRL, 789 sysbus_mmio_get_region(sbd, 0)); 790 sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); 791 } 792 793 /* This takes the board allocated linear DDR memory and creates aliases 794 * for each split DDR range/aperture on the Versal address map. 795 */ 796 static void versal_map_ddr(Versal *s) 797 { 798 uint64_t size = memory_region_size(s->cfg.mr_ddr); 799 /* Describes the various split DDR access regions. */ 800 static const struct { 801 uint64_t base; 802 uint64_t size; 803 } addr_ranges[] = { 804 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 805 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 806 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 807 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 808 }; 809 uint64_t offset = 0; 810 int i; 811 812 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); 813 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 814 char *name; 815 uint64_t mapsize; 816 817 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 818 name = g_strdup_printf("noc-ddr-range%d", i); 819 /* Create the MR alias. */ 820 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), 821 name, s->cfg.mr_ddr, 822 offset, mapsize); 823 824 /* Map it onto the NoC MR. */ 825 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, 826 &s->noc.mr_ddr_ranges[i]); 827 offset += mapsize; 828 size -= mapsize; 829 g_free(name); 830 } 831 } 832 833 static void versal_unimp_area(Versal *s, const char *name, 834 MemoryRegion *mr, 835 hwaddr base, hwaddr size) 836 { 837 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 838 MemoryRegion *mr_dev; 839 840 qdev_prop_set_string(dev, "name", name); 841 qdev_prop_set_uint64(dev, "size", size); 842 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 843 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 844 845 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 846 memory_region_add_subregion(mr, base, mr_dev); 847 } 848 849 static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level) 850 { 851 qemu_log_mask(LOG_UNIMP, 852 "Selecting between enabling SD mode or eMMC mode on " 853 "controller %d is not yet implemented\n", n); 854 } 855 856 static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level) 857 { 858 qemu_log_mask(LOG_UNIMP, 859 "Selecting between enabling the QSPI or OSPI linear address " 860 "region is not yet implemented\n"); 861 } 862 863 static void versal_unimp_irq_parity_imr(void *opaque, int n, int level) 864 { 865 qemu_log_mask(LOG_UNIMP, 866 "PMC SLCR parity interrupt behaviour " 867 "is not yet implemented\n"); 868 } 869 870 static void versal_unimp(Versal *s) 871 { 872 qemu_irq gpio_in; 873 874 versal_unimp_area(s, "psm", &s->mr_ps, 875 MM_PSM_START, MM_PSM_END - MM_PSM_START); 876 versal_unimp_area(s, "crf", &s->mr_ps, 877 MM_FPD_CRF, MM_FPD_CRF_SIZE); 878 versal_unimp_area(s, "apu", &s->mr_ps, 879 MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE); 880 versal_unimp_area(s, "crp", &s->mr_ps, 881 MM_PMC_CRP, MM_PMC_CRP_SIZE); 882 versal_unimp_area(s, "iou-scntr", &s->mr_ps, 883 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); 884 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, 885 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); 886 887 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, 888 "sd-emmc-sel-dummy", 2); 889 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel, 890 "qspi-ospi-mux-sel-dummy", 1); 891 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr, 892 "irq-parity-imr-dummy", 1); 893 894 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0); 895 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, 896 gpio_in); 897 898 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1); 899 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, 900 gpio_in); 901 902 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); 903 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 904 "qspi-ospi-mux-sel", 0, 905 gpio_in); 906 907 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); 908 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 909 SYSBUS_DEVICE_GPIO_IRQ, 0, 910 gpio_in); 911 } 912 913 static void versal_realize(DeviceState *dev, Error **errp) 914 { 915 Versal *s = XLNX_VERSAL(dev); 916 qemu_irq pic[XLNX_VERSAL_NR_IRQS]; 917 918 versal_create_apu_cpus(s); 919 versal_create_apu_gic(s, pic); 920 versal_create_rpu_cpus(s); 921 versal_create_uarts(s, pic); 922 versal_create_canfds(s, pic); 923 versal_create_usbs(s, pic); 924 versal_create_gems(s, pic); 925 versal_create_admas(s, pic); 926 versal_create_sds(s, pic); 927 versal_create_pmc_apb_irq_orgate(s, pic); 928 versal_create_rtc(s, pic); 929 versal_create_trng(s, pic); 930 versal_create_xrams(s, pic); 931 versal_create_bbram(s, pic); 932 versal_create_efuse(s, pic); 933 versal_create_pmc_iou_slcr(s, pic); 934 versal_create_ospi(s, pic); 935 versal_create_crl(s, pic); 936 versal_create_cfu(s, pic); 937 versal_map_ddr(s); 938 versal_unimp(s); 939 940 /* Create the On Chip Memory (OCM). */ 941 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", 942 MM_OCM_SIZE, &error_fatal); 943 944 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); 945 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); 946 memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, 947 &s->lpd.rpu.mr_ps_alias, 0); 948 } 949 950 static void versal_init(Object *obj) 951 { 952 Versal *s = XLNX_VERSAL(obj); 953 954 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); 955 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); 956 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); 957 memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), 958 "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); 959 } 960 961 static Property versal_properties[] = { 962 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, 963 MemoryRegion *), 964 DEFINE_PROP_LINK("canbus0", Versal, lpd.iou.canbus[0], 965 TYPE_CAN_BUS, CanBusState *), 966 DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1], 967 TYPE_CAN_BUS, CanBusState *), 968 DEFINE_PROP_END_OF_LIST() 969 }; 970 971 static void versal_class_init(ObjectClass *klass, void *data) 972 { 973 DeviceClass *dc = DEVICE_CLASS(klass); 974 975 dc->realize = versal_realize; 976 device_class_set_props(dc, versal_properties); 977 /* No VMSD since we haven't got any top-level SoC state to save. */ 978 } 979 980 static const TypeInfo versal_info = { 981 .name = TYPE_XLNX_VERSAL, 982 .parent = TYPE_SYS_BUS_DEVICE, 983 .instance_size = sizeof(Versal), 984 .instance_init = versal_init, 985 .class_init = versal_class_init, 986 }; 987 988 static void versal_register_types(void) 989 { 990 type_register_static(&versal_info); 991 } 992 993 type_init(versal_register_types); 994