1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "cpu.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/boot.h" 24 #include "net/net.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/boards.h" 27 #include "hw/block/flash.h" 28 #include "hw/loader.h" 29 #include "hw/adc/zynq-xadc.h" 30 #include "hw/ssi/ssi.h" 31 #include "hw/usb/chipidea.h" 32 #include "qemu/error-report.h" 33 #include "hw/sd/sdhci.h" 34 #include "hw/char/cadence_uart.h" 35 #include "hw/net/cadence_gem.h" 36 #include "hw/cpu/a9mpcore.h" 37 #include "hw/qdev-clock.h" 38 #include "sysemu/reset.h" 39 #include "qom/object.h" 40 #include "exec/tswap.h" 41 #include "target/arm/cpu-qom.h" 42 43 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") 44 OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) 45 46 /* board base frequency: 33.333333 MHz */ 47 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) 48 49 #define NUM_SPI_FLASHES 4 50 #define NUM_QSPI_FLASHES 2 51 #define NUM_QSPI_BUSSES 2 52 53 #define FLASH_SIZE (64 * 1024 * 1024) 54 #define FLASH_SECTOR_SIZE (128 * 1024) 55 56 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 57 58 #define MPCORE_PERIPHBASE 0xF8F00000 59 #define ZYNQ_BOARD_MIDR 0x413FC090 60 61 static const int dma_irqs[8] = { 62 46, 47, 48, 49, 72, 73, 74, 75 63 }; 64 65 #define BOARD_SETUP_ADDR 0x100 66 67 #define SLCR_LOCK_OFFSET 0x004 68 #define SLCR_UNLOCK_OFFSET 0x008 69 #define SLCR_ARM_PLL_OFFSET 0x100 70 71 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 72 #define SLCR_XILINX_LOCK_KEY 0x767b 73 74 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ 75 76 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 77 extract32((x), 12, 4) << 16) 78 79 /* Write immediate val to address r0 + addr. r0 should contain base offset 80 * of the SLCR block. Clobbers r1. 81 */ 82 83 #define SLCR_WRITE(addr, val) \ 84 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 85 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 86 0xe5801000 + (addr) 87 88 struct ZynqMachineState { 89 MachineState parent; 90 Clock *ps_clk; 91 }; 92 93 static void zynq_write_board_setup(ARMCPU *cpu, 94 const struct arm_boot_info *info) 95 { 96 int n; 97 uint32_t board_setup_blob[] = { 98 0xe3a004f8, /* mov r0, #0xf8000000 */ 99 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 100 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 101 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 102 0xe12fff1e, /* bx lr */ 103 }; 104 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 105 board_setup_blob[n] = tswap32(board_setup_blob[n]); 106 } 107 rom_add_blob_fixed("board-setup", board_setup_blob, 108 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 109 } 110 111 static struct arm_boot_info zynq_binfo = {}; 112 113 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 114 { 115 DeviceState *dev; 116 SysBusDevice *s; 117 118 dev = qdev_new(TYPE_CADENCE_GEM); 119 if (nd->used) { 120 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 121 qdev_set_nic_properties(dev, nd); 122 } 123 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); 124 s = SYS_BUS_DEVICE(dev); 125 sysbus_realize_and_unref(s, &error_fatal); 126 sysbus_mmio_map(s, 0, base); 127 sysbus_connect_irq(s, 0, irq); 128 } 129 130 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 131 bool is_qspi, int unit0) 132 { 133 int unit = unit0; 134 DeviceState *dev; 135 SysBusDevice *busdev; 136 SSIBus *spi; 137 DeviceState *flash_dev; 138 int i, j; 139 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 140 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 141 142 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 143 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 144 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 145 qdev_prop_set_uint8(dev, "num-busses", num_busses); 146 busdev = SYS_BUS_DEVICE(dev); 147 sysbus_realize_and_unref(busdev, &error_fatal); 148 sysbus_mmio_map(busdev, 0, base_addr); 149 if (is_qspi) { 150 sysbus_mmio_map(busdev, 1, 0xFC000000); 151 } 152 sysbus_connect_irq(busdev, 0, irq); 153 154 for (i = 0; i < num_busses; ++i) { 155 char bus_name[16]; 156 qemu_irq cs_line; 157 158 snprintf(bus_name, 16, "spi%d", i); 159 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 160 161 for (j = 0; j < num_ss; ++j) { 162 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); 163 flash_dev = qdev_new("n25q128"); 164 if (dinfo) { 165 qdev_prop_set_drive_err(flash_dev, "drive", 166 blk_by_legacy_dinfo(dinfo), 167 &error_fatal); 168 } 169 qdev_prop_set_uint8(flash_dev, "cs", j); 170 qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal); 171 172 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 173 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 174 } 175 } 176 177 return unit; 178 } 179 180 static void zynq_init(MachineState *machine) 181 { 182 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); 183 ARMCPU *cpu; 184 MemoryRegion *address_space_mem = get_system_memory(); 185 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 186 DeviceState *dev, *slcr; 187 SysBusDevice *busdev; 188 qemu_irq pic[64]; 189 int n; 190 191 /* max 2GB ram */ 192 if (machine->ram_size > 2 * GiB) { 193 error_report("RAM size more than 2 GiB is not supported"); 194 exit(EXIT_FAILURE); 195 } 196 197 cpu = ARM_CPU(object_new(machine->cpu_type)); 198 199 /* By default A9 CPUs have EL3 enabled. This board does not 200 * currently support EL3 so the CPU EL3 property is disabled before 201 * realization. 202 */ 203 if (object_property_find(OBJECT(cpu), "has_el3")) { 204 object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal); 205 } 206 207 object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR, 208 &error_fatal); 209 object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE, 210 &error_fatal); 211 qdev_realize(DEVICE(cpu), NULL, &error_fatal); 212 213 /* DDR remapped to address zero. */ 214 memory_region_add_subregion(address_space_mem, 0, machine->ram); 215 216 /* 256K of on-chip memory */ 217 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, 218 &error_fatal); 219 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 220 221 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 222 223 /* AMD */ 224 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, 225 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 226 FLASH_SECTOR_SIZE, 1, 227 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 228 0); 229 230 /* Create the main clock source, and feed slcr with it */ 231 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); 232 object_property_add_child(OBJECT(zynq_machine), "ps_clk", 233 OBJECT(zynq_machine->ps_clk)); 234 object_unref(OBJECT(zynq_machine->ps_clk)); 235 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); 236 237 /* Create slcr, keep a pointer to connect clocks */ 238 slcr = qdev_new("xilinx-zynq_slcr"); 239 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); 240 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); 241 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); 242 243 dev = qdev_new(TYPE_A9MPCORE_PRIV); 244 qdev_prop_set_uint32(dev, "num-cpu", 1); 245 busdev = SYS_BUS_DEVICE(dev); 246 sysbus_realize_and_unref(busdev, &error_fatal); 247 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 248 sysbus_connect_irq(busdev, 0, 249 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 250 251 for (n = 0; n < 64; n++) { 252 pic[n] = qdev_get_gpio_in(dev, n); 253 } 254 255 n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0); 256 n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n); 257 n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); 258 259 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); 260 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); 261 262 dev = qdev_new(TYPE_CADENCE_UART); 263 busdev = SYS_BUS_DEVICE(dev); 264 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 265 qdev_connect_clock_in(dev, "refclk", 266 qdev_get_clock_out(slcr, "uart0_ref_clk")); 267 sysbus_realize_and_unref(busdev, &error_fatal); 268 sysbus_mmio_map(busdev, 0, 0xE0000000); 269 sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); 270 dev = qdev_new(TYPE_CADENCE_UART); 271 busdev = SYS_BUS_DEVICE(dev); 272 qdev_prop_set_chr(dev, "chardev", serial_hd(1)); 273 qdev_connect_clock_in(dev, "refclk", 274 qdev_get_clock_out(slcr, "uart1_ref_clk")); 275 sysbus_realize_and_unref(busdev, &error_fatal); 276 sysbus_mmio_map(busdev, 0, 0xE0001000); 277 sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); 278 279 sysbus_create_varargs("cadence_ttc", 0xF8001000, 280 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 281 sysbus_create_varargs("cadence_ttc", 0xF8002000, 282 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 283 284 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 285 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 286 287 for (n = 0; n < 2; n++) { 288 int hci_irq = n ? 79 : 56; 289 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; 290 DriveInfo *di; 291 BlockBackend *blk; 292 DeviceState *carddev; 293 294 /* Compatible with: 295 * - SD Host Controller Specification Version 2.0 Part A2 296 * - SDIO Specification Version 2.0 297 * - MMC Specification Version 3.31 298 */ 299 dev = qdev_new(TYPE_SYSBUS_SDHCI); 300 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 301 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); 302 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 303 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); 304 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); 305 306 di = drive_get(IF_SD, 0, n); 307 blk = di ? blk_by_legacy_dinfo(di) : NULL; 308 carddev = qdev_new(TYPE_SD_CARD); 309 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 310 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 311 &error_fatal); 312 } 313 314 dev = qdev_new(TYPE_ZYNQ_XADC); 315 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 316 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 317 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 318 319 dev = qdev_new("pl330"); 320 object_property_set_link(OBJECT(dev), "memory", 321 OBJECT(address_space_mem), 322 &error_fatal); 323 qdev_prop_set_uint8(dev, "num_chnls", 8); 324 qdev_prop_set_uint8(dev, "num_periph_req", 4); 325 qdev_prop_set_uint8(dev, "num_events", 16); 326 327 qdev_prop_set_uint8(dev, "data_width", 64); 328 qdev_prop_set_uint8(dev, "wr_cap", 8); 329 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 330 qdev_prop_set_uint8(dev, "rd_cap", 8); 331 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 332 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 333 334 busdev = SYS_BUS_DEVICE(dev); 335 sysbus_realize_and_unref(busdev, &error_fatal); 336 sysbus_mmio_map(busdev, 0, 0xF8003000); 337 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 338 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ 339 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 340 } 341 342 dev = qdev_new("xlnx.ps7-dev-cfg"); 343 busdev = SYS_BUS_DEVICE(dev); 344 sysbus_realize_and_unref(busdev, &error_fatal); 345 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 346 sysbus_mmio_map(busdev, 0, 0xF8007000); 347 348 zynq_binfo.ram_size = machine->ram_size; 349 zynq_binfo.board_id = 0xd32; 350 zynq_binfo.loader_start = 0; 351 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 352 zynq_binfo.write_board_setup = zynq_write_board_setup; 353 354 arm_load_kernel(cpu, machine, &zynq_binfo); 355 } 356 357 static void zynq_machine_class_init(ObjectClass *oc, void *data) 358 { 359 MachineClass *mc = MACHINE_CLASS(oc); 360 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 361 mc->init = zynq_init; 362 mc->max_cpus = 1; 363 mc->no_sdcard = 1; 364 mc->ignore_memory_transaction_failures = true; 365 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 366 mc->default_ram_id = "zynq.ext_ram"; 367 } 368 369 static const TypeInfo zynq_machine_type = { 370 .name = TYPE_ZYNQ_MACHINE, 371 .parent = TYPE_MACHINE, 372 .class_init = zynq_machine_class_init, 373 .instance_size = sizeof(ZynqMachineState), 374 }; 375 376 static void zynq_machine_register_types(void) 377 { 378 type_register_static(&zynq_machine_type); 379 } 380 381 type_init(zynq_machine_register_types) 382