1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "hw/sysbus.h" 19 #include "hw/arm/arm.h" 20 #include "net/net.h" 21 #include "exec/address-spaces.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/boards.h" 24 #include "hw/block/flash.h" 25 #include "sysemu/block-backend.h" 26 #include "hw/loader.h" 27 #include "hw/ssi.h" 28 #include "qemu/error-report.h" 29 30 #define NUM_SPI_FLASHES 4 31 #define NUM_QSPI_FLASHES 2 32 #define NUM_QSPI_BUSSES 2 33 34 #define FLASH_SIZE (64 * 1024 * 1024) 35 #define FLASH_SECTOR_SIZE (128 * 1024) 36 37 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 38 39 #define MPCORE_PERIPHBASE 0xF8F00000 40 #define ZYNQ_BOARD_MIDR 0x413FC090 41 42 static const int dma_irqs[8] = { 43 46, 47, 48, 49, 72, 73, 74, 75 44 }; 45 46 #define BOARD_SETUP_ADDR 0x100 47 48 #define SLCR_LOCK_OFFSET 0x004 49 #define SLCR_UNLOCK_OFFSET 0x008 50 #define SLCR_ARM_PLL_OFFSET 0x100 51 52 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 53 #define SLCR_XILINX_LOCK_KEY 0x767b 54 55 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 56 extract32((x), 12, 4) << 16) 57 58 /* Write immediate val to address r0 + addr. r0 should contain base offset 59 * of the SLCR block. Clobbers r1. 60 */ 61 62 #define SLCR_WRITE(addr, val) \ 63 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 64 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 65 0xe5801000 + (addr) 66 67 static void zynq_write_board_setup(ARMCPU *cpu, 68 const struct arm_boot_info *info) 69 { 70 int n; 71 uint32_t board_setup_blob[] = { 72 0xe3a004f8, /* mov r0, #0xf8000000 */ 73 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 74 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 75 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 76 0xe12fff1e, /* bx lr */ 77 }; 78 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 79 board_setup_blob[n] = tswap32(board_setup_blob[n]); 80 } 81 rom_add_blob_fixed("board-setup", board_setup_blob, 82 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 83 } 84 85 static struct arm_boot_info zynq_binfo = {}; 86 87 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 88 { 89 DeviceState *dev; 90 SysBusDevice *s; 91 92 dev = qdev_create(NULL, "cadence_gem"); 93 if (nd->used) { 94 qemu_check_nic_model(nd, "cadence_gem"); 95 qdev_set_nic_properties(dev, nd); 96 } 97 qdev_init_nofail(dev); 98 s = SYS_BUS_DEVICE(dev); 99 sysbus_mmio_map(s, 0, base); 100 sysbus_connect_irq(s, 0, irq); 101 } 102 103 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 104 bool is_qspi) 105 { 106 DeviceState *dev; 107 SysBusDevice *busdev; 108 SSIBus *spi; 109 DeviceState *flash_dev; 110 int i, j; 111 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 112 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 113 114 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 115 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 116 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 117 qdev_prop_set_uint8(dev, "num-busses", num_busses); 118 qdev_init_nofail(dev); 119 busdev = SYS_BUS_DEVICE(dev); 120 sysbus_mmio_map(busdev, 0, base_addr); 121 if (is_qspi) { 122 sysbus_mmio_map(busdev, 1, 0xFC000000); 123 } 124 sysbus_connect_irq(busdev, 0, irq); 125 126 for (i = 0; i < num_busses; ++i) { 127 char bus_name[16]; 128 qemu_irq cs_line; 129 130 snprintf(bus_name, 16, "spi%d", i); 131 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 132 133 for (j = 0; j < num_ss; ++j) { 134 flash_dev = ssi_create_slave(spi, "n25q128"); 135 136 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 137 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 138 } 139 } 140 141 } 142 143 static void zynq_init(MachineState *machine) 144 { 145 ram_addr_t ram_size = machine->ram_size; 146 const char *cpu_model = machine->cpu_model; 147 const char *kernel_filename = machine->kernel_filename; 148 const char *kernel_cmdline = machine->kernel_cmdline; 149 const char *initrd_filename = machine->initrd_filename; 150 ObjectClass *cpu_oc; 151 ARMCPU *cpu; 152 MemoryRegion *address_space_mem = get_system_memory(); 153 MemoryRegion *ext_ram = g_new(MemoryRegion, 1); 154 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 155 DeviceState *dev; 156 SysBusDevice *busdev; 157 qemu_irq pic[64]; 158 Error *err = NULL; 159 int n; 160 161 if (!cpu_model) { 162 cpu_model = "cortex-a9"; 163 } 164 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 165 166 cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); 167 168 /* By default A9 CPUs have EL3 enabled. This board does not 169 * currently support EL3 so the CPU EL3 property is disabled before 170 * realization. 171 */ 172 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { 173 object_property_set_bool(OBJECT(cpu), false, "has_el3", &err); 174 if (err) { 175 error_report_err(err); 176 exit(1); 177 } 178 } 179 180 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err); 181 if (err) { 182 error_report_err(err); 183 exit(1); 184 } 185 186 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err); 187 if (err) { 188 error_report_err(err); 189 exit(1); 190 } 191 object_property_set_bool(OBJECT(cpu), true, "realized", &err); 192 if (err) { 193 error_report_err(err); 194 exit(1); 195 } 196 197 /* max 2GB ram */ 198 if (ram_size > 0x80000000) { 199 ram_size = 0x80000000; 200 } 201 202 /* DDR remapped to address zero. */ 203 memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", 204 ram_size); 205 memory_region_add_subregion(address_space_mem, 0, ext_ram); 206 207 /* 256K of on-chip memory */ 208 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, 209 &error_fatal); 210 vmstate_register_ram_global(ocm_ram); 211 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 212 213 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 214 215 /* AMD */ 216 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, 217 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 218 FLASH_SECTOR_SIZE, 219 FLASH_SIZE/FLASH_SECTOR_SIZE, 1, 220 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 221 0); 222 223 dev = qdev_create(NULL, "xilinx,zynq_slcr"); 224 qdev_init_nofail(dev); 225 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); 226 227 dev = qdev_create(NULL, "a9mpcore_priv"); 228 qdev_prop_set_uint32(dev, "num-cpu", 1); 229 qdev_init_nofail(dev); 230 busdev = SYS_BUS_DEVICE(dev); 231 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 232 sysbus_connect_irq(busdev, 0, 233 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 234 235 for (n = 0; n < 64; n++) { 236 pic[n] = qdev_get_gpio_in(dev, n); 237 } 238 239 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 240 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 241 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 242 243 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); 244 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); 245 246 sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); 247 sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]); 248 249 sysbus_create_varargs("cadence_ttc", 0xF8001000, 250 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 251 sysbus_create_varargs("cadence_ttc", 0xF8002000, 252 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 253 254 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 255 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 256 257 dev = qdev_create(NULL, "generic-sdhci"); 258 qdev_init_nofail(dev); 259 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); 260 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); 261 262 dev = qdev_create(NULL, "generic-sdhci"); 263 qdev_init_nofail(dev); 264 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); 265 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); 266 267 dev = qdev_create(NULL, "pl330"); 268 qdev_prop_set_uint8(dev, "num_chnls", 8); 269 qdev_prop_set_uint8(dev, "num_periph_req", 4); 270 qdev_prop_set_uint8(dev, "num_events", 16); 271 272 qdev_prop_set_uint8(dev, "data_width", 64); 273 qdev_prop_set_uint8(dev, "wr_cap", 8); 274 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 275 qdev_prop_set_uint8(dev, "rd_cap", 8); 276 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 277 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 278 279 qdev_init_nofail(dev); 280 busdev = SYS_BUS_DEVICE(dev); 281 sysbus_mmio_map(busdev, 0, 0xF8003000); 282 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 283 for (n = 0; n < 8; ++n) { /* event irqs */ 284 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 285 } 286 287 zynq_binfo.ram_size = ram_size; 288 zynq_binfo.kernel_filename = kernel_filename; 289 zynq_binfo.kernel_cmdline = kernel_cmdline; 290 zynq_binfo.initrd_filename = initrd_filename; 291 zynq_binfo.nb_cpus = 1; 292 zynq_binfo.board_id = 0xd32; 293 zynq_binfo.loader_start = 0; 294 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 295 zynq_binfo.write_board_setup = zynq_write_board_setup; 296 297 arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); 298 } 299 300 static void zynq_machine_init(MachineClass *mc) 301 { 302 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 303 mc->init = zynq_init; 304 mc->block_default_type = IF_SCSI; 305 mc->max_cpus = 1; 306 mc->no_sdcard = 1; 307 } 308 309 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) 310