1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "hw/sysbus.h" 19 #include "hw/arm-misc.h" 20 #include "net/net.h" 21 #include "exec/address-spaces.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/boards.h" 24 #include "hw/flash.h" 25 #include "sysemu/blockdev.h" 26 #include "hw/loader.h" 27 #include "hw/ssi.h" 28 29 #define NUM_SPI_FLASHES 4 30 #define NUM_QSPI_FLASHES 2 31 #define NUM_QSPI_BUSSES 2 32 33 #define FLASH_SIZE (64 * 1024 * 1024) 34 #define FLASH_SECTOR_SIZE (128 * 1024) 35 36 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 37 38 static struct arm_boot_info zynq_binfo = {}; 39 40 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 41 { 42 DeviceState *dev; 43 SysBusDevice *s; 44 45 qemu_check_nic_model(nd, "cadence_gem"); 46 dev = qdev_create(NULL, "cadence_gem"); 47 qdev_set_nic_properties(dev, nd); 48 qdev_init_nofail(dev); 49 s = SYS_BUS_DEVICE(dev); 50 sysbus_mmio_map(s, 0, base); 51 sysbus_connect_irq(s, 0, irq); 52 } 53 54 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 55 bool is_qspi) 56 { 57 DeviceState *dev; 58 SysBusDevice *busdev; 59 SSIBus *spi; 60 DeviceState *flash_dev; 61 int i, j; 62 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 63 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 64 65 dev = qdev_create(NULL, "xilinx,spips"); 66 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 67 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 68 qdev_prop_set_uint8(dev, "num-busses", num_busses); 69 qdev_init_nofail(dev); 70 busdev = SYS_BUS_DEVICE(dev); 71 sysbus_mmio_map(busdev, 0, base_addr); 72 if (is_qspi) { 73 sysbus_mmio_map(busdev, 1, 0xFC000000); 74 } 75 sysbus_connect_irq(busdev, 0, irq); 76 77 for (i = 0; i < num_busses; ++i) { 78 char bus_name[16]; 79 qemu_irq cs_line; 80 81 snprintf(bus_name, 16, "spi%d", i); 82 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 83 84 for (j = 0; j < num_ss; ++j) { 85 flash_dev = ssi_create_slave_no_init(spi, "n25q128"); 86 qdev_init_nofail(flash_dev); 87 88 cs_line = qdev_get_gpio_in(flash_dev, 0); 89 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 90 } 91 } 92 93 } 94 95 static void zynq_init(QEMUMachineInitArgs *args) 96 { 97 ram_addr_t ram_size = args->ram_size; 98 const char *cpu_model = args->cpu_model; 99 const char *kernel_filename = args->kernel_filename; 100 const char *kernel_cmdline = args->kernel_cmdline; 101 const char *initrd_filename = args->initrd_filename; 102 ARMCPU *cpu; 103 MemoryRegion *address_space_mem = get_system_memory(); 104 MemoryRegion *ext_ram = g_new(MemoryRegion, 1); 105 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 106 DeviceState *dev; 107 SysBusDevice *busdev; 108 qemu_irq *irqp; 109 qemu_irq pic[64]; 110 NICInfo *nd; 111 int n; 112 qemu_irq cpu_irq; 113 114 if (!cpu_model) { 115 cpu_model = "cortex-a9"; 116 } 117 118 cpu = cpu_arm_init(cpu_model); 119 if (!cpu) { 120 fprintf(stderr, "Unable to find CPU definition\n"); 121 exit(1); 122 } 123 irqp = arm_pic_init_cpu(cpu); 124 cpu_irq = irqp[ARM_PIC_CPU_IRQ]; 125 126 /* max 2GB ram */ 127 if (ram_size > 0x80000000) { 128 ram_size = 0x80000000; 129 } 130 131 /* DDR remapped to address zero. */ 132 memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size); 133 vmstate_register_ram_global(ext_ram); 134 memory_region_add_subregion(address_space_mem, 0, ext_ram); 135 136 /* 256K of on-chip memory */ 137 memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10); 138 vmstate_register_ram_global(ocm_ram); 139 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 140 141 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 142 143 /* AMD */ 144 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, 145 dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE, 146 FLASH_SIZE/FLASH_SECTOR_SIZE, 1, 147 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 148 0); 149 150 dev = qdev_create(NULL, "xilinx,zynq_slcr"); 151 qdev_init_nofail(dev); 152 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); 153 154 dev = qdev_create(NULL, "a9mpcore_priv"); 155 qdev_prop_set_uint32(dev, "num-cpu", 1); 156 qdev_init_nofail(dev); 157 busdev = SYS_BUS_DEVICE(dev); 158 sysbus_mmio_map(busdev, 0, 0xF8F00000); 159 sysbus_connect_irq(busdev, 0, cpu_irq); 160 161 for (n = 0; n < 64; n++) { 162 pic[n] = qdev_get_gpio_in(dev, n); 163 } 164 165 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 166 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 167 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 168 169 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); 170 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); 171 172 sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); 173 sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]); 174 175 sysbus_create_varargs("cadence_ttc", 0xF8001000, 176 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 177 sysbus_create_varargs("cadence_ttc", 0xF8002000, 178 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 179 180 for (n = 0; n < nb_nics; n++) { 181 nd = &nd_table[n]; 182 if (n == 0) { 183 gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]); 184 } else if (n == 1) { 185 gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]); 186 } 187 } 188 189 dev = qdev_create(NULL, "generic-sdhci"); 190 qdev_init_nofail(dev); 191 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); 192 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); 193 194 dev = qdev_create(NULL, "generic-sdhci"); 195 qdev_init_nofail(dev); 196 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); 197 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); 198 199 zynq_binfo.ram_size = ram_size; 200 zynq_binfo.kernel_filename = kernel_filename; 201 zynq_binfo.kernel_cmdline = kernel_cmdline; 202 zynq_binfo.initrd_filename = initrd_filename; 203 zynq_binfo.nb_cpus = 1; 204 zynq_binfo.board_id = 0xd32; 205 zynq_binfo.loader_start = 0; 206 arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo); 207 } 208 209 static QEMUMachine zynq_machine = { 210 .name = "xilinx-zynq-a9", 211 .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9", 212 .init = zynq_init, 213 .block_default_type = IF_SCSI, 214 .max_cpus = 1, 215 .no_sdcard = 1, 216 DEFAULT_MACHINE_OPTIONS, 217 }; 218 219 static void zynq_machine_init(void) 220 { 221 qemu_register_machine(&zynq_machine); 222 } 223 224 machine_init(zynq_machine_init); 225