1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/arm.h" 24 #include "net/net.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/block-backend.h" 30 #include "hw/loader.h" 31 #include "hw/misc/zynq-xadc.h" 32 #include "hw/ssi/ssi.h" 33 #include "qemu/error-report.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/char/cadence_uart.h" 36 #include "hw/net/cadence_gem.h" 37 #include "hw/cpu/a9mpcore.h" 38 39 #define NUM_SPI_FLASHES 4 40 #define NUM_QSPI_FLASHES 2 41 #define NUM_QSPI_BUSSES 2 42 43 #define FLASH_SIZE (64 * 1024 * 1024) 44 #define FLASH_SECTOR_SIZE (128 * 1024) 45 46 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 47 48 #define MPCORE_PERIPHBASE 0xF8F00000 49 #define ZYNQ_BOARD_MIDR 0x413FC090 50 51 static const int dma_irqs[8] = { 52 46, 47, 48, 49, 72, 73, 74, 75 53 }; 54 55 #define BOARD_SETUP_ADDR 0x100 56 57 #define SLCR_LOCK_OFFSET 0x004 58 #define SLCR_UNLOCK_OFFSET 0x008 59 #define SLCR_ARM_PLL_OFFSET 0x100 60 61 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 62 #define SLCR_XILINX_LOCK_KEY 0x767b 63 64 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 65 extract32((x), 12, 4) << 16) 66 67 /* Write immediate val to address r0 + addr. r0 should contain base offset 68 * of the SLCR block. Clobbers r1. 69 */ 70 71 #define SLCR_WRITE(addr, val) \ 72 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 73 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 74 0xe5801000 + (addr) 75 76 static void zynq_write_board_setup(ARMCPU *cpu, 77 const struct arm_boot_info *info) 78 { 79 int n; 80 uint32_t board_setup_blob[] = { 81 0xe3a004f8, /* mov r0, #0xf8000000 */ 82 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 83 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 84 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 85 0xe12fff1e, /* bx lr */ 86 }; 87 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 88 board_setup_blob[n] = tswap32(board_setup_blob[n]); 89 } 90 rom_add_blob_fixed("board-setup", board_setup_blob, 91 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 92 } 93 94 static struct arm_boot_info zynq_binfo = {}; 95 96 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 97 { 98 DeviceState *dev; 99 SysBusDevice *s; 100 101 dev = qdev_create(NULL, TYPE_CADENCE_GEM); 102 if (nd->used) { 103 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 104 qdev_set_nic_properties(dev, nd); 105 } 106 qdev_init_nofail(dev); 107 s = SYS_BUS_DEVICE(dev); 108 sysbus_mmio_map(s, 0, base); 109 sysbus_connect_irq(s, 0, irq); 110 } 111 112 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 113 bool is_qspi) 114 { 115 DeviceState *dev; 116 SysBusDevice *busdev; 117 SSIBus *spi; 118 DeviceState *flash_dev; 119 int i, j; 120 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 121 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 122 123 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 124 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 125 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 126 qdev_prop_set_uint8(dev, "num-busses", num_busses); 127 qdev_init_nofail(dev); 128 busdev = SYS_BUS_DEVICE(dev); 129 sysbus_mmio_map(busdev, 0, base_addr); 130 if (is_qspi) { 131 sysbus_mmio_map(busdev, 1, 0xFC000000); 132 } 133 sysbus_connect_irq(busdev, 0, irq); 134 135 for (i = 0; i < num_busses; ++i) { 136 char bus_name[16]; 137 qemu_irq cs_line; 138 139 snprintf(bus_name, 16, "spi%d", i); 140 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 141 142 for (j = 0; j < num_ss; ++j) { 143 DriveInfo *dinfo = drive_get_next(IF_MTD); 144 flash_dev = ssi_create_slave_no_init(spi, "n25q128"); 145 if (dinfo) { 146 qdev_prop_set_drive(flash_dev, "drive", 147 blk_by_legacy_dinfo(dinfo), &error_fatal); 148 } 149 qdev_init_nofail(flash_dev); 150 151 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 152 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 153 } 154 } 155 156 } 157 158 static void zynq_init(MachineState *machine) 159 { 160 ram_addr_t ram_size = machine->ram_size; 161 const char *cpu_model = machine->cpu_model; 162 const char *kernel_filename = machine->kernel_filename; 163 const char *kernel_cmdline = machine->kernel_cmdline; 164 const char *initrd_filename = machine->initrd_filename; 165 ObjectClass *cpu_oc; 166 ARMCPU *cpu; 167 MemoryRegion *address_space_mem = get_system_memory(); 168 MemoryRegion *ext_ram = g_new(MemoryRegion, 1); 169 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 170 DeviceState *dev, *carddev; 171 SysBusDevice *busdev; 172 DriveInfo *di; 173 BlockBackend *blk; 174 qemu_irq pic[64]; 175 int n; 176 177 if (!cpu_model) { 178 cpu_model = "cortex-a9"; 179 } 180 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 181 182 cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); 183 184 /* By default A9 CPUs have EL3 enabled. This board does not 185 * currently support EL3 so the CPU EL3 property is disabled before 186 * realization. 187 */ 188 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { 189 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); 190 } 191 192 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", 193 &error_fatal); 194 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", 195 &error_fatal); 196 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); 197 198 /* max 2GB ram */ 199 if (ram_size > 0x80000000) { 200 ram_size = 0x80000000; 201 } 202 203 /* DDR remapped to address zero. */ 204 memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", 205 ram_size); 206 memory_region_add_subregion(address_space_mem, 0, ext_ram); 207 208 /* 256K of on-chip memory */ 209 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, 210 &error_fatal); 211 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 212 213 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 214 215 /* AMD */ 216 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, 217 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 218 FLASH_SECTOR_SIZE, 219 FLASH_SIZE/FLASH_SECTOR_SIZE, 1, 220 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 221 0); 222 223 dev = qdev_create(NULL, "xilinx,zynq_slcr"); 224 qdev_init_nofail(dev); 225 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); 226 227 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 228 qdev_prop_set_uint32(dev, "num-cpu", 1); 229 qdev_init_nofail(dev); 230 busdev = SYS_BUS_DEVICE(dev); 231 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 232 sysbus_connect_irq(busdev, 0, 233 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 234 235 for (n = 0; n < 64; n++) { 236 pic[n] = qdev_get_gpio_in(dev, n); 237 } 238 239 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 240 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 241 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 242 243 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); 244 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); 245 246 cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hds[0]); 247 cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hds[1]); 248 249 sysbus_create_varargs("cadence_ttc", 0xF8001000, 250 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 251 sysbus_create_varargs("cadence_ttc", 0xF8002000, 252 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 253 254 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 255 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 256 257 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); 258 qdev_init_nofail(dev); 259 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); 260 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); 261 262 di = drive_get_next(IF_SD); 263 blk = di ? blk_by_legacy_dinfo(di) : NULL; 264 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 265 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 266 object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 267 268 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); 269 qdev_init_nofail(dev); 270 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); 271 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); 272 273 di = drive_get_next(IF_SD); 274 blk = di ? blk_by_legacy_dinfo(di) : NULL; 275 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 276 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 277 object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 278 279 dev = qdev_create(NULL, TYPE_ZYNQ_XADC); 280 qdev_init_nofail(dev); 281 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 282 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 283 284 dev = qdev_create(NULL, "pl330"); 285 qdev_prop_set_uint8(dev, "num_chnls", 8); 286 qdev_prop_set_uint8(dev, "num_periph_req", 4); 287 qdev_prop_set_uint8(dev, "num_events", 16); 288 289 qdev_prop_set_uint8(dev, "data_width", 64); 290 qdev_prop_set_uint8(dev, "wr_cap", 8); 291 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 292 qdev_prop_set_uint8(dev, "rd_cap", 8); 293 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 294 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 295 296 qdev_init_nofail(dev); 297 busdev = SYS_BUS_DEVICE(dev); 298 sysbus_mmio_map(busdev, 0, 0xF8003000); 299 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 300 for (n = 0; n < 8; ++n) { /* event irqs */ 301 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 302 } 303 304 dev = qdev_create(NULL, "xlnx.ps7-dev-cfg"); 305 qdev_init_nofail(dev); 306 busdev = SYS_BUS_DEVICE(dev); 307 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 308 sysbus_mmio_map(busdev, 0, 0xF8007000); 309 310 zynq_binfo.ram_size = ram_size; 311 zynq_binfo.kernel_filename = kernel_filename; 312 zynq_binfo.kernel_cmdline = kernel_cmdline; 313 zynq_binfo.initrd_filename = initrd_filename; 314 zynq_binfo.nb_cpus = 1; 315 zynq_binfo.board_id = 0xd32; 316 zynq_binfo.loader_start = 0; 317 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 318 zynq_binfo.write_board_setup = zynq_write_board_setup; 319 320 arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); 321 } 322 323 static void zynq_machine_init(MachineClass *mc) 324 { 325 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 326 mc->init = zynq_init; 327 mc->max_cpus = 1; 328 mc->no_sdcard = 1; 329 mc->ignore_memory_transaction_failures = true; 330 } 331 332 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) 333