1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "cpu.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/boot.h" 24 #include "net/net.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/block/flash.h" 29 #include "hw/loader.h" 30 #include "hw/misc/zynq-xadc.h" 31 #include "hw/ssi/ssi.h" 32 #include "hw/usb/chipidea.h" 33 #include "qemu/error-report.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/char/cadence_uart.h" 36 #include "hw/net/cadence_gem.h" 37 #include "hw/cpu/a9mpcore.h" 38 #include "hw/qdev-clock.h" 39 #include "sysemu/reset.h" 40 #include "qom/object.h" 41 42 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") 43 OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) 44 45 /* board base frequency: 33.333333 MHz */ 46 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) 47 48 #define NUM_SPI_FLASHES 4 49 #define NUM_QSPI_FLASHES 2 50 #define NUM_QSPI_BUSSES 2 51 52 #define FLASH_SIZE (64 * 1024 * 1024) 53 #define FLASH_SECTOR_SIZE (128 * 1024) 54 55 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 56 57 #define MPCORE_PERIPHBASE 0xF8F00000 58 #define ZYNQ_BOARD_MIDR 0x413FC090 59 60 static const int dma_irqs[8] = { 61 46, 47, 48, 49, 72, 73, 74, 75 62 }; 63 64 #define BOARD_SETUP_ADDR 0x100 65 66 #define SLCR_LOCK_OFFSET 0x004 67 #define SLCR_UNLOCK_OFFSET 0x008 68 #define SLCR_ARM_PLL_OFFSET 0x100 69 70 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 71 #define SLCR_XILINX_LOCK_KEY 0x767b 72 73 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ 74 75 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 76 extract32((x), 12, 4) << 16) 77 78 /* Write immediate val to address r0 + addr. r0 should contain base offset 79 * of the SLCR block. Clobbers r1. 80 */ 81 82 #define SLCR_WRITE(addr, val) \ 83 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 84 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 85 0xe5801000 + (addr) 86 87 struct ZynqMachineState { 88 MachineState parent; 89 Clock *ps_clk; 90 }; 91 92 static void zynq_write_board_setup(ARMCPU *cpu, 93 const struct arm_boot_info *info) 94 { 95 int n; 96 uint32_t board_setup_blob[] = { 97 0xe3a004f8, /* mov r0, #0xf8000000 */ 98 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 99 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 100 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 101 0xe12fff1e, /* bx lr */ 102 }; 103 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 104 board_setup_blob[n] = tswap32(board_setup_blob[n]); 105 } 106 rom_add_blob_fixed("board-setup", board_setup_blob, 107 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 108 } 109 110 static struct arm_boot_info zynq_binfo = {}; 111 112 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 113 { 114 DeviceState *dev; 115 SysBusDevice *s; 116 117 dev = qdev_new(TYPE_CADENCE_GEM); 118 if (nd->used) { 119 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 120 qdev_set_nic_properties(dev, nd); 121 } 122 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); 123 s = SYS_BUS_DEVICE(dev); 124 sysbus_realize_and_unref(s, &error_fatal); 125 sysbus_mmio_map(s, 0, base); 126 sysbus_connect_irq(s, 0, irq); 127 } 128 129 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 130 bool is_qspi) 131 { 132 DeviceState *dev; 133 SysBusDevice *busdev; 134 SSIBus *spi; 135 DeviceState *flash_dev; 136 int i, j; 137 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 138 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 139 140 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 141 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 142 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 143 qdev_prop_set_uint8(dev, "num-busses", num_busses); 144 busdev = SYS_BUS_DEVICE(dev); 145 sysbus_realize_and_unref(busdev, &error_fatal); 146 sysbus_mmio_map(busdev, 0, base_addr); 147 if (is_qspi) { 148 sysbus_mmio_map(busdev, 1, 0xFC000000); 149 } 150 sysbus_connect_irq(busdev, 0, irq); 151 152 for (i = 0; i < num_busses; ++i) { 153 char bus_name[16]; 154 qemu_irq cs_line; 155 156 snprintf(bus_name, 16, "spi%d", i); 157 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 158 159 for (j = 0; j < num_ss; ++j) { 160 DriveInfo *dinfo = drive_get_next(IF_MTD); 161 flash_dev = qdev_new("n25q128"); 162 if (dinfo) { 163 qdev_prop_set_drive_err(flash_dev, "drive", 164 blk_by_legacy_dinfo(dinfo), 165 &error_fatal); 166 } 167 qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal); 168 169 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 170 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 171 } 172 } 173 174 } 175 176 static void zynq_init(MachineState *machine) 177 { 178 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); 179 ARMCPU *cpu; 180 MemoryRegion *address_space_mem = get_system_memory(); 181 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 182 DeviceState *dev, *slcr; 183 SysBusDevice *busdev; 184 qemu_irq pic[64]; 185 int n; 186 187 /* max 2GB ram */ 188 if (machine->ram_size > 2 * GiB) { 189 error_report("RAM size more than 2 GiB is not supported"); 190 exit(EXIT_FAILURE); 191 } 192 193 cpu = ARM_CPU(object_new(machine->cpu_type)); 194 195 /* By default A9 CPUs have EL3 enabled. This board does not 196 * currently support EL3 so the CPU EL3 property is disabled before 197 * realization. 198 */ 199 if (object_property_find(OBJECT(cpu), "has_el3")) { 200 object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal); 201 } 202 203 object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR, 204 &error_fatal); 205 object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE, 206 &error_fatal); 207 qdev_realize(DEVICE(cpu), NULL, &error_fatal); 208 209 /* DDR remapped to address zero. */ 210 memory_region_add_subregion(address_space_mem, 0, machine->ram); 211 212 /* 256K of on-chip memory */ 213 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, 214 &error_fatal); 215 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 216 217 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 218 219 /* AMD */ 220 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, 221 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 222 FLASH_SECTOR_SIZE, 1, 223 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 224 0); 225 226 /* Create the main clock source, and feed slcr with it */ 227 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); 228 object_property_add_child(OBJECT(zynq_machine), "ps_clk", 229 OBJECT(zynq_machine->ps_clk)); 230 object_unref(OBJECT(zynq_machine->ps_clk)); 231 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); 232 233 /* Create slcr, keep a pointer to connect clocks */ 234 slcr = qdev_new("xilinx,zynq_slcr"); 235 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); 236 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); 237 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); 238 239 dev = qdev_new(TYPE_A9MPCORE_PRIV); 240 qdev_prop_set_uint32(dev, "num-cpu", 1); 241 busdev = SYS_BUS_DEVICE(dev); 242 sysbus_realize_and_unref(busdev, &error_fatal); 243 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 244 sysbus_connect_irq(busdev, 0, 245 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 246 247 for (n = 0; n < 64; n++) { 248 pic[n] = qdev_get_gpio_in(dev, n); 249 } 250 251 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 252 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 253 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 254 255 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); 256 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); 257 258 dev = qdev_new(TYPE_CADENCE_UART); 259 busdev = SYS_BUS_DEVICE(dev); 260 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 261 qdev_connect_clock_in(dev, "refclk", 262 qdev_get_clock_out(slcr, "uart0_ref_clk")); 263 sysbus_realize_and_unref(busdev, &error_fatal); 264 sysbus_mmio_map(busdev, 0, 0xE0000000); 265 sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); 266 dev = qdev_new(TYPE_CADENCE_UART); 267 busdev = SYS_BUS_DEVICE(dev); 268 qdev_prop_set_chr(dev, "chardev", serial_hd(1)); 269 qdev_connect_clock_in(dev, "refclk", 270 qdev_get_clock_out(slcr, "uart1_ref_clk")); 271 sysbus_realize_and_unref(busdev, &error_fatal); 272 sysbus_mmio_map(busdev, 0, 0xE0001000); 273 sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); 274 275 sysbus_create_varargs("cadence_ttc", 0xF8001000, 276 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 277 sysbus_create_varargs("cadence_ttc", 0xF8002000, 278 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 279 280 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 281 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 282 283 for (n = 0; n < 2; n++) { 284 int hci_irq = n ? 79 : 56; 285 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; 286 DriveInfo *di; 287 BlockBackend *blk; 288 DeviceState *carddev; 289 290 /* Compatible with: 291 * - SD Host Controller Specification Version 2.0 Part A2 292 * - SDIO Specification Version 2.0 293 * - MMC Specification Version 3.31 294 */ 295 dev = qdev_new(TYPE_SYSBUS_SDHCI); 296 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 297 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); 298 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 299 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); 300 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); 301 302 di = drive_get_next(IF_SD); 303 blk = di ? blk_by_legacy_dinfo(di) : NULL; 304 carddev = qdev_new(TYPE_SD_CARD); 305 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 306 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 307 &error_fatal); 308 } 309 310 dev = qdev_new(TYPE_ZYNQ_XADC); 311 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 312 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 313 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 314 315 dev = qdev_new("pl330"); 316 qdev_prop_set_uint8(dev, "num_chnls", 8); 317 qdev_prop_set_uint8(dev, "num_periph_req", 4); 318 qdev_prop_set_uint8(dev, "num_events", 16); 319 320 qdev_prop_set_uint8(dev, "data_width", 64); 321 qdev_prop_set_uint8(dev, "wr_cap", 8); 322 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 323 qdev_prop_set_uint8(dev, "rd_cap", 8); 324 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 325 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 326 327 busdev = SYS_BUS_DEVICE(dev); 328 sysbus_realize_and_unref(busdev, &error_fatal); 329 sysbus_mmio_map(busdev, 0, 0xF8003000); 330 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 331 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ 332 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 333 } 334 335 dev = qdev_new("xlnx.ps7-dev-cfg"); 336 busdev = SYS_BUS_DEVICE(dev); 337 sysbus_realize_and_unref(busdev, &error_fatal); 338 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 339 sysbus_mmio_map(busdev, 0, 0xF8007000); 340 341 zynq_binfo.ram_size = machine->ram_size; 342 zynq_binfo.nb_cpus = 1; 343 zynq_binfo.board_id = 0xd32; 344 zynq_binfo.loader_start = 0; 345 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 346 zynq_binfo.write_board_setup = zynq_write_board_setup; 347 348 arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); 349 } 350 351 static void zynq_machine_class_init(ObjectClass *oc, void *data) 352 { 353 MachineClass *mc = MACHINE_CLASS(oc); 354 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 355 mc->init = zynq_init; 356 mc->max_cpus = 1; 357 mc->no_sdcard = 1; 358 mc->ignore_memory_transaction_failures = true; 359 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 360 mc->default_ram_id = "zynq.ext_ram"; 361 } 362 363 static const TypeInfo zynq_machine_type = { 364 .name = TYPE_ZYNQ_MACHINE, 365 .parent = TYPE_MACHINE, 366 .class_init = zynq_machine_class_init, 367 .instance_size = sizeof(ZynqMachineState), 368 }; 369 370 static void zynq_machine_register_types(void) 371 { 372 type_register_static(&zynq_machine_type); 373 } 374 375 type_init(zynq_machine_register_types) 376