1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "cpu.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/boot.h" 24 #include "net/net.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/block/flash.h" 29 #include "hw/loader.h" 30 #include "hw/misc/zynq-xadc.h" 31 #include "hw/ssi/ssi.h" 32 #include "hw/usb/chipidea.h" 33 #include "qemu/error-report.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/char/cadence_uart.h" 36 #include "hw/net/cadence_gem.h" 37 #include "hw/cpu/a9mpcore.h" 38 39 #define NUM_SPI_FLASHES 4 40 #define NUM_QSPI_FLASHES 2 41 #define NUM_QSPI_BUSSES 2 42 43 #define FLASH_SIZE (64 * 1024 * 1024) 44 #define FLASH_SECTOR_SIZE (128 * 1024) 45 46 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 47 48 #define MPCORE_PERIPHBASE 0xF8F00000 49 #define ZYNQ_BOARD_MIDR 0x413FC090 50 51 static const int dma_irqs[8] = { 52 46, 47, 48, 49, 72, 73, 74, 75 53 }; 54 55 #define BOARD_SETUP_ADDR 0x100 56 57 #define SLCR_LOCK_OFFSET 0x004 58 #define SLCR_UNLOCK_OFFSET 0x008 59 #define SLCR_ARM_PLL_OFFSET 0x100 60 61 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 62 #define SLCR_XILINX_LOCK_KEY 0x767b 63 64 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ 65 66 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 67 extract32((x), 12, 4) << 16) 68 69 /* Write immediate val to address r0 + addr. r0 should contain base offset 70 * of the SLCR block. Clobbers r1. 71 */ 72 73 #define SLCR_WRITE(addr, val) \ 74 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 75 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 76 0xe5801000 + (addr) 77 78 static void zynq_write_board_setup(ARMCPU *cpu, 79 const struct arm_boot_info *info) 80 { 81 int n; 82 uint32_t board_setup_blob[] = { 83 0xe3a004f8, /* mov r0, #0xf8000000 */ 84 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 85 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 86 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 87 0xe12fff1e, /* bx lr */ 88 }; 89 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 90 board_setup_blob[n] = tswap32(board_setup_blob[n]); 91 } 92 rom_add_blob_fixed("board-setup", board_setup_blob, 93 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 94 } 95 96 static struct arm_boot_info zynq_binfo = {}; 97 98 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 99 { 100 DeviceState *dev; 101 SysBusDevice *s; 102 103 dev = qdev_create(NULL, TYPE_CADENCE_GEM); 104 if (nd->used) { 105 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 106 qdev_set_nic_properties(dev, nd); 107 } 108 qdev_init_nofail(dev); 109 s = SYS_BUS_DEVICE(dev); 110 sysbus_mmio_map(s, 0, base); 111 sysbus_connect_irq(s, 0, irq); 112 } 113 114 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 115 bool is_qspi) 116 { 117 DeviceState *dev; 118 SysBusDevice *busdev; 119 SSIBus *spi; 120 DeviceState *flash_dev; 121 int i, j; 122 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 123 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 124 125 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 126 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 127 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 128 qdev_prop_set_uint8(dev, "num-busses", num_busses); 129 qdev_init_nofail(dev); 130 busdev = SYS_BUS_DEVICE(dev); 131 sysbus_mmio_map(busdev, 0, base_addr); 132 if (is_qspi) { 133 sysbus_mmio_map(busdev, 1, 0xFC000000); 134 } 135 sysbus_connect_irq(busdev, 0, irq); 136 137 for (i = 0; i < num_busses; ++i) { 138 char bus_name[16]; 139 qemu_irq cs_line; 140 141 snprintf(bus_name, 16, "spi%d", i); 142 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 143 144 for (j = 0; j < num_ss; ++j) { 145 DriveInfo *dinfo = drive_get_next(IF_MTD); 146 flash_dev = ssi_create_slave_no_init(spi, "n25q128"); 147 if (dinfo) { 148 qdev_prop_set_drive(flash_dev, "drive", 149 blk_by_legacy_dinfo(dinfo), &error_fatal); 150 } 151 qdev_init_nofail(flash_dev); 152 153 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 154 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 155 } 156 } 157 158 } 159 160 static void zynq_init(MachineState *machine) 161 { 162 ARMCPU *cpu; 163 MemoryRegion *address_space_mem = get_system_memory(); 164 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 165 DeviceState *dev; 166 SysBusDevice *busdev; 167 qemu_irq pic[64]; 168 int n; 169 170 /* max 2GB ram */ 171 if (machine->ram_size > 2 * GiB) { 172 error_report("RAM size more than 2 GiB is not supported"); 173 exit(EXIT_FAILURE); 174 } 175 176 cpu = ARM_CPU(object_new(machine->cpu_type)); 177 178 /* By default A9 CPUs have EL3 enabled. This board does not 179 * currently support EL3 so the CPU EL3 property is disabled before 180 * realization. 181 */ 182 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { 183 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); 184 } 185 186 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", 187 &error_fatal); 188 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", 189 &error_fatal); 190 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); 191 192 /* DDR remapped to address zero. */ 193 memory_region_add_subregion(address_space_mem, 0, machine->ram); 194 195 /* 256K of on-chip memory */ 196 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, 197 &error_fatal); 198 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 199 200 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 201 202 /* AMD */ 203 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, 204 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 205 FLASH_SECTOR_SIZE, 1, 206 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 207 0); 208 209 dev = qdev_create(NULL, "xilinx,zynq_slcr"); 210 qdev_init_nofail(dev); 211 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); 212 213 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 214 qdev_prop_set_uint32(dev, "num-cpu", 1); 215 qdev_init_nofail(dev); 216 busdev = SYS_BUS_DEVICE(dev); 217 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 218 sysbus_connect_irq(busdev, 0, 219 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 220 221 for (n = 0; n < 64; n++) { 222 pic[n] = qdev_get_gpio_in(dev, n); 223 } 224 225 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 226 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 227 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 228 229 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); 230 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); 231 232 cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); 233 cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); 234 235 sysbus_create_varargs("cadence_ttc", 0xF8001000, 236 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 237 sysbus_create_varargs("cadence_ttc", 0xF8002000, 238 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 239 240 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 241 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 242 243 for (n = 0; n < 2; n++) { 244 int hci_irq = n ? 79 : 56; 245 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; 246 DriveInfo *di; 247 BlockBackend *blk; 248 DeviceState *carddev; 249 250 /* Compatible with: 251 * - SD Host Controller Specification Version 2.0 Part A2 252 * - SDIO Specification Version 2.0 253 * - MMC Specification Version 3.31 254 */ 255 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); 256 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 257 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); 258 qdev_init_nofail(dev); 259 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); 260 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); 261 262 di = drive_get_next(IF_SD); 263 blk = di ? blk_by_legacy_dinfo(di) : NULL; 264 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 265 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 266 object_property_set_bool(OBJECT(carddev), true, "realized", 267 &error_fatal); 268 } 269 270 dev = qdev_create(NULL, TYPE_ZYNQ_XADC); 271 qdev_init_nofail(dev); 272 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 273 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 274 275 dev = qdev_create(NULL, "pl330"); 276 qdev_prop_set_uint8(dev, "num_chnls", 8); 277 qdev_prop_set_uint8(dev, "num_periph_req", 4); 278 qdev_prop_set_uint8(dev, "num_events", 16); 279 280 qdev_prop_set_uint8(dev, "data_width", 64); 281 qdev_prop_set_uint8(dev, "wr_cap", 8); 282 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 283 qdev_prop_set_uint8(dev, "rd_cap", 8); 284 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 285 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 286 287 qdev_init_nofail(dev); 288 busdev = SYS_BUS_DEVICE(dev); 289 sysbus_mmio_map(busdev, 0, 0xF8003000); 290 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 291 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ 292 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 293 } 294 295 dev = qdev_create(NULL, "xlnx.ps7-dev-cfg"); 296 qdev_init_nofail(dev); 297 busdev = SYS_BUS_DEVICE(dev); 298 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 299 sysbus_mmio_map(busdev, 0, 0xF8007000); 300 301 zynq_binfo.ram_size = machine->ram_size; 302 zynq_binfo.nb_cpus = 1; 303 zynq_binfo.board_id = 0xd32; 304 zynq_binfo.loader_start = 0; 305 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 306 zynq_binfo.write_board_setup = zynq_write_board_setup; 307 308 arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); 309 } 310 311 static void zynq_machine_init(MachineClass *mc) 312 { 313 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 314 mc->init = zynq_init; 315 mc->max_cpus = 1; 316 mc->no_sdcard = 1; 317 mc->ignore_memory_transaction_failures = true; 318 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 319 mc->default_ram_id = "zynq.ext_ram"; 320 } 321 322 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) 323