1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "cpu.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/boot.h" 24 #include "net/net.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/block/flash.h" 29 #include "hw/loader.h" 30 #include "hw/misc/zynq-xadc.h" 31 #include "hw/ssi/ssi.h" 32 #include "hw/usb/chipidea.h" 33 #include "qemu/error-report.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/char/cadence_uart.h" 36 #include "hw/net/cadence_gem.h" 37 #include "hw/cpu/a9mpcore.h" 38 #include "hw/qdev-clock.h" 39 #include "sysemu/reset.h" 40 41 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") 42 #define ZYNQ_MACHINE(obj) \ 43 OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE) 44 45 /* board base frequency: 33.333333 MHz */ 46 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) 47 48 #define NUM_SPI_FLASHES 4 49 #define NUM_QSPI_FLASHES 2 50 #define NUM_QSPI_BUSSES 2 51 52 #define FLASH_SIZE (64 * 1024 * 1024) 53 #define FLASH_SECTOR_SIZE (128 * 1024) 54 55 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 56 57 #define MPCORE_PERIPHBASE 0xF8F00000 58 #define ZYNQ_BOARD_MIDR 0x413FC090 59 60 static const int dma_irqs[8] = { 61 46, 47, 48, 49, 72, 73, 74, 75 62 }; 63 64 #define BOARD_SETUP_ADDR 0x100 65 66 #define SLCR_LOCK_OFFSET 0x004 67 #define SLCR_UNLOCK_OFFSET 0x008 68 #define SLCR_ARM_PLL_OFFSET 0x100 69 70 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 71 #define SLCR_XILINX_LOCK_KEY 0x767b 72 73 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ 74 75 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 76 extract32((x), 12, 4) << 16) 77 78 /* Write immediate val to address r0 + addr. r0 should contain base offset 79 * of the SLCR block. Clobbers r1. 80 */ 81 82 #define SLCR_WRITE(addr, val) \ 83 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 84 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 85 0xe5801000 + (addr) 86 87 typedef struct ZynqMachineState { 88 MachineState parent; 89 Clock *ps_clk; 90 } ZynqMachineState; 91 92 static void zynq_write_board_setup(ARMCPU *cpu, 93 const struct arm_boot_info *info) 94 { 95 int n; 96 uint32_t board_setup_blob[] = { 97 0xe3a004f8, /* mov r0, #0xf8000000 */ 98 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 99 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 100 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 101 0xe12fff1e, /* bx lr */ 102 }; 103 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 104 board_setup_blob[n] = tswap32(board_setup_blob[n]); 105 } 106 rom_add_blob_fixed("board-setup", board_setup_blob, 107 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 108 } 109 110 static struct arm_boot_info zynq_binfo = {}; 111 112 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 113 { 114 DeviceState *dev; 115 SysBusDevice *s; 116 117 dev = qdev_create(NULL, TYPE_CADENCE_GEM); 118 if (nd->used) { 119 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 120 qdev_set_nic_properties(dev, nd); 121 } 122 qdev_init_nofail(dev); 123 s = SYS_BUS_DEVICE(dev); 124 sysbus_mmio_map(s, 0, base); 125 sysbus_connect_irq(s, 0, irq); 126 } 127 128 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 129 bool is_qspi) 130 { 131 DeviceState *dev; 132 SysBusDevice *busdev; 133 SSIBus *spi; 134 DeviceState *flash_dev; 135 int i, j; 136 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 137 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 138 139 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 140 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 141 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 142 qdev_prop_set_uint8(dev, "num-busses", num_busses); 143 qdev_init_nofail(dev); 144 busdev = SYS_BUS_DEVICE(dev); 145 sysbus_mmio_map(busdev, 0, base_addr); 146 if (is_qspi) { 147 sysbus_mmio_map(busdev, 1, 0xFC000000); 148 } 149 sysbus_connect_irq(busdev, 0, irq); 150 151 for (i = 0; i < num_busses; ++i) { 152 char bus_name[16]; 153 qemu_irq cs_line; 154 155 snprintf(bus_name, 16, "spi%d", i); 156 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 157 158 for (j = 0; j < num_ss; ++j) { 159 DriveInfo *dinfo = drive_get_next(IF_MTD); 160 flash_dev = ssi_create_slave_no_init(spi, "n25q128"); 161 if (dinfo) { 162 qdev_prop_set_drive(flash_dev, "drive", 163 blk_by_legacy_dinfo(dinfo), &error_fatal); 164 } 165 qdev_init_nofail(flash_dev); 166 167 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 168 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 169 } 170 } 171 172 } 173 174 static void zynq_init(MachineState *machine) 175 { 176 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); 177 ARMCPU *cpu; 178 MemoryRegion *address_space_mem = get_system_memory(); 179 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 180 DeviceState *dev, *slcr; 181 SysBusDevice *busdev; 182 qemu_irq pic[64]; 183 int n; 184 185 /* max 2GB ram */ 186 if (machine->ram_size > 2 * GiB) { 187 error_report("RAM size more than 2 GiB is not supported"); 188 exit(EXIT_FAILURE); 189 } 190 191 cpu = ARM_CPU(object_new(machine->cpu_type)); 192 193 /* By default A9 CPUs have EL3 enabled. This board does not 194 * currently support EL3 so the CPU EL3 property is disabled before 195 * realization. 196 */ 197 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { 198 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); 199 } 200 201 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", 202 &error_fatal); 203 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", 204 &error_fatal); 205 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); 206 207 /* DDR remapped to address zero. */ 208 memory_region_add_subregion(address_space_mem, 0, machine->ram); 209 210 /* 256K of on-chip memory */ 211 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, 212 &error_fatal); 213 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 214 215 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 216 217 /* AMD */ 218 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, 219 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 220 FLASH_SECTOR_SIZE, 1, 221 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 222 0); 223 224 /* Create slcr, keep a pointer to connect clocks */ 225 slcr = qdev_create(NULL, "xilinx,zynq_slcr"); 226 qdev_init_nofail(slcr); 227 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); 228 229 /* Create the main clock source, and feed slcr with it */ 230 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); 231 object_property_add_child(OBJECT(zynq_machine), "ps_clk", 232 OBJECT(zynq_machine->ps_clk)); 233 object_unref(OBJECT(zynq_machine->ps_clk)); 234 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); 235 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); 236 237 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 238 qdev_prop_set_uint32(dev, "num-cpu", 1); 239 qdev_init_nofail(dev); 240 busdev = SYS_BUS_DEVICE(dev); 241 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 242 sysbus_connect_irq(busdev, 0, 243 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 244 245 for (n = 0; n < 64; n++) { 246 pic[n] = qdev_get_gpio_in(dev, n); 247 } 248 249 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 250 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 251 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 252 253 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); 254 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); 255 256 dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); 257 qdev_connect_clock_in(dev, "refclk", 258 qdev_get_clock_out(slcr, "uart0_ref_clk")); 259 dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); 260 qdev_connect_clock_in(dev, "refclk", 261 qdev_get_clock_out(slcr, "uart1_ref_clk")); 262 263 sysbus_create_varargs("cadence_ttc", 0xF8001000, 264 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 265 sysbus_create_varargs("cadence_ttc", 0xF8002000, 266 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 267 268 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 269 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 270 271 for (n = 0; n < 2; n++) { 272 int hci_irq = n ? 79 : 56; 273 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; 274 DriveInfo *di; 275 BlockBackend *blk; 276 DeviceState *carddev; 277 278 /* Compatible with: 279 * - SD Host Controller Specification Version 2.0 Part A2 280 * - SDIO Specification Version 2.0 281 * - MMC Specification Version 3.31 282 */ 283 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); 284 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 285 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); 286 qdev_init_nofail(dev); 287 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); 288 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); 289 290 di = drive_get_next(IF_SD); 291 blk = di ? blk_by_legacy_dinfo(di) : NULL; 292 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 293 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 294 object_property_set_bool(OBJECT(carddev), true, "realized", 295 &error_fatal); 296 } 297 298 dev = qdev_create(NULL, TYPE_ZYNQ_XADC); 299 qdev_init_nofail(dev); 300 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 301 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 302 303 dev = qdev_create(NULL, "pl330"); 304 qdev_prop_set_uint8(dev, "num_chnls", 8); 305 qdev_prop_set_uint8(dev, "num_periph_req", 4); 306 qdev_prop_set_uint8(dev, "num_events", 16); 307 308 qdev_prop_set_uint8(dev, "data_width", 64); 309 qdev_prop_set_uint8(dev, "wr_cap", 8); 310 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 311 qdev_prop_set_uint8(dev, "rd_cap", 8); 312 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 313 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 314 315 qdev_init_nofail(dev); 316 busdev = SYS_BUS_DEVICE(dev); 317 sysbus_mmio_map(busdev, 0, 0xF8003000); 318 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 319 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ 320 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 321 } 322 323 dev = qdev_create(NULL, "xlnx.ps7-dev-cfg"); 324 qdev_init_nofail(dev); 325 busdev = SYS_BUS_DEVICE(dev); 326 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 327 sysbus_mmio_map(busdev, 0, 0xF8007000); 328 329 zynq_binfo.ram_size = machine->ram_size; 330 zynq_binfo.nb_cpus = 1; 331 zynq_binfo.board_id = 0xd32; 332 zynq_binfo.loader_start = 0; 333 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 334 zynq_binfo.write_board_setup = zynq_write_board_setup; 335 336 arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); 337 } 338 339 static void zynq_machine_class_init(ObjectClass *oc, void *data) 340 { 341 MachineClass *mc = MACHINE_CLASS(oc); 342 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 343 mc->init = zynq_init; 344 mc->max_cpus = 1; 345 mc->no_sdcard = 1; 346 mc->ignore_memory_transaction_failures = true; 347 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 348 mc->default_ram_id = "zynq.ext_ram"; 349 } 350 351 static const TypeInfo zynq_machine_type = { 352 .name = TYPE_ZYNQ_MACHINE, 353 .parent = TYPE_MACHINE, 354 .class_init = zynq_machine_class_init, 355 .instance_size = sizeof(ZynqMachineState), 356 }; 357 358 static void zynq_machine_register_types(void) 359 { 360 type_register_static(&zynq_machine_type); 361 } 362 363 type_init(zynq_machine_register_types) 364