1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "hw/sysbus.h" 19 #include "hw/arm/arm.h" 20 #include "net/net.h" 21 #include "exec/address-spaces.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/boards.h" 24 #include "hw/block/flash.h" 25 #include "sysemu/blockdev.h" 26 #include "hw/loader.h" 27 #include "hw/ssi.h" 28 #include "qemu/error-report.h" 29 30 #define NUM_SPI_FLASHES 4 31 #define NUM_QSPI_FLASHES 2 32 #define NUM_QSPI_BUSSES 2 33 34 #define FLASH_SIZE (64 * 1024 * 1024) 35 #define FLASH_SECTOR_SIZE (128 * 1024) 36 37 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 38 39 #define MPCORE_PERIPHBASE 0xF8F00000 40 41 static const int dma_irqs[8] = { 42 46, 47, 48, 49, 72, 73, 74, 75 43 }; 44 45 static struct arm_boot_info zynq_binfo = {}; 46 47 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 48 { 49 DeviceState *dev; 50 SysBusDevice *s; 51 52 dev = qdev_create(NULL, "cadence_gem"); 53 if (nd->used) { 54 qemu_check_nic_model(nd, "cadence_gem"); 55 qdev_set_nic_properties(dev, nd); 56 } 57 qdev_init_nofail(dev); 58 s = SYS_BUS_DEVICE(dev); 59 sysbus_mmio_map(s, 0, base); 60 sysbus_connect_irq(s, 0, irq); 61 } 62 63 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 64 bool is_qspi) 65 { 66 DeviceState *dev; 67 SysBusDevice *busdev; 68 SSIBus *spi; 69 DeviceState *flash_dev; 70 int i, j; 71 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 72 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 73 74 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 75 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 76 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 77 qdev_prop_set_uint8(dev, "num-busses", num_busses); 78 qdev_init_nofail(dev); 79 busdev = SYS_BUS_DEVICE(dev); 80 sysbus_mmio_map(busdev, 0, base_addr); 81 if (is_qspi) { 82 sysbus_mmio_map(busdev, 1, 0xFC000000); 83 } 84 sysbus_connect_irq(busdev, 0, irq); 85 86 for (i = 0; i < num_busses; ++i) { 87 char bus_name[16]; 88 qemu_irq cs_line; 89 90 snprintf(bus_name, 16, "spi%d", i); 91 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 92 93 for (j = 0; j < num_ss; ++j) { 94 flash_dev = ssi_create_slave(spi, "n25q128"); 95 96 cs_line = qdev_get_gpio_in(flash_dev, 0); 97 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 98 } 99 } 100 101 } 102 103 static void zynq_init(QEMUMachineInitArgs *args) 104 { 105 ram_addr_t ram_size = args->ram_size; 106 const char *cpu_model = args->cpu_model; 107 const char *kernel_filename = args->kernel_filename; 108 const char *kernel_cmdline = args->kernel_cmdline; 109 const char *initrd_filename = args->initrd_filename; 110 ObjectClass *cpu_oc; 111 ARMCPU *cpu; 112 MemoryRegion *address_space_mem = get_system_memory(); 113 MemoryRegion *ext_ram = g_new(MemoryRegion, 1); 114 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 115 DeviceState *dev; 116 SysBusDevice *busdev; 117 qemu_irq pic[64]; 118 Error *err = NULL; 119 int n; 120 121 if (!cpu_model) { 122 cpu_model = "cortex-a9"; 123 } 124 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 125 126 cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); 127 128 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err); 129 if (err) { 130 error_report("%s", error_get_pretty(err)); 131 exit(1); 132 } 133 object_property_set_bool(OBJECT(cpu), true, "realized", &err); 134 if (err) { 135 error_report("%s", error_get_pretty(err)); 136 exit(1); 137 } 138 139 /* max 2GB ram */ 140 if (ram_size > 0x80000000) { 141 ram_size = 0x80000000; 142 } 143 144 /* DDR remapped to address zero. */ 145 memory_region_init_ram(ext_ram, NULL, "zynq.ext_ram", ram_size); 146 vmstate_register_ram_global(ext_ram); 147 memory_region_add_subregion(address_space_mem, 0, ext_ram); 148 149 /* 256K of on-chip memory */ 150 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10); 151 vmstate_register_ram_global(ocm_ram); 152 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 153 154 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 155 156 /* AMD */ 157 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, 158 dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE, 159 FLASH_SIZE/FLASH_SECTOR_SIZE, 1, 160 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 161 0); 162 163 dev = qdev_create(NULL, "xilinx,zynq_slcr"); 164 qdev_init_nofail(dev); 165 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); 166 167 dev = qdev_create(NULL, "a9mpcore_priv"); 168 qdev_prop_set_uint32(dev, "num-cpu", 1); 169 qdev_init_nofail(dev); 170 busdev = SYS_BUS_DEVICE(dev); 171 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 172 sysbus_connect_irq(busdev, 0, 173 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 174 175 for (n = 0; n < 64; n++) { 176 pic[n] = qdev_get_gpio_in(dev, n); 177 } 178 179 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 180 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 181 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 182 183 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); 184 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); 185 186 sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); 187 sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]); 188 189 sysbus_create_varargs("cadence_ttc", 0xF8001000, 190 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 191 sysbus_create_varargs("cadence_ttc", 0xF8002000, 192 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 193 194 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 195 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 196 197 dev = qdev_create(NULL, "generic-sdhci"); 198 qdev_init_nofail(dev); 199 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); 200 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); 201 202 dev = qdev_create(NULL, "generic-sdhci"); 203 qdev_init_nofail(dev); 204 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); 205 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); 206 207 dev = qdev_create(NULL, "pl330"); 208 qdev_prop_set_uint8(dev, "num_chnls", 8); 209 qdev_prop_set_uint8(dev, "num_periph_req", 4); 210 qdev_prop_set_uint8(dev, "num_events", 16); 211 212 qdev_prop_set_uint8(dev, "data_width", 64); 213 qdev_prop_set_uint8(dev, "wr_cap", 8); 214 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 215 qdev_prop_set_uint8(dev, "rd_cap", 8); 216 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 217 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 218 219 qdev_init_nofail(dev); 220 busdev = SYS_BUS_DEVICE(dev); 221 sysbus_mmio_map(busdev, 0, 0xF8003000); 222 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 223 for (n = 0; n < 8; ++n) { /* event irqs */ 224 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 225 } 226 227 zynq_binfo.ram_size = ram_size; 228 zynq_binfo.kernel_filename = kernel_filename; 229 zynq_binfo.kernel_cmdline = kernel_cmdline; 230 zynq_binfo.initrd_filename = initrd_filename; 231 zynq_binfo.nb_cpus = 1; 232 zynq_binfo.board_id = 0xd32; 233 zynq_binfo.loader_start = 0; 234 arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); 235 } 236 237 static QEMUMachine zynq_machine = { 238 .name = "xilinx-zynq-a9", 239 .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9", 240 .init = zynq_init, 241 .block_default_type = IF_SCSI, 242 .max_cpus = 1, 243 .no_sdcard = 1, 244 }; 245 246 static void zynq_machine_init(void) 247 { 248 qemu_register_machine(&zynq_machine); 249 } 250 251 machine_init(zynq_machine_init); 252