1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/vfio/vfio-calxeda-xgmac.h" 38 #include "hw/vfio/vfio-amd-xgbe.h" 39 #include "hw/devices.h" 40 #include "net/net.h" 41 #include "sysemu/block-backend.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/numa.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "hw/compat.h" 47 #include "hw/loader.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/bitops.h" 50 #include "qemu/error-report.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 62 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 63 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 64 void *data) \ 65 { \ 66 MachineClass *mc = MACHINE_CLASS(oc); \ 67 virt_machine_##major##_##minor##_options(mc); \ 68 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 69 if (latest) { \ 70 mc->alias = "virt"; \ 71 } \ 72 } \ 73 static const TypeInfo machvirt_##major##_##minor##_info = { \ 74 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 75 .parent = TYPE_VIRT_MACHINE, \ 76 .instance_init = virt_##major##_##minor##_instance_init, \ 77 .class_init = virt_##major##_##minor##_class_init, \ 78 }; \ 79 static void machvirt_machine_##major##_##minor##_init(void) \ 80 { \ 81 type_register_static(&machvirt_##major##_##minor##_info); \ 82 } \ 83 type_init(machvirt_machine_##major##_##minor##_init); 84 85 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 87 #define DEFINE_VIRT_MACHINE(major, minor) \ 88 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 89 90 91 /* Number of external interrupt lines to configure the GIC with */ 92 #define NUM_IRQS 256 93 94 #define PLATFORM_BUS_NUM_IRQS 64 95 96 static ARMPlatformBusSystemParams platform_bus_params; 97 98 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 99 * RAM can go up to the 256GB mark, leaving 256GB of the physical 100 * address space unallocated and free for future use between 256G and 512G. 101 * If we need to provide more RAM to VMs in the future then we need to: 102 * * allocate a second bank of RAM starting at 2TB and working up 103 * * fix the DT and ACPI table generation code in QEMU to correctly 104 * report two split lumps of RAM to the guest 105 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 106 * (We don't want to fill all the way up to 512GB with RAM because 107 * we might want it for non-RAM purposes later. Conversely it seems 108 * reasonable to assume that anybody configuring a VM with a quarter 109 * of a terabyte of RAM will be doing it on a host with more than a 110 * terabyte of physical address space.) 111 */ 112 #define RAMLIMIT_GB 255 113 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 114 115 /* Addresses and sizes of our components. 116 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 117 * 128MB..256MB is used for miscellaneous device I/O. 118 * 256MB..1GB is reserved for possible future PCI support (ie where the 119 * PCI memory window will go if we add a PCI host controller). 120 * 1GB and up is RAM (which may happily spill over into the 121 * high memory region beyond 4GB). 122 * This represents a compromise between how much RAM can be given to 123 * a 32 bit VM and leaving space for expansion and in particular for PCI. 124 * Note that devices should generally be placed at multiples of 0x10000, 125 * to accommodate guests using 64K pages. 126 */ 127 static const MemMapEntry a15memmap[] = { 128 /* Space up to 0x8000000 is reserved for a boot ROM */ 129 [VIRT_FLASH] = { 0, 0x08000000 }, 130 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 131 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 132 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 133 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 134 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 135 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 136 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 137 /* This redistributor space allows up to 2*64kB*123 CPUs */ 138 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 139 [VIRT_UART] = { 0x09000000, 0x00001000 }, 140 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 141 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 142 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 143 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 144 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 146 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 147 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 148 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 149 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 150 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 151 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 152 /* Second PCIe window, 512GB wide at the 512GB boundary */ 153 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 154 }; 155 156 static const int a15irqmap[] = { 157 [VIRT_UART] = 1, 158 [VIRT_RTC] = 2, 159 [VIRT_PCIE] = 3, /* ... to 6 */ 160 [VIRT_GPIO] = 7, 161 [VIRT_SECURE_UART] = 8, 162 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 163 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 164 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 165 }; 166 167 static const char *valid_cpus[] = { 168 ARM_CPU_TYPE_NAME("cortex-a15"), 169 ARM_CPU_TYPE_NAME("cortex-a53"), 170 ARM_CPU_TYPE_NAME("cortex-a57"), 171 ARM_CPU_TYPE_NAME("host"), 172 }; 173 174 static bool cpu_type_valid(const char *cpu) 175 { 176 int i; 177 178 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 179 if (strcmp(cpu, valid_cpus[i]) == 0) { 180 return true; 181 } 182 } 183 return false; 184 } 185 186 static void create_fdt(VirtMachineState *vms) 187 { 188 void *fdt = create_device_tree(&vms->fdt_size); 189 190 if (!fdt) { 191 error_report("create_device_tree() failed"); 192 exit(1); 193 } 194 195 vms->fdt = fdt; 196 197 /* Header */ 198 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 199 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 200 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 201 202 /* 203 * /chosen and /memory nodes must exist for load_dtb 204 * to fill in necessary properties later 205 */ 206 qemu_fdt_add_subnode(fdt, "/chosen"); 207 qemu_fdt_add_subnode(fdt, "/memory"); 208 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 209 210 /* Clock node, for the benefit of the UART. The kernel device tree 211 * binding documentation claims the PL011 node clock properties are 212 * optional but in practice if you omit them the kernel refuses to 213 * probe for the device. 214 */ 215 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 216 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 217 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 218 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 219 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 220 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 221 "clk24mhz"); 222 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 223 224 if (have_numa_distance) { 225 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 226 uint32_t *matrix = g_malloc0(size); 227 int idx, i, j; 228 229 for (i = 0; i < nb_numa_nodes; i++) { 230 for (j = 0; j < nb_numa_nodes; j++) { 231 idx = (i * nb_numa_nodes + j) * 3; 232 matrix[idx + 0] = cpu_to_be32(i); 233 matrix[idx + 1] = cpu_to_be32(j); 234 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 235 } 236 } 237 238 qemu_fdt_add_subnode(fdt, "/distance-map"); 239 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 240 "numa-distance-map-v1"); 241 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 242 matrix, size); 243 g_free(matrix); 244 } 245 } 246 247 static void fdt_add_psci_node(const VirtMachineState *vms) 248 { 249 uint32_t cpu_suspend_fn; 250 uint32_t cpu_off_fn; 251 uint32_t cpu_on_fn; 252 uint32_t migrate_fn; 253 void *fdt = vms->fdt; 254 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 255 const char *psci_method; 256 257 switch (vms->psci_conduit) { 258 case QEMU_PSCI_CONDUIT_DISABLED: 259 return; 260 case QEMU_PSCI_CONDUIT_HVC: 261 psci_method = "hvc"; 262 break; 263 case QEMU_PSCI_CONDUIT_SMC: 264 psci_method = "smc"; 265 break; 266 default: 267 g_assert_not_reached(); 268 } 269 270 qemu_fdt_add_subnode(fdt, "/psci"); 271 if (armcpu->psci_version == 2) { 272 const char comp[] = "arm,psci-0.2\0arm,psci"; 273 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 274 275 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 276 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 277 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 278 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 279 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 280 } else { 281 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 282 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 283 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 284 } 285 } else { 286 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 287 288 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 289 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 290 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 291 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 292 } 293 294 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 295 * to the instruction that should be used to invoke PSCI functions. 296 * However, the device tree binding uses 'method' instead, so that is 297 * what we should use here. 298 */ 299 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 300 301 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 302 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 303 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 304 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 305 } 306 307 static void fdt_add_timer_nodes(const VirtMachineState *vms) 308 { 309 /* On real hardware these interrupts are level-triggered. 310 * On KVM they were edge-triggered before host kernel version 4.4, 311 * and level-triggered afterwards. 312 * On emulated QEMU they are level-triggered. 313 * 314 * Getting the DTB info about them wrong is awkward for some 315 * guest kernels: 316 * pre-4.8 ignore the DT and leave the interrupt configured 317 * with whatever the GIC reset value (or the bootloader) left it at 318 * 4.8 before rc6 honour the incorrect data by programming it back 319 * into the GIC, causing problems 320 * 4.8rc6 and later ignore the DT and always write "level triggered" 321 * into the GIC 322 * 323 * For backwards-compatibility, virt-2.8 and earlier will continue 324 * to say these are edge-triggered, but later machines will report 325 * the correct information. 326 */ 327 ARMCPU *armcpu; 328 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 329 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 330 331 if (vmc->claim_edge_triggered_timers) { 332 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 333 } 334 335 if (vms->gic_version == 2) { 336 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 337 GIC_FDT_IRQ_PPI_CPU_WIDTH, 338 (1 << vms->smp_cpus) - 1); 339 } 340 341 qemu_fdt_add_subnode(vms->fdt, "/timer"); 342 343 armcpu = ARM_CPU(qemu_get_cpu(0)); 344 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 345 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 346 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 347 compat, sizeof(compat)); 348 } else { 349 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 350 "arm,armv7-timer"); 351 } 352 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 353 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 354 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 355 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 356 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 358 } 359 360 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 361 { 362 int cpu; 363 int addr_cells = 1; 364 const MachineState *ms = MACHINE(vms); 365 366 /* 367 * From Documentation/devicetree/bindings/arm/cpus.txt 368 * On ARM v8 64-bit systems value should be set to 2, 369 * that corresponds to the MPIDR_EL1 register size. 370 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 371 * in the system, #address-cells can be set to 1, since 372 * MPIDR_EL1[63:32] bits are not used for CPUs 373 * identification. 374 * 375 * Here we actually don't know whether our system is 32- or 64-bit one. 376 * The simplest way to go is to examine affinity IDs of all our CPUs. If 377 * at least one of them has Aff3 populated, we set #address-cells to 2. 378 */ 379 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 380 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 381 382 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 383 addr_cells = 2; 384 break; 385 } 386 } 387 388 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 389 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 390 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 391 392 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 393 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 394 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 395 CPUState *cs = CPU(armcpu); 396 397 qemu_fdt_add_subnode(vms->fdt, nodename); 398 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 399 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 400 armcpu->dtb_compatible); 401 402 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 403 && vms->smp_cpus > 1) { 404 qemu_fdt_setprop_string(vms->fdt, nodename, 405 "enable-method", "psci"); 406 } 407 408 if (addr_cells == 2) { 409 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 410 armcpu->mp_affinity); 411 } else { 412 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 413 armcpu->mp_affinity); 414 } 415 416 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 417 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 418 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 419 } 420 421 g_free(nodename); 422 } 423 } 424 425 static void fdt_add_its_gic_node(VirtMachineState *vms) 426 { 427 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 428 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 429 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 430 "arm,gic-v3-its"); 431 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 432 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 433 2, vms->memmap[VIRT_GIC_ITS].base, 434 2, vms->memmap[VIRT_GIC_ITS].size); 435 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 436 } 437 438 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 439 { 440 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 441 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 442 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 443 "arm,gic-v2m-frame"); 444 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 445 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 446 2, vms->memmap[VIRT_GIC_V2M].base, 447 2, vms->memmap[VIRT_GIC_V2M].size); 448 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 449 } 450 451 static void fdt_add_gic_node(VirtMachineState *vms) 452 { 453 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 454 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 455 456 qemu_fdt_add_subnode(vms->fdt, "/intc"); 457 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 458 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 459 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 460 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 461 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 462 if (vms->gic_version == 3) { 463 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 464 "arm,gic-v3"); 465 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 466 2, vms->memmap[VIRT_GIC_DIST].base, 467 2, vms->memmap[VIRT_GIC_DIST].size, 468 2, vms->memmap[VIRT_GIC_REDIST].base, 469 2, vms->memmap[VIRT_GIC_REDIST].size); 470 if (vms->virt) { 471 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 472 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 473 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 474 } 475 } else { 476 /* 'cortex-a15-gic' means 'GIC v2' */ 477 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 478 "arm,cortex-a15-gic"); 479 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 480 2, vms->memmap[VIRT_GIC_DIST].base, 481 2, vms->memmap[VIRT_GIC_DIST].size, 482 2, vms->memmap[VIRT_GIC_CPU].base, 483 2, vms->memmap[VIRT_GIC_CPU].size); 484 } 485 486 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 487 } 488 489 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 490 { 491 CPUState *cpu; 492 ARMCPU *armcpu; 493 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 494 495 CPU_FOREACH(cpu) { 496 armcpu = ARM_CPU(cpu); 497 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 498 return; 499 } 500 if (kvm_enabled()) { 501 if (kvm_irqchip_in_kernel()) { 502 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 503 } 504 kvm_arm_pmu_init(cpu); 505 } 506 } 507 508 if (vms->gic_version == 2) { 509 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 510 GIC_FDT_IRQ_PPI_CPU_WIDTH, 511 (1 << vms->smp_cpus) - 1); 512 } 513 514 armcpu = ARM_CPU(qemu_get_cpu(0)); 515 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 516 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 517 const char compat[] = "arm,armv8-pmuv3"; 518 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 519 compat, sizeof(compat)); 520 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 521 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 522 } 523 } 524 525 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 526 { 527 const char *itsclass = its_class_name(); 528 DeviceState *dev; 529 530 if (!itsclass) { 531 /* Do nothing if not supported */ 532 return; 533 } 534 535 dev = qdev_create(NULL, itsclass); 536 537 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 538 &error_abort); 539 qdev_init_nofail(dev); 540 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 541 542 fdt_add_its_gic_node(vms); 543 } 544 545 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 546 { 547 int i; 548 int irq = vms->irqmap[VIRT_GIC_V2M]; 549 DeviceState *dev; 550 551 dev = qdev_create(NULL, "arm-gicv2m"); 552 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 553 qdev_prop_set_uint32(dev, "base-spi", irq); 554 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 555 qdev_init_nofail(dev); 556 557 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 558 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 559 } 560 561 fdt_add_v2m_gic_node(vms); 562 } 563 564 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 565 { 566 /* We create a standalone GIC */ 567 DeviceState *gicdev; 568 SysBusDevice *gicbusdev; 569 const char *gictype; 570 int type = vms->gic_version, i; 571 572 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 573 574 gicdev = qdev_create(NULL, gictype); 575 qdev_prop_set_uint32(gicdev, "revision", type); 576 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 577 /* Note that the num-irq property counts both internal and external 578 * interrupts; there are always 32 of the former (mandated by GIC spec). 579 */ 580 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 581 if (!kvm_irqchip_in_kernel()) { 582 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 583 } 584 qdev_init_nofail(gicdev); 585 gicbusdev = SYS_BUS_DEVICE(gicdev); 586 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 587 if (type == 3) { 588 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 589 } else { 590 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 591 } 592 593 /* Wire the outputs from each CPU's generic timer and the GICv3 594 * maintenance interrupt signal to the appropriate GIC PPI inputs, 595 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 596 */ 597 for (i = 0; i < smp_cpus; i++) { 598 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 599 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 600 int irq; 601 /* Mapping from the output timer irq lines from the CPU to the 602 * GIC PPI inputs we use for the virt board. 603 */ 604 const int timer_irq[] = { 605 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 606 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 607 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 608 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 609 }; 610 611 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 612 qdev_connect_gpio_out(cpudev, irq, 613 qdev_get_gpio_in(gicdev, 614 ppibase + timer_irq[irq])); 615 } 616 617 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 618 qdev_get_gpio_in(gicdev, ppibase 619 + ARCH_GICV3_MAINT_IRQ)); 620 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 621 qdev_get_gpio_in(gicdev, ppibase 622 + VIRTUAL_PMU_IRQ)); 623 624 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 625 sysbus_connect_irq(gicbusdev, i + smp_cpus, 626 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 627 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 628 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 629 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 630 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 631 } 632 633 for (i = 0; i < NUM_IRQS; i++) { 634 pic[i] = qdev_get_gpio_in(gicdev, i); 635 } 636 637 fdt_add_gic_node(vms); 638 639 if (type == 3 && vms->its) { 640 create_its(vms, gicdev); 641 } else if (type == 2) { 642 create_v2m(vms, pic); 643 } 644 } 645 646 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 647 MemoryRegion *mem, Chardev *chr) 648 { 649 char *nodename; 650 hwaddr base = vms->memmap[uart].base; 651 hwaddr size = vms->memmap[uart].size; 652 int irq = vms->irqmap[uart]; 653 const char compat[] = "arm,pl011\0arm,primecell"; 654 const char clocknames[] = "uartclk\0apb_pclk"; 655 DeviceState *dev = qdev_create(NULL, "pl011"); 656 SysBusDevice *s = SYS_BUS_DEVICE(dev); 657 658 qdev_prop_set_chr(dev, "chardev", chr); 659 qdev_init_nofail(dev); 660 memory_region_add_subregion(mem, base, 661 sysbus_mmio_get_region(s, 0)); 662 sysbus_connect_irq(s, 0, pic[irq]); 663 664 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 665 qemu_fdt_add_subnode(vms->fdt, nodename); 666 /* Note that we can't use setprop_string because of the embedded NUL */ 667 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 668 compat, sizeof(compat)); 669 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 670 2, base, 2, size); 671 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 672 GIC_FDT_IRQ_TYPE_SPI, irq, 673 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 674 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 675 vms->clock_phandle, vms->clock_phandle); 676 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 677 clocknames, sizeof(clocknames)); 678 679 if (uart == VIRT_UART) { 680 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 681 } else { 682 /* Mark as not usable by the normal world */ 683 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 684 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 685 } 686 687 g_free(nodename); 688 } 689 690 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 691 { 692 char *nodename; 693 hwaddr base = vms->memmap[VIRT_RTC].base; 694 hwaddr size = vms->memmap[VIRT_RTC].size; 695 int irq = vms->irqmap[VIRT_RTC]; 696 const char compat[] = "arm,pl031\0arm,primecell"; 697 698 sysbus_create_simple("pl031", base, pic[irq]); 699 700 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 701 qemu_fdt_add_subnode(vms->fdt, nodename); 702 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 703 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 704 2, base, 2, size); 705 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 706 GIC_FDT_IRQ_TYPE_SPI, irq, 707 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 708 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 709 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 710 g_free(nodename); 711 } 712 713 static DeviceState *gpio_key_dev; 714 static void virt_powerdown_req(Notifier *n, void *opaque) 715 { 716 /* use gpio Pin 3 for power button event */ 717 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 718 } 719 720 static Notifier virt_system_powerdown_notifier = { 721 .notify = virt_powerdown_req 722 }; 723 724 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 725 { 726 char *nodename; 727 DeviceState *pl061_dev; 728 hwaddr base = vms->memmap[VIRT_GPIO].base; 729 hwaddr size = vms->memmap[VIRT_GPIO].size; 730 int irq = vms->irqmap[VIRT_GPIO]; 731 const char compat[] = "arm,pl061\0arm,primecell"; 732 733 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 734 735 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 736 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 737 qemu_fdt_add_subnode(vms->fdt, nodename); 738 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 739 2, base, 2, size); 740 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 741 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 742 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 743 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 744 GIC_FDT_IRQ_TYPE_SPI, irq, 745 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 746 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 747 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 748 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 749 750 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 751 qdev_get_gpio_in(pl061_dev, 3)); 752 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 753 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 754 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 755 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 756 757 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 758 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 759 "label", "GPIO Key Poweroff"); 760 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 761 KEY_POWER); 762 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 763 "gpios", phandle, 3, 0); 764 765 /* connect powerdown request */ 766 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 767 768 g_free(nodename); 769 } 770 771 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 772 { 773 int i; 774 hwaddr size = vms->memmap[VIRT_MMIO].size; 775 776 /* We create the transports in forwards order. Since qbus_realize() 777 * prepends (not appends) new child buses, the incrementing loop below will 778 * create a list of virtio-mmio buses with decreasing base addresses. 779 * 780 * When a -device option is processed from the command line, 781 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 782 * order. The upshot is that -device options in increasing command line 783 * order are mapped to virtio-mmio buses with decreasing base addresses. 784 * 785 * When this code was originally written, that arrangement ensured that the 786 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 787 * the first -device on the command line. (The end-to-end order is a 788 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 789 * guest kernel's name-to-address assignment strategy.) 790 * 791 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 792 * the message, if not necessarily the code, of commit 70161ff336. 793 * Therefore the loop now establishes the inverse of the original intent. 794 * 795 * Unfortunately, we can't counteract the kernel change by reversing the 796 * loop; it would break existing command lines. 797 * 798 * In any case, the kernel makes no guarantee about the stability of 799 * enumeration order of virtio devices (as demonstrated by it changing 800 * between kernel versions). For reliable and stable identification 801 * of disks users must use UUIDs or similar mechanisms. 802 */ 803 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 804 int irq = vms->irqmap[VIRT_MMIO] + i; 805 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 806 807 sysbus_create_simple("virtio-mmio", base, pic[irq]); 808 } 809 810 /* We add dtb nodes in reverse order so that they appear in the finished 811 * device tree lowest address first. 812 * 813 * Note that this mapping is independent of the loop above. The previous 814 * loop influences virtio device to virtio transport assignment, whereas 815 * this loop controls how virtio transports are laid out in the dtb. 816 */ 817 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 818 char *nodename; 819 int irq = vms->irqmap[VIRT_MMIO] + i; 820 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 821 822 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 823 qemu_fdt_add_subnode(vms->fdt, nodename); 824 qemu_fdt_setprop_string(vms->fdt, nodename, 825 "compatible", "virtio,mmio"); 826 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 827 2, base, 2, size); 828 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 829 GIC_FDT_IRQ_TYPE_SPI, irq, 830 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 831 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 832 g_free(nodename); 833 } 834 } 835 836 static void create_one_flash(const char *name, hwaddr flashbase, 837 hwaddr flashsize, const char *file, 838 MemoryRegion *sysmem) 839 { 840 /* Create and map a single flash device. We use the same 841 * parameters as the flash devices on the Versatile Express board. 842 */ 843 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 844 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 845 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 846 const uint64_t sectorlength = 256 * 1024; 847 848 if (dinfo) { 849 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 850 &error_abort); 851 } 852 853 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 854 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 855 qdev_prop_set_uint8(dev, "width", 4); 856 qdev_prop_set_uint8(dev, "device-width", 2); 857 qdev_prop_set_bit(dev, "big-endian", false); 858 qdev_prop_set_uint16(dev, "id0", 0x89); 859 qdev_prop_set_uint16(dev, "id1", 0x18); 860 qdev_prop_set_uint16(dev, "id2", 0x00); 861 qdev_prop_set_uint16(dev, "id3", 0x00); 862 qdev_prop_set_string(dev, "name", name); 863 qdev_init_nofail(dev); 864 865 memory_region_add_subregion(sysmem, flashbase, 866 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 867 868 if (file) { 869 char *fn; 870 int image_size; 871 872 if (drive_get(IF_PFLASH, 0, 0)) { 873 error_report("The contents of the first flash device may be " 874 "specified with -bios or with -drive if=pflash... " 875 "but you cannot use both options at once"); 876 exit(1); 877 } 878 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 879 if (!fn) { 880 error_report("Could not find ROM image '%s'", file); 881 exit(1); 882 } 883 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 884 g_free(fn); 885 if (image_size < 0) { 886 error_report("Could not load ROM image '%s'", file); 887 exit(1); 888 } 889 } 890 } 891 892 static void create_flash(const VirtMachineState *vms, 893 MemoryRegion *sysmem, 894 MemoryRegion *secure_sysmem) 895 { 896 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 897 * Any file passed via -bios goes in the first of these. 898 * sysmem is the system memory space. secure_sysmem is the secure view 899 * of the system, and the first flash device should be made visible only 900 * there. The second flash device is visible to both secure and nonsecure. 901 * If sysmem == secure_sysmem this means there is no separate Secure 902 * address space and both flash devices are generally visible. 903 */ 904 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 905 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 906 char *nodename; 907 908 create_one_flash("virt.flash0", flashbase, flashsize, 909 bios_name, secure_sysmem); 910 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 911 NULL, sysmem); 912 913 if (sysmem == secure_sysmem) { 914 /* Report both flash devices as a single node in the DT */ 915 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 916 qemu_fdt_add_subnode(vms->fdt, nodename); 917 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 918 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 919 2, flashbase, 2, flashsize, 920 2, flashbase + flashsize, 2, flashsize); 921 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 922 g_free(nodename); 923 } else { 924 /* Report the devices as separate nodes so we can mark one as 925 * only visible to the secure world. 926 */ 927 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 928 qemu_fdt_add_subnode(vms->fdt, nodename); 929 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 930 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 931 2, flashbase, 2, flashsize); 932 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 933 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 934 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 935 g_free(nodename); 936 937 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 938 qemu_fdt_add_subnode(vms->fdt, nodename); 939 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 940 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 941 2, flashbase + flashsize, 2, flashsize); 942 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 943 g_free(nodename); 944 } 945 } 946 947 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 948 { 949 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 950 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 951 FWCfgState *fw_cfg; 952 char *nodename; 953 954 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 955 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 956 957 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 958 qemu_fdt_add_subnode(vms->fdt, nodename); 959 qemu_fdt_setprop_string(vms->fdt, nodename, 960 "compatible", "qemu,fw-cfg-mmio"); 961 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 962 2, base, 2, size); 963 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 964 g_free(nodename); 965 return fw_cfg; 966 } 967 968 static void create_pcie_irq_map(const VirtMachineState *vms, 969 uint32_t gic_phandle, 970 int first_irq, const char *nodename) 971 { 972 int devfn, pin; 973 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 974 uint32_t *irq_map = full_irq_map; 975 976 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 977 for (pin = 0; pin < 4; pin++) { 978 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 979 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 980 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 981 int i; 982 983 uint32_t map[] = { 984 devfn << 8, 0, 0, /* devfn */ 985 pin + 1, /* PCI pin */ 986 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 987 988 /* Convert map to big endian */ 989 for (i = 0; i < 10; i++) { 990 irq_map[i] = cpu_to_be32(map[i]); 991 } 992 irq_map += 10; 993 } 994 } 995 996 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 997 full_irq_map, sizeof(full_irq_map)); 998 999 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1000 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1001 0x7 /* PCI irq */); 1002 } 1003 1004 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 1005 { 1006 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1007 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1008 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 1009 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 1010 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1011 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1012 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 1013 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 1014 hwaddr base = base_mmio; 1015 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1016 int irq = vms->irqmap[VIRT_PCIE]; 1017 MemoryRegion *mmio_alias; 1018 MemoryRegion *mmio_reg; 1019 MemoryRegion *ecam_alias; 1020 MemoryRegion *ecam_reg; 1021 DeviceState *dev; 1022 char *nodename; 1023 int i; 1024 PCIHostState *pci; 1025 1026 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1027 qdev_init_nofail(dev); 1028 1029 /* Map only the first size_ecam bytes of ECAM space */ 1030 ecam_alias = g_new0(MemoryRegion, 1); 1031 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1032 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1033 ecam_reg, 0, size_ecam); 1034 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1035 1036 /* Map the MMIO window into system address space so as to expose 1037 * the section of PCI MMIO space which starts at the same base address 1038 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1039 * the window). 1040 */ 1041 mmio_alias = g_new0(MemoryRegion, 1); 1042 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1043 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1044 mmio_reg, base_mmio, size_mmio); 1045 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1046 1047 if (vms->highmem) { 1048 /* Map high MMIO space */ 1049 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1050 1051 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1052 mmio_reg, base_mmio_high, size_mmio_high); 1053 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1054 high_mmio_alias); 1055 } 1056 1057 /* Map IO port space */ 1058 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1059 1060 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1061 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1062 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1063 } 1064 1065 pci = PCI_HOST_BRIDGE(dev); 1066 if (pci->bus) { 1067 for (i = 0; i < nb_nics; i++) { 1068 NICInfo *nd = &nd_table[i]; 1069 1070 if (!nd->model) { 1071 nd->model = g_strdup("virtio"); 1072 } 1073 1074 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1075 } 1076 } 1077 1078 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1079 qemu_fdt_add_subnode(vms->fdt, nodename); 1080 qemu_fdt_setprop_string(vms->fdt, nodename, 1081 "compatible", "pci-host-ecam-generic"); 1082 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1083 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1084 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1085 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1086 nr_pcie_buses - 1); 1087 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1088 1089 if (vms->msi_phandle) { 1090 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1091 vms->msi_phandle); 1092 } 1093 1094 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1095 2, base_ecam, 2, size_ecam); 1096 1097 if (vms->highmem) { 1098 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1099 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1100 2, base_pio, 2, size_pio, 1101 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1102 2, base_mmio, 2, size_mmio, 1103 1, FDT_PCI_RANGE_MMIO_64BIT, 1104 2, base_mmio_high, 1105 2, base_mmio_high, 2, size_mmio_high); 1106 } else { 1107 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1108 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1109 2, base_pio, 2, size_pio, 1110 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1111 2, base_mmio, 2, size_mmio); 1112 } 1113 1114 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1115 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1116 1117 g_free(nodename); 1118 } 1119 1120 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1121 { 1122 DeviceState *dev; 1123 SysBusDevice *s; 1124 int i; 1125 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1126 MemoryRegion *sysmem = get_system_memory(); 1127 1128 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1129 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1130 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1131 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1132 1133 fdt_params->system_params = &platform_bus_params; 1134 fdt_params->binfo = &vms->bootinfo; 1135 fdt_params->intc = "/intc"; 1136 /* 1137 * register a machine init done notifier that creates the device tree 1138 * nodes of the platform bus and its children dynamic sysbus devices 1139 */ 1140 arm_register_platform_bus_fdt_creator(fdt_params); 1141 1142 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1143 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1144 qdev_prop_set_uint32(dev, "num_irqs", 1145 platform_bus_params.platform_bus_num_irqs); 1146 qdev_prop_set_uint32(dev, "mmio_size", 1147 platform_bus_params.platform_bus_size); 1148 qdev_init_nofail(dev); 1149 s = SYS_BUS_DEVICE(dev); 1150 1151 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1152 int irqn = platform_bus_params.platform_bus_first_irq + i; 1153 sysbus_connect_irq(s, i, pic[irqn]); 1154 } 1155 1156 memory_region_add_subregion(sysmem, 1157 platform_bus_params.platform_bus_base, 1158 sysbus_mmio_get_region(s, 0)); 1159 } 1160 1161 static void create_secure_ram(VirtMachineState *vms, 1162 MemoryRegion *secure_sysmem) 1163 { 1164 MemoryRegion *secram = g_new(MemoryRegion, 1); 1165 char *nodename; 1166 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1167 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1168 1169 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1170 &error_fatal); 1171 memory_region_add_subregion(secure_sysmem, base, secram); 1172 1173 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1174 qemu_fdt_add_subnode(vms->fdt, nodename); 1175 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1176 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1177 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1178 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1179 1180 g_free(nodename); 1181 } 1182 1183 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1184 { 1185 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1186 bootinfo); 1187 1188 *fdt_size = board->fdt_size; 1189 return board->fdt; 1190 } 1191 1192 static void virt_build_smbios(VirtMachineState *vms) 1193 { 1194 uint8_t *smbios_tables, *smbios_anchor; 1195 size_t smbios_tables_len, smbios_anchor_len; 1196 const char *product = "QEMU Virtual Machine"; 1197 1198 if (!vms->fw_cfg) { 1199 return; 1200 } 1201 1202 if (kvm_enabled()) { 1203 product = "KVM Virtual Machine"; 1204 } 1205 1206 smbios_set_defaults("QEMU", product, 1207 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1208 1209 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1210 &smbios_anchor, &smbios_anchor_len); 1211 1212 if (smbios_anchor) { 1213 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1214 smbios_tables, smbios_tables_len); 1215 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1216 smbios_anchor, smbios_anchor_len); 1217 } 1218 } 1219 1220 static 1221 void virt_machine_done(Notifier *notifier, void *data) 1222 { 1223 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1224 machine_done); 1225 1226 virt_acpi_setup(vms); 1227 virt_build_smbios(vms); 1228 } 1229 1230 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1231 { 1232 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1233 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1234 1235 if (!vmc->disallow_affinity_adjustment) { 1236 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1237 * GIC's target-list limitations. 32-bit KVM hosts currently 1238 * always create clusters of 4 CPUs, but that is expected to 1239 * change when they gain support for gicv3. When KVM is enabled 1240 * it will override the changes we make here, therefore our 1241 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1242 * and to improve SGI efficiency. 1243 */ 1244 if (vms->gic_version == 3) { 1245 clustersz = GICV3_TARGETLIST_BITS; 1246 } else { 1247 clustersz = GIC_TARGETLIST_BITS; 1248 } 1249 } 1250 return arm_cpu_mp_affinity(idx, clustersz); 1251 } 1252 1253 static void machvirt_init(MachineState *machine) 1254 { 1255 VirtMachineState *vms = VIRT_MACHINE(machine); 1256 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1257 MachineClass *mc = MACHINE_GET_CLASS(machine); 1258 const CPUArchIdList *possible_cpus; 1259 qemu_irq pic[NUM_IRQS]; 1260 MemoryRegion *sysmem = get_system_memory(); 1261 MemoryRegion *secure_sysmem = NULL; 1262 int n, virt_max_cpus; 1263 MemoryRegion *ram = g_new(MemoryRegion, 1); 1264 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1265 1266 /* We can probe only here because during property set 1267 * KVM is not available yet 1268 */ 1269 if (!vms->gic_version) { 1270 if (!kvm_enabled()) { 1271 error_report("gic-version=host requires KVM"); 1272 exit(1); 1273 } 1274 1275 vms->gic_version = kvm_arm_vgic_probe(); 1276 if (!vms->gic_version) { 1277 error_report("Unable to determine GIC version supported by host"); 1278 exit(1); 1279 } 1280 } 1281 1282 if (!cpu_type_valid(machine->cpu_type)) { 1283 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1284 exit(1); 1285 } 1286 1287 /* If we have an EL3 boot ROM then the assumption is that it will 1288 * implement PSCI itself, so disable QEMU's internal implementation 1289 * so it doesn't get in the way. Instead of starting secondary 1290 * CPUs in PSCI powerdown state we will start them all running and 1291 * let the boot ROM sort them out. 1292 * The usual case is that we do use QEMU's PSCI implementation; 1293 * if the guest has EL2 then we will use SMC as the conduit, 1294 * and otherwise we will use HVC (for backwards compatibility and 1295 * because if we're using KVM then we must use HVC). 1296 */ 1297 if (vms->secure && firmware_loaded) { 1298 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1299 } else if (vms->virt) { 1300 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1301 } else { 1302 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1303 } 1304 1305 /* The maximum number of CPUs depends on the GIC version, or on how 1306 * many redistributors we can fit into the memory map. 1307 */ 1308 if (vms->gic_version == 3) { 1309 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1310 } else { 1311 virt_max_cpus = GIC_NCPU; 1312 } 1313 1314 if (max_cpus > virt_max_cpus) { 1315 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1316 "supported by machine 'mach-virt' (%d)", 1317 max_cpus, virt_max_cpus); 1318 exit(1); 1319 } 1320 1321 vms->smp_cpus = smp_cpus; 1322 1323 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1324 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1325 exit(1); 1326 } 1327 1328 if (vms->virt && kvm_enabled()) { 1329 error_report("mach-virt: KVM does not support providing " 1330 "Virtualization extensions to the guest CPU"); 1331 exit(1); 1332 } 1333 1334 if (vms->secure) { 1335 if (kvm_enabled()) { 1336 error_report("mach-virt: KVM does not support Security extensions"); 1337 exit(1); 1338 } 1339 1340 /* The Secure view of the world is the same as the NonSecure, 1341 * but with a few extra devices. Create it as a container region 1342 * containing the system memory at low priority; any secure-only 1343 * devices go in at higher priority and take precedence. 1344 */ 1345 secure_sysmem = g_new(MemoryRegion, 1); 1346 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1347 UINT64_MAX); 1348 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1349 } 1350 1351 create_fdt(vms); 1352 1353 possible_cpus = mc->possible_cpu_arch_ids(machine); 1354 for (n = 0; n < possible_cpus->len; n++) { 1355 Object *cpuobj; 1356 CPUState *cs; 1357 1358 if (n >= smp_cpus) { 1359 break; 1360 } 1361 1362 cpuobj = object_new(possible_cpus->cpus[n].type); 1363 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1364 "mp-affinity", NULL); 1365 1366 cs = CPU(cpuobj); 1367 cs->cpu_index = n; 1368 1369 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1370 &error_fatal); 1371 1372 if (!vms->secure) { 1373 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1374 } 1375 1376 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1377 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1378 } 1379 1380 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1381 object_property_set_int(cpuobj, vms->psci_conduit, 1382 "psci-conduit", NULL); 1383 1384 /* Secondary CPUs start in PSCI powered-down state */ 1385 if (n > 0) { 1386 object_property_set_bool(cpuobj, true, 1387 "start-powered-off", NULL); 1388 } 1389 } 1390 1391 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1392 object_property_set_bool(cpuobj, false, "pmu", NULL); 1393 } 1394 1395 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1396 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1397 "reset-cbar", &error_abort); 1398 } 1399 1400 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1401 &error_abort); 1402 if (vms->secure) { 1403 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1404 "secure-memory", &error_abort); 1405 } 1406 1407 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1408 object_unref(cpuobj); 1409 } 1410 fdt_add_timer_nodes(vms); 1411 fdt_add_cpu_nodes(vms); 1412 fdt_add_psci_node(vms); 1413 1414 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1415 machine->ram_size); 1416 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1417 1418 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1419 1420 create_gic(vms, pic); 1421 1422 fdt_add_pmu_nodes(vms); 1423 1424 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1425 1426 if (vms->secure) { 1427 create_secure_ram(vms, secure_sysmem); 1428 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1429 } 1430 1431 create_rtc(vms, pic); 1432 1433 create_pcie(vms, pic); 1434 1435 create_gpio(vms, pic); 1436 1437 /* Create mmio transports, so the user can create virtio backends 1438 * (which will be automatically plugged in to the transports). If 1439 * no backend is created the transport will just sit harmlessly idle. 1440 */ 1441 create_virtio_devices(vms, pic); 1442 1443 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1444 rom_set_fw(vms->fw_cfg); 1445 1446 vms->machine_done.notify = virt_machine_done; 1447 qemu_add_machine_init_done_notifier(&vms->machine_done); 1448 1449 vms->bootinfo.ram_size = machine->ram_size; 1450 vms->bootinfo.kernel_filename = machine->kernel_filename; 1451 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1452 vms->bootinfo.initrd_filename = machine->initrd_filename; 1453 vms->bootinfo.nb_cpus = smp_cpus; 1454 vms->bootinfo.board_id = -1; 1455 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1456 vms->bootinfo.get_dtb = machvirt_dtb; 1457 vms->bootinfo.firmware_loaded = firmware_loaded; 1458 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1459 1460 /* 1461 * arm_load_kernel machine init done notifier registration must 1462 * happen before the platform_bus_create call. In this latter, 1463 * another notifier is registered which adds platform bus nodes. 1464 * Notifiers are executed in registration reverse order. 1465 */ 1466 create_platform_bus(vms, pic); 1467 } 1468 1469 static bool virt_get_secure(Object *obj, Error **errp) 1470 { 1471 VirtMachineState *vms = VIRT_MACHINE(obj); 1472 1473 return vms->secure; 1474 } 1475 1476 static void virt_set_secure(Object *obj, bool value, Error **errp) 1477 { 1478 VirtMachineState *vms = VIRT_MACHINE(obj); 1479 1480 vms->secure = value; 1481 } 1482 1483 static bool virt_get_virt(Object *obj, Error **errp) 1484 { 1485 VirtMachineState *vms = VIRT_MACHINE(obj); 1486 1487 return vms->virt; 1488 } 1489 1490 static void virt_set_virt(Object *obj, bool value, Error **errp) 1491 { 1492 VirtMachineState *vms = VIRT_MACHINE(obj); 1493 1494 vms->virt = value; 1495 } 1496 1497 static bool virt_get_highmem(Object *obj, Error **errp) 1498 { 1499 VirtMachineState *vms = VIRT_MACHINE(obj); 1500 1501 return vms->highmem; 1502 } 1503 1504 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1505 { 1506 VirtMachineState *vms = VIRT_MACHINE(obj); 1507 1508 vms->highmem = value; 1509 } 1510 1511 static bool virt_get_its(Object *obj, Error **errp) 1512 { 1513 VirtMachineState *vms = VIRT_MACHINE(obj); 1514 1515 return vms->its; 1516 } 1517 1518 static void virt_set_its(Object *obj, bool value, Error **errp) 1519 { 1520 VirtMachineState *vms = VIRT_MACHINE(obj); 1521 1522 vms->its = value; 1523 } 1524 1525 static char *virt_get_gic_version(Object *obj, Error **errp) 1526 { 1527 VirtMachineState *vms = VIRT_MACHINE(obj); 1528 const char *val = vms->gic_version == 3 ? "3" : "2"; 1529 1530 return g_strdup(val); 1531 } 1532 1533 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1534 { 1535 VirtMachineState *vms = VIRT_MACHINE(obj); 1536 1537 if (!strcmp(value, "3")) { 1538 vms->gic_version = 3; 1539 } else if (!strcmp(value, "2")) { 1540 vms->gic_version = 2; 1541 } else if (!strcmp(value, "host")) { 1542 vms->gic_version = 0; /* Will probe later */ 1543 } else { 1544 error_setg(errp, "Invalid gic-version value"); 1545 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1546 } 1547 } 1548 1549 static CpuInstanceProperties 1550 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1551 { 1552 MachineClass *mc = MACHINE_GET_CLASS(ms); 1553 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1554 1555 assert(cpu_index < possible_cpus->len); 1556 return possible_cpus->cpus[cpu_index].props; 1557 } 1558 1559 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1560 { 1561 return idx % nb_numa_nodes; 1562 } 1563 1564 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1565 { 1566 int n; 1567 VirtMachineState *vms = VIRT_MACHINE(ms); 1568 1569 if (ms->possible_cpus) { 1570 assert(ms->possible_cpus->len == max_cpus); 1571 return ms->possible_cpus; 1572 } 1573 1574 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1575 sizeof(CPUArchId) * max_cpus); 1576 ms->possible_cpus->len = max_cpus; 1577 for (n = 0; n < ms->possible_cpus->len; n++) { 1578 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1579 ms->possible_cpus->cpus[n].arch_id = 1580 virt_cpu_mp_affinity(vms, n); 1581 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1582 ms->possible_cpus->cpus[n].props.thread_id = n; 1583 } 1584 return ms->possible_cpus; 1585 } 1586 1587 static void virt_machine_class_init(ObjectClass *oc, void *data) 1588 { 1589 MachineClass *mc = MACHINE_CLASS(oc); 1590 1591 mc->init = machvirt_init; 1592 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1593 * it later in machvirt_init, where we have more information about the 1594 * configuration of the particular instance. 1595 */ 1596 mc->max_cpus = 255; 1597 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1598 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1599 mc->block_default_type = IF_VIRTIO; 1600 mc->no_cdrom = 1; 1601 mc->pci_allow_0_address = true; 1602 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1603 mc->minimum_page_bits = 12; 1604 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1605 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1606 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1607 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1608 } 1609 1610 static const TypeInfo virt_machine_info = { 1611 .name = TYPE_VIRT_MACHINE, 1612 .parent = TYPE_MACHINE, 1613 .abstract = true, 1614 .instance_size = sizeof(VirtMachineState), 1615 .class_size = sizeof(VirtMachineClass), 1616 .class_init = virt_machine_class_init, 1617 }; 1618 1619 static void machvirt_machine_init(void) 1620 { 1621 type_register_static(&virt_machine_info); 1622 } 1623 type_init(machvirt_machine_init); 1624 1625 static void virt_2_12_instance_init(Object *obj) 1626 { 1627 VirtMachineState *vms = VIRT_MACHINE(obj); 1628 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1629 1630 /* EL3 is disabled by default on virt: this makes us consistent 1631 * between KVM and TCG for this board, and it also allows us to 1632 * boot UEFI blobs which assume no TrustZone support. 1633 */ 1634 vms->secure = false; 1635 object_property_add_bool(obj, "secure", virt_get_secure, 1636 virt_set_secure, NULL); 1637 object_property_set_description(obj, "secure", 1638 "Set on/off to enable/disable the ARM " 1639 "Security Extensions (TrustZone)", 1640 NULL); 1641 1642 /* EL2 is also disabled by default, for similar reasons */ 1643 vms->virt = false; 1644 object_property_add_bool(obj, "virtualization", virt_get_virt, 1645 virt_set_virt, NULL); 1646 object_property_set_description(obj, "virtualization", 1647 "Set on/off to enable/disable emulating a " 1648 "guest CPU which implements the ARM " 1649 "Virtualization Extensions", 1650 NULL); 1651 1652 /* High memory is enabled by default */ 1653 vms->highmem = true; 1654 object_property_add_bool(obj, "highmem", virt_get_highmem, 1655 virt_set_highmem, NULL); 1656 object_property_set_description(obj, "highmem", 1657 "Set on/off to enable/disable using " 1658 "physical address space above 32 bits", 1659 NULL); 1660 /* Default GIC type is v2 */ 1661 vms->gic_version = 2; 1662 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1663 virt_set_gic_version, NULL); 1664 object_property_set_description(obj, "gic-version", 1665 "Set GIC version. " 1666 "Valid values are 2, 3 and host", NULL); 1667 1668 if (vmc->no_its) { 1669 vms->its = false; 1670 } else { 1671 /* Default allows ITS instantiation */ 1672 vms->its = true; 1673 object_property_add_bool(obj, "its", virt_get_its, 1674 virt_set_its, NULL); 1675 object_property_set_description(obj, "its", 1676 "Set on/off to enable/disable " 1677 "ITS instantiation", 1678 NULL); 1679 } 1680 1681 vms->memmap = a15memmap; 1682 vms->irqmap = a15irqmap; 1683 } 1684 1685 static void virt_machine_2_12_options(MachineClass *mc) 1686 { 1687 } 1688 DEFINE_VIRT_MACHINE_AS_LATEST(2, 12) 1689 1690 #define VIRT_COMPAT_2_11 \ 1691 HW_COMPAT_2_11 1692 1693 static void virt_2_11_instance_init(Object *obj) 1694 { 1695 virt_2_12_instance_init(obj); 1696 } 1697 1698 static void virt_machine_2_11_options(MachineClass *mc) 1699 { 1700 virt_machine_2_12_options(mc); 1701 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); 1702 } 1703 DEFINE_VIRT_MACHINE(2, 11) 1704 1705 #define VIRT_COMPAT_2_10 \ 1706 HW_COMPAT_2_10 1707 1708 static void virt_2_10_instance_init(Object *obj) 1709 { 1710 virt_2_11_instance_init(obj); 1711 } 1712 1713 static void virt_machine_2_10_options(MachineClass *mc) 1714 { 1715 virt_machine_2_11_options(mc); 1716 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); 1717 } 1718 DEFINE_VIRT_MACHINE(2, 10) 1719 1720 #define VIRT_COMPAT_2_9 \ 1721 HW_COMPAT_2_9 1722 1723 static void virt_2_9_instance_init(Object *obj) 1724 { 1725 virt_2_10_instance_init(obj); 1726 } 1727 1728 static void virt_machine_2_9_options(MachineClass *mc) 1729 { 1730 virt_machine_2_10_options(mc); 1731 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1732 } 1733 DEFINE_VIRT_MACHINE(2, 9) 1734 1735 #define VIRT_COMPAT_2_8 \ 1736 HW_COMPAT_2_8 1737 1738 static void virt_2_8_instance_init(Object *obj) 1739 { 1740 virt_2_9_instance_init(obj); 1741 } 1742 1743 static void virt_machine_2_8_options(MachineClass *mc) 1744 { 1745 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1746 1747 virt_machine_2_9_options(mc); 1748 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1749 /* For 2.8 and earlier we falsely claimed in the DT that 1750 * our timers were edge-triggered, not level-triggered. 1751 */ 1752 vmc->claim_edge_triggered_timers = true; 1753 } 1754 DEFINE_VIRT_MACHINE(2, 8) 1755 1756 #define VIRT_COMPAT_2_7 \ 1757 HW_COMPAT_2_7 1758 1759 static void virt_2_7_instance_init(Object *obj) 1760 { 1761 virt_2_8_instance_init(obj); 1762 } 1763 1764 static void virt_machine_2_7_options(MachineClass *mc) 1765 { 1766 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1767 1768 virt_machine_2_8_options(mc); 1769 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1770 /* ITS was introduced with 2.8 */ 1771 vmc->no_its = true; 1772 /* Stick with 1K pages for migration compatibility */ 1773 mc->minimum_page_bits = 0; 1774 } 1775 DEFINE_VIRT_MACHINE(2, 7) 1776 1777 #define VIRT_COMPAT_2_6 \ 1778 HW_COMPAT_2_6 1779 1780 static void virt_2_6_instance_init(Object *obj) 1781 { 1782 virt_2_7_instance_init(obj); 1783 } 1784 1785 static void virt_machine_2_6_options(MachineClass *mc) 1786 { 1787 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1788 1789 virt_machine_2_7_options(mc); 1790 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1791 vmc->disallow_affinity_adjustment = true; 1792 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1793 vmc->no_pmu = true; 1794 } 1795 DEFINE_VIRT_MACHINE(2, 6) 1796