xref: /openbmc/qemu/hw/arm/virt.c (revision fa59483d)
1 /*
2  * ARM mach-virt emulation
3  *
4  * Copyright (c) 2013 Linaro Limited
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * Emulate a virtual board which works by passing Linux all the information
19  * it needs about what devices are present via the device tree.
20  * There are some restrictions about what we can do here:
21  *  + we can only present devices whose Linux drivers will work based
22  *    purely on the device tree with no platform data at all
23  *  + we want to present a very stripped-down minimalist platform,
24  *    both because this reduces the security attack surface from the guest
25  *    and also because it reduces our exposure to being broken when
26  *    the kernel updates its device tree bindings and requires further
27  *    information in a device binding that we aren't providing.
28  * This is essentially the same approach kvmtool uses.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "qapi/error.h"
34 #include "hw/sysbus.h"
35 #include "hw/arm/arm.h"
36 #include "hw/arm/primecell.h"
37 #include "hw/arm/virt.h"
38 #include "hw/vfio/vfio-calxeda-xgmac.h"
39 #include "hw/vfio/vfio-amd-xgbe.h"
40 #include "hw/display/ramfb.h"
41 #include "net/net.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/numa.h"
44 #include "sysemu/sysemu.h"
45 #include "sysemu/kvm.h"
46 #include "hw/loader.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/bitops.h"
49 #include "qemu/error-report.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/arm/sysbus-fdt.h"
52 #include "hw/platform-bus.h"
53 #include "hw/arm/fdt.h"
54 #include "hw/intc/arm_gic.h"
55 #include "hw/intc/arm_gicv3_common.h"
56 #include "kvm_arm.h"
57 #include "hw/firmware/smbios.h"
58 #include "qapi/visitor.h"
59 #include "standard-headers/linux/input.h"
60 #include "hw/arm/smmuv3.h"
61 #include "hw/acpi/acpi.h"
62 #include "target/arm/internals.h"
63 
64 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
65     static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
66                                                     void *data) \
67     { \
68         MachineClass *mc = MACHINE_CLASS(oc); \
69         virt_machine_##major##_##minor##_options(mc); \
70         mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
71         if (latest) { \
72             mc->alias = "virt"; \
73         } \
74     } \
75     static const TypeInfo machvirt_##major##_##minor##_info = { \
76         .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
77         .parent = TYPE_VIRT_MACHINE, \
78         .class_init = virt_##major##_##minor##_class_init, \
79     }; \
80     static void machvirt_machine_##major##_##minor##_init(void) \
81     { \
82         type_register_static(&machvirt_##major##_##minor##_info); \
83     } \
84     type_init(machvirt_machine_##major##_##minor##_init);
85 
86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
87     DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
88 #define DEFINE_VIRT_MACHINE(major, minor) \
89     DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
90 
91 
92 /* Number of external interrupt lines to configure the GIC with */
93 #define NUM_IRQS 256
94 
95 #define PLATFORM_BUS_NUM_IRQS 64
96 
97 /* Legacy RAM limit in GB (< version 4.0) */
98 #define LEGACY_RAMLIMIT_GB 255
99 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
100 
101 /* Addresses and sizes of our components.
102  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
103  * 128MB..256MB is used for miscellaneous device I/O.
104  * 256MB..1GB is reserved for possible future PCI support (ie where the
105  * PCI memory window will go if we add a PCI host controller).
106  * 1GB and up is RAM (which may happily spill over into the
107  * high memory region beyond 4GB).
108  * This represents a compromise between how much RAM can be given to
109  * a 32 bit VM and leaving space for expansion and in particular for PCI.
110  * Note that devices should generally be placed at multiples of 0x10000,
111  * to accommodate guests using 64K pages.
112  */
113 static const MemMapEntry base_memmap[] = {
114     /* Space up to 0x8000000 is reserved for a boot ROM */
115     [VIRT_FLASH] =              {          0, 0x08000000 },
116     [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
117     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
118     [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
119     [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
120     [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
121     [VIRT_GIC_HYP] =            { 0x08030000, 0x00010000 },
122     [VIRT_GIC_VCPU] =           { 0x08040000, 0x00010000 },
123     /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
124     [VIRT_GIC_ITS] =            { 0x08080000, 0x00020000 },
125     /* This redistributor space allows up to 2*64kB*123 CPUs */
126     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
127     [VIRT_UART] =               { 0x09000000, 0x00001000 },
128     [VIRT_RTC] =                { 0x09010000, 0x00001000 },
129     [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
130     [VIRT_GPIO] =               { 0x09030000, 0x00001000 },
131     [VIRT_SECURE_UART] =        { 0x09040000, 0x00001000 },
132     [VIRT_SMMU] =               { 0x09050000, 0x00020000 },
133     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
134     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
135     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
136     [VIRT_SECURE_MEM] =         { 0x0e000000, 0x01000000 },
137     [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
138     [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
139     [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
140     /* Actual RAM size depends on initial RAM and device memory settings */
141     [VIRT_MEM] =                { GiB, LEGACY_RAMLIMIT_BYTES },
142 };
143 
144 /*
145  * Highmem IO Regions: This memory map is floating, located after the RAM.
146  * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
147  * top of the RAM, so that its base get the same alignment as the size,
148  * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
149  * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
150  * Note the extended_memmap is sized so that it eventually also includes the
151  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
152  * index of base_memmap).
153  */
154 static MemMapEntry extended_memmap[] = {
155     /* Additional 64 MB redist region (can contain up to 512 redistributors) */
156     [VIRT_HIGH_GIC_REDIST2] =   { 0x0, 64 * MiB },
157     [VIRT_HIGH_PCIE_ECAM] =     { 0x0, 256 * MiB },
158     /* Second PCIe window */
159     [VIRT_HIGH_PCIE_MMIO] =     { 0x0, 512 * GiB },
160 };
161 
162 static const int a15irqmap[] = {
163     [VIRT_UART] = 1,
164     [VIRT_RTC] = 2,
165     [VIRT_PCIE] = 3, /* ... to 6 */
166     [VIRT_GPIO] = 7,
167     [VIRT_SECURE_UART] = 8,
168     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
169     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
170     [VIRT_SMMU] = 74,    /* ...to 74 + NUM_SMMU_IRQS - 1 */
171     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
172 };
173 
174 static const char *valid_cpus[] = {
175     ARM_CPU_TYPE_NAME("cortex-a15"),
176     ARM_CPU_TYPE_NAME("cortex-a53"),
177     ARM_CPU_TYPE_NAME("cortex-a57"),
178     ARM_CPU_TYPE_NAME("cortex-a72"),
179     ARM_CPU_TYPE_NAME("host"),
180     ARM_CPU_TYPE_NAME("max"),
181 };
182 
183 static bool cpu_type_valid(const char *cpu)
184 {
185     int i;
186 
187     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
188         if (strcmp(cpu, valid_cpus[i]) == 0) {
189             return true;
190         }
191     }
192     return false;
193 }
194 
195 static void create_fdt(VirtMachineState *vms)
196 {
197     void *fdt = create_device_tree(&vms->fdt_size);
198 
199     if (!fdt) {
200         error_report("create_device_tree() failed");
201         exit(1);
202     }
203 
204     vms->fdt = fdt;
205 
206     /* Header */
207     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
208     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
209     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
210 
211     /* /chosen must exist for load_dtb to fill in necessary properties later */
212     qemu_fdt_add_subnode(fdt, "/chosen");
213 
214     /* Clock node, for the benefit of the UART. The kernel device tree
215      * binding documentation claims the PL011 node clock properties are
216      * optional but in practice if you omit them the kernel refuses to
217      * probe for the device.
218      */
219     vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
220     qemu_fdt_add_subnode(fdt, "/apb-pclk");
221     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
222     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
223     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
224     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
225                                 "clk24mhz");
226     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
227 
228     if (have_numa_distance) {
229         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
230         uint32_t *matrix = g_malloc0(size);
231         int idx, i, j;
232 
233         for (i = 0; i < nb_numa_nodes; i++) {
234             for (j = 0; j < nb_numa_nodes; j++) {
235                 idx = (i * nb_numa_nodes + j) * 3;
236                 matrix[idx + 0] = cpu_to_be32(i);
237                 matrix[idx + 1] = cpu_to_be32(j);
238                 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
239             }
240         }
241 
242         qemu_fdt_add_subnode(fdt, "/distance-map");
243         qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
244                                 "numa-distance-map-v1");
245         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
246                          matrix, size);
247         g_free(matrix);
248     }
249 }
250 
251 static void fdt_add_timer_nodes(const VirtMachineState *vms)
252 {
253     /* On real hardware these interrupts are level-triggered.
254      * On KVM they were edge-triggered before host kernel version 4.4,
255      * and level-triggered afterwards.
256      * On emulated QEMU they are level-triggered.
257      *
258      * Getting the DTB info about them wrong is awkward for some
259      * guest kernels:
260      *  pre-4.8 ignore the DT and leave the interrupt configured
261      *   with whatever the GIC reset value (or the bootloader) left it at
262      *  4.8 before rc6 honour the incorrect data by programming it back
263      *   into the GIC, causing problems
264      *  4.8rc6 and later ignore the DT and always write "level triggered"
265      *   into the GIC
266      *
267      * For backwards-compatibility, virt-2.8 and earlier will continue
268      * to say these are edge-triggered, but later machines will report
269      * the correct information.
270      */
271     ARMCPU *armcpu;
272     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
273     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
274 
275     if (vmc->claim_edge_triggered_timers) {
276         irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
277     }
278 
279     if (vms->gic_version == 2) {
280         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
281                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
282                              (1 << vms->smp_cpus) - 1);
283     }
284 
285     qemu_fdt_add_subnode(vms->fdt, "/timer");
286 
287     armcpu = ARM_CPU(qemu_get_cpu(0));
288     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
289         const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
290         qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
291                          compat, sizeof(compat));
292     } else {
293         qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
294                                 "arm,armv7-timer");
295     }
296     qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
297     qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
298                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
299                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
300                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
301                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
302 }
303 
304 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
305 {
306     int cpu;
307     int addr_cells = 1;
308     const MachineState *ms = MACHINE(vms);
309 
310     /*
311      * From Documentation/devicetree/bindings/arm/cpus.txt
312      *  On ARM v8 64-bit systems value should be set to 2,
313      *  that corresponds to the MPIDR_EL1 register size.
314      *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
315      *  in the system, #address-cells can be set to 1, since
316      *  MPIDR_EL1[63:32] bits are not used for CPUs
317      *  identification.
318      *
319      *  Here we actually don't know whether our system is 32- or 64-bit one.
320      *  The simplest way to go is to examine affinity IDs of all our CPUs. If
321      *  at least one of them has Aff3 populated, we set #address-cells to 2.
322      */
323     for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
324         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
325 
326         if (armcpu->mp_affinity & ARM_AFF3_MASK) {
327             addr_cells = 2;
328             break;
329         }
330     }
331 
332     qemu_fdt_add_subnode(vms->fdt, "/cpus");
333     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
334     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
335 
336     for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
337         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
338         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
339         CPUState *cs = CPU(armcpu);
340 
341         qemu_fdt_add_subnode(vms->fdt, nodename);
342         qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
343         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
344                                     armcpu->dtb_compatible);
345 
346         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
347             && vms->smp_cpus > 1) {
348             qemu_fdt_setprop_string(vms->fdt, nodename,
349                                         "enable-method", "psci");
350         }
351 
352         if (addr_cells == 2) {
353             qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
354                                  armcpu->mp_affinity);
355         } else {
356             qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
357                                   armcpu->mp_affinity);
358         }
359 
360         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
361             qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
362                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
363         }
364 
365         g_free(nodename);
366     }
367 }
368 
369 static void fdt_add_its_gic_node(VirtMachineState *vms)
370 {
371     char *nodename;
372 
373     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
374     nodename = g_strdup_printf("/intc/its@%" PRIx64,
375                                vms->memmap[VIRT_GIC_ITS].base);
376     qemu_fdt_add_subnode(vms->fdt, nodename);
377     qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
378                             "arm,gic-v3-its");
379     qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
380     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
381                                  2, vms->memmap[VIRT_GIC_ITS].base,
382                                  2, vms->memmap[VIRT_GIC_ITS].size);
383     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
384     g_free(nodename);
385 }
386 
387 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
388 {
389     char *nodename;
390 
391     nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
392                                vms->memmap[VIRT_GIC_V2M].base);
393     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
394     qemu_fdt_add_subnode(vms->fdt, nodename);
395     qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
396                             "arm,gic-v2m-frame");
397     qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
398     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
399                                  2, vms->memmap[VIRT_GIC_V2M].base,
400                                  2, vms->memmap[VIRT_GIC_V2M].size);
401     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
402     g_free(nodename);
403 }
404 
405 static void fdt_add_gic_node(VirtMachineState *vms)
406 {
407     char *nodename;
408 
409     vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
410     qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
411 
412     nodename = g_strdup_printf("/intc@%" PRIx64,
413                                vms->memmap[VIRT_GIC_DIST].base);
414     qemu_fdt_add_subnode(vms->fdt, nodename);
415     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
416     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
417     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
418     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
419     qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
420     if (vms->gic_version == 3) {
421         int nb_redist_regions = virt_gicv3_redist_region_count(vms);
422 
423         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
424                                 "arm,gic-v3");
425 
426         qemu_fdt_setprop_cell(vms->fdt, nodename,
427                               "#redistributor-regions", nb_redist_regions);
428 
429         if (nb_redist_regions == 1) {
430             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
431                                          2, vms->memmap[VIRT_GIC_DIST].base,
432                                          2, vms->memmap[VIRT_GIC_DIST].size,
433                                          2, vms->memmap[VIRT_GIC_REDIST].base,
434                                          2, vms->memmap[VIRT_GIC_REDIST].size);
435         } else {
436             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
437                                  2, vms->memmap[VIRT_GIC_DIST].base,
438                                  2, vms->memmap[VIRT_GIC_DIST].size,
439                                  2, vms->memmap[VIRT_GIC_REDIST].base,
440                                  2, vms->memmap[VIRT_GIC_REDIST].size,
441                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
442                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
443         }
444 
445         if (vms->virt) {
446             qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
447                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
448                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
449         }
450     } else {
451         /* 'cortex-a15-gic' means 'GIC v2' */
452         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
453                                 "arm,cortex-a15-gic");
454         if (!vms->virt) {
455             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
456                                          2, vms->memmap[VIRT_GIC_DIST].base,
457                                          2, vms->memmap[VIRT_GIC_DIST].size,
458                                          2, vms->memmap[VIRT_GIC_CPU].base,
459                                          2, vms->memmap[VIRT_GIC_CPU].size);
460         } else {
461             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
462                                          2, vms->memmap[VIRT_GIC_DIST].base,
463                                          2, vms->memmap[VIRT_GIC_DIST].size,
464                                          2, vms->memmap[VIRT_GIC_CPU].base,
465                                          2, vms->memmap[VIRT_GIC_CPU].size,
466                                          2, vms->memmap[VIRT_GIC_HYP].base,
467                                          2, vms->memmap[VIRT_GIC_HYP].size,
468                                          2, vms->memmap[VIRT_GIC_VCPU].base,
469                                          2, vms->memmap[VIRT_GIC_VCPU].size);
470             qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
471                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
472                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
473         }
474     }
475 
476     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
477     g_free(nodename);
478 }
479 
480 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
481 {
482     CPUState *cpu;
483     ARMCPU *armcpu;
484     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
485 
486     CPU_FOREACH(cpu) {
487         armcpu = ARM_CPU(cpu);
488         if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
489             return;
490         }
491         if (kvm_enabled()) {
492             if (kvm_irqchip_in_kernel()) {
493                 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
494             }
495             kvm_arm_pmu_init(cpu);
496         }
497     }
498 
499     if (vms->gic_version == 2) {
500         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
501                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
502                              (1 << vms->smp_cpus) - 1);
503     }
504 
505     armcpu = ARM_CPU(qemu_get_cpu(0));
506     qemu_fdt_add_subnode(vms->fdt, "/pmu");
507     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
508         const char compat[] = "arm,armv8-pmuv3";
509         qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
510                          compat, sizeof(compat));
511         qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
512                                GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
513     }
514 }
515 
516 static void create_its(VirtMachineState *vms, DeviceState *gicdev)
517 {
518     const char *itsclass = its_class_name();
519     DeviceState *dev;
520 
521     if (!itsclass) {
522         /* Do nothing if not supported */
523         return;
524     }
525 
526     dev = qdev_create(NULL, itsclass);
527 
528     object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
529                              &error_abort);
530     qdev_init_nofail(dev);
531     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
532 
533     fdt_add_its_gic_node(vms);
534 }
535 
536 static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
537 {
538     int i;
539     int irq = vms->irqmap[VIRT_GIC_V2M];
540     DeviceState *dev;
541 
542     dev = qdev_create(NULL, "arm-gicv2m");
543     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
544     qdev_prop_set_uint32(dev, "base-spi", irq);
545     qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
546     qdev_init_nofail(dev);
547 
548     for (i = 0; i < NUM_GICV2M_SPIS; i++) {
549         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
550     }
551 
552     fdt_add_v2m_gic_node(vms);
553 }
554 
555 static void create_gic(VirtMachineState *vms, qemu_irq *pic)
556 {
557     /* We create a standalone GIC */
558     DeviceState *gicdev;
559     SysBusDevice *gicbusdev;
560     const char *gictype;
561     int type = vms->gic_version, i;
562     uint32_t nb_redist_regions = 0;
563 
564     gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
565 
566     gicdev = qdev_create(NULL, gictype);
567     qdev_prop_set_uint32(gicdev, "revision", type);
568     qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
569     /* Note that the num-irq property counts both internal and external
570      * interrupts; there are always 32 of the former (mandated by GIC spec).
571      */
572     qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
573     if (!kvm_irqchip_in_kernel()) {
574         qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
575     }
576 
577     if (type == 3) {
578         uint32_t redist0_capacity =
579                     vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
580         uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
581 
582         nb_redist_regions = virt_gicv3_redist_region_count(vms);
583 
584         qdev_prop_set_uint32(gicdev, "len-redist-region-count",
585                              nb_redist_regions);
586         qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
587 
588         if (nb_redist_regions == 2) {
589             uint32_t redist1_capacity =
590                     vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
591 
592             qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
593                 MIN(smp_cpus - redist0_count, redist1_capacity));
594         }
595     } else {
596         if (!kvm_irqchip_in_kernel()) {
597             qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
598                               vms->virt);
599         }
600     }
601     qdev_init_nofail(gicdev);
602     gicbusdev = SYS_BUS_DEVICE(gicdev);
603     sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
604     if (type == 3) {
605         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
606         if (nb_redist_regions == 2) {
607             sysbus_mmio_map(gicbusdev, 2,
608                             vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
609         }
610     } else {
611         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
612         if (vms->virt) {
613             sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
614             sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
615         }
616     }
617 
618     /* Wire the outputs from each CPU's generic timer and the GICv3
619      * maintenance interrupt signal to the appropriate GIC PPI inputs,
620      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
621      */
622     for (i = 0; i < smp_cpus; i++) {
623         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
624         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
625         int irq;
626         /* Mapping from the output timer irq lines from the CPU to the
627          * GIC PPI inputs we use for the virt board.
628          */
629         const int timer_irq[] = {
630             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
631             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
632             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
633             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
634         };
635 
636         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
637             qdev_connect_gpio_out(cpudev, irq,
638                                   qdev_get_gpio_in(gicdev,
639                                                    ppibase + timer_irq[irq]));
640         }
641 
642         if (type == 3) {
643             qemu_irq irq = qdev_get_gpio_in(gicdev,
644                                             ppibase + ARCH_GIC_MAINT_IRQ);
645             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
646                                         0, irq);
647         } else if (vms->virt) {
648             qemu_irq irq = qdev_get_gpio_in(gicdev,
649                                             ppibase + ARCH_GIC_MAINT_IRQ);
650             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
651         }
652 
653         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
654                                     qdev_get_gpio_in(gicdev, ppibase
655                                                      + VIRTUAL_PMU_IRQ));
656 
657         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
658         sysbus_connect_irq(gicbusdev, i + smp_cpus,
659                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
660         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
661                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
662         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
663                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
664     }
665 
666     for (i = 0; i < NUM_IRQS; i++) {
667         pic[i] = qdev_get_gpio_in(gicdev, i);
668     }
669 
670     fdt_add_gic_node(vms);
671 
672     if (type == 3 && vms->its) {
673         create_its(vms, gicdev);
674     } else if (type == 2) {
675         create_v2m(vms, pic);
676     }
677 }
678 
679 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
680                         MemoryRegion *mem, Chardev *chr)
681 {
682     char *nodename;
683     hwaddr base = vms->memmap[uart].base;
684     hwaddr size = vms->memmap[uart].size;
685     int irq = vms->irqmap[uart];
686     const char compat[] = "arm,pl011\0arm,primecell";
687     const char clocknames[] = "uartclk\0apb_pclk";
688     DeviceState *dev = qdev_create(NULL, "pl011");
689     SysBusDevice *s = SYS_BUS_DEVICE(dev);
690 
691     qdev_prop_set_chr(dev, "chardev", chr);
692     qdev_init_nofail(dev);
693     memory_region_add_subregion(mem, base,
694                                 sysbus_mmio_get_region(s, 0));
695     sysbus_connect_irq(s, 0, pic[irq]);
696 
697     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
698     qemu_fdt_add_subnode(vms->fdt, nodename);
699     /* Note that we can't use setprop_string because of the embedded NUL */
700     qemu_fdt_setprop(vms->fdt, nodename, "compatible",
701                          compat, sizeof(compat));
702     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
703                                      2, base, 2, size);
704     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
705                                GIC_FDT_IRQ_TYPE_SPI, irq,
706                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
707     qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
708                                vms->clock_phandle, vms->clock_phandle);
709     qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
710                          clocknames, sizeof(clocknames));
711 
712     if (uart == VIRT_UART) {
713         qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
714     } else {
715         /* Mark as not usable by the normal world */
716         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
717         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
718 
719         qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
720         qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
721                                 nodename);
722     }
723 
724     g_free(nodename);
725 }
726 
727 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
728 {
729     char *nodename;
730     hwaddr base = vms->memmap[VIRT_RTC].base;
731     hwaddr size = vms->memmap[VIRT_RTC].size;
732     int irq = vms->irqmap[VIRT_RTC];
733     const char compat[] = "arm,pl031\0arm,primecell";
734 
735     sysbus_create_simple("pl031", base, pic[irq]);
736 
737     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
738     qemu_fdt_add_subnode(vms->fdt, nodename);
739     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
740     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
741                                  2, base, 2, size);
742     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
743                            GIC_FDT_IRQ_TYPE_SPI, irq,
744                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
745     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
746     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
747     g_free(nodename);
748 }
749 
750 static DeviceState *gpio_key_dev;
751 static void virt_powerdown_req(Notifier *n, void *opaque)
752 {
753     /* use gpio Pin 3 for power button event */
754     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
755 }
756 
757 static Notifier virt_system_powerdown_notifier = {
758     .notify = virt_powerdown_req
759 };
760 
761 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
762 {
763     char *nodename;
764     DeviceState *pl061_dev;
765     hwaddr base = vms->memmap[VIRT_GPIO].base;
766     hwaddr size = vms->memmap[VIRT_GPIO].size;
767     int irq = vms->irqmap[VIRT_GPIO];
768     const char compat[] = "arm,pl061\0arm,primecell";
769 
770     pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
771 
772     uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
773     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
774     qemu_fdt_add_subnode(vms->fdt, nodename);
775     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
776                                  2, base, 2, size);
777     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
778     qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
779     qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
780     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
781                            GIC_FDT_IRQ_TYPE_SPI, irq,
782                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
783     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
784     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
785     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
786 
787     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
788                                         qdev_get_gpio_in(pl061_dev, 3));
789     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
790     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
791     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
792     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
793 
794     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
795     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
796                             "label", "GPIO Key Poweroff");
797     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
798                           KEY_POWER);
799     qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
800                            "gpios", phandle, 3, 0);
801 
802     /* connect powerdown request */
803     qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
804 
805     g_free(nodename);
806 }
807 
808 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
809 {
810     int i;
811     hwaddr size = vms->memmap[VIRT_MMIO].size;
812 
813     /* We create the transports in forwards order. Since qbus_realize()
814      * prepends (not appends) new child buses, the incrementing loop below will
815      * create a list of virtio-mmio buses with decreasing base addresses.
816      *
817      * When a -device option is processed from the command line,
818      * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
819      * order. The upshot is that -device options in increasing command line
820      * order are mapped to virtio-mmio buses with decreasing base addresses.
821      *
822      * When this code was originally written, that arrangement ensured that the
823      * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
824      * the first -device on the command line. (The end-to-end order is a
825      * function of this loop, qbus_realize(), qbus_find_recursive(), and the
826      * guest kernel's name-to-address assignment strategy.)
827      *
828      * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
829      * the message, if not necessarily the code, of commit 70161ff336.
830      * Therefore the loop now establishes the inverse of the original intent.
831      *
832      * Unfortunately, we can't counteract the kernel change by reversing the
833      * loop; it would break existing command lines.
834      *
835      * In any case, the kernel makes no guarantee about the stability of
836      * enumeration order of virtio devices (as demonstrated by it changing
837      * between kernel versions). For reliable and stable identification
838      * of disks users must use UUIDs or similar mechanisms.
839      */
840     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
841         int irq = vms->irqmap[VIRT_MMIO] + i;
842         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
843 
844         sysbus_create_simple("virtio-mmio", base, pic[irq]);
845     }
846 
847     /* We add dtb nodes in reverse order so that they appear in the finished
848      * device tree lowest address first.
849      *
850      * Note that this mapping is independent of the loop above. The previous
851      * loop influences virtio device to virtio transport assignment, whereas
852      * this loop controls how virtio transports are laid out in the dtb.
853      */
854     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
855         char *nodename;
856         int irq = vms->irqmap[VIRT_MMIO] + i;
857         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
858 
859         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
860         qemu_fdt_add_subnode(vms->fdt, nodename);
861         qemu_fdt_setprop_string(vms->fdt, nodename,
862                                 "compatible", "virtio,mmio");
863         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
864                                      2, base, 2, size);
865         qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
866                                GIC_FDT_IRQ_TYPE_SPI, irq,
867                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
868         qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
869         g_free(nodename);
870     }
871 }
872 
873 static void create_one_flash(const char *name, hwaddr flashbase,
874                              hwaddr flashsize, const char *file,
875                              MemoryRegion *sysmem)
876 {
877     /* Create and map a single flash device. We use the same
878      * parameters as the flash devices on the Versatile Express board.
879      */
880     DriveInfo *dinfo = drive_get_next(IF_PFLASH);
881     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
882     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
883     const uint64_t sectorlength = 256 * 1024;
884 
885     if (dinfo) {
886         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
887                             &error_abort);
888     }
889 
890     qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
891     qdev_prop_set_uint64(dev, "sector-length", sectorlength);
892     qdev_prop_set_uint8(dev, "width", 4);
893     qdev_prop_set_uint8(dev, "device-width", 2);
894     qdev_prop_set_bit(dev, "big-endian", false);
895     qdev_prop_set_uint16(dev, "id0", 0x89);
896     qdev_prop_set_uint16(dev, "id1", 0x18);
897     qdev_prop_set_uint16(dev, "id2", 0x00);
898     qdev_prop_set_uint16(dev, "id3", 0x00);
899     qdev_prop_set_string(dev, "name", name);
900     qdev_init_nofail(dev);
901 
902     memory_region_add_subregion(sysmem, flashbase,
903                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
904 
905     if (file) {
906         char *fn;
907         int image_size;
908 
909         if (drive_get(IF_PFLASH, 0, 0)) {
910             error_report("The contents of the first flash device may be "
911                          "specified with -bios or with -drive if=pflash... "
912                          "but you cannot use both options at once");
913             exit(1);
914         }
915         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
916         if (!fn) {
917             error_report("Could not find ROM image '%s'", file);
918             exit(1);
919         }
920         image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
921         g_free(fn);
922         if (image_size < 0) {
923             error_report("Could not load ROM image '%s'", file);
924             exit(1);
925         }
926     }
927 }
928 
929 static void create_flash(const VirtMachineState *vms,
930                          MemoryRegion *sysmem,
931                          MemoryRegion *secure_sysmem)
932 {
933     /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
934      * Any file passed via -bios goes in the first of these.
935      * sysmem is the system memory space. secure_sysmem is the secure view
936      * of the system, and the first flash device should be made visible only
937      * there. The second flash device is visible to both secure and nonsecure.
938      * If sysmem == secure_sysmem this means there is no separate Secure
939      * address space and both flash devices are generally visible.
940      */
941     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
942     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
943     char *nodename;
944 
945     create_one_flash("virt.flash0", flashbase, flashsize,
946                      bios_name, secure_sysmem);
947     create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
948                      NULL, sysmem);
949 
950     if (sysmem == secure_sysmem) {
951         /* Report both flash devices as a single node in the DT */
952         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
953         qemu_fdt_add_subnode(vms->fdt, nodename);
954         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
955         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
956                                      2, flashbase, 2, flashsize,
957                                      2, flashbase + flashsize, 2, flashsize);
958         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
959         g_free(nodename);
960     } else {
961         /* Report the devices as separate nodes so we can mark one as
962          * only visible to the secure world.
963          */
964         nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
965         qemu_fdt_add_subnode(vms->fdt, nodename);
966         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
967         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
968                                      2, flashbase, 2, flashsize);
969         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
970         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
971         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
972         g_free(nodename);
973 
974         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
975         qemu_fdt_add_subnode(vms->fdt, nodename);
976         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
977         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
978                                      2, flashbase + flashsize, 2, flashsize);
979         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
980         g_free(nodename);
981     }
982 }
983 
984 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
985 {
986     hwaddr base = vms->memmap[VIRT_FW_CFG].base;
987     hwaddr size = vms->memmap[VIRT_FW_CFG].size;
988     FWCfgState *fw_cfg;
989     char *nodename;
990 
991     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
992     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
993 
994     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
995     qemu_fdt_add_subnode(vms->fdt, nodename);
996     qemu_fdt_setprop_string(vms->fdt, nodename,
997                             "compatible", "qemu,fw-cfg-mmio");
998     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
999                                  2, base, 2, size);
1000     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1001     g_free(nodename);
1002     return fw_cfg;
1003 }
1004 
1005 static void create_pcie_irq_map(const VirtMachineState *vms,
1006                                 uint32_t gic_phandle,
1007                                 int first_irq, const char *nodename)
1008 {
1009     int devfn, pin;
1010     uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1011     uint32_t *irq_map = full_irq_map;
1012 
1013     for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1014         for (pin = 0; pin < 4; pin++) {
1015             int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1016             int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1017             int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1018             int i;
1019 
1020             uint32_t map[] = {
1021                 devfn << 8, 0, 0,                           /* devfn */
1022                 pin + 1,                                    /* PCI pin */
1023                 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1024 
1025             /* Convert map to big endian */
1026             for (i = 0; i < 10; i++) {
1027                 irq_map[i] = cpu_to_be32(map[i]);
1028             }
1029             irq_map += 10;
1030         }
1031     }
1032 
1033     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1034                      full_irq_map, sizeof(full_irq_map));
1035 
1036     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1037                            0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1038                            0x7           /* PCI irq */);
1039 }
1040 
1041 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1042                         PCIBus *bus)
1043 {
1044     char *node;
1045     const char compat[] = "arm,smmu-v3";
1046     int irq =  vms->irqmap[VIRT_SMMU];
1047     int i;
1048     hwaddr base = vms->memmap[VIRT_SMMU].base;
1049     hwaddr size = vms->memmap[VIRT_SMMU].size;
1050     const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1051     DeviceState *dev;
1052 
1053     if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1054         return;
1055     }
1056 
1057     dev = qdev_create(NULL, "arm-smmuv3");
1058 
1059     object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1060                              &error_abort);
1061     qdev_init_nofail(dev);
1062     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1063     for (i = 0; i < NUM_SMMU_IRQS; i++) {
1064         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1065     }
1066 
1067     node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1068     qemu_fdt_add_subnode(vms->fdt, node);
1069     qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1070     qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1071 
1072     qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1073             GIC_FDT_IRQ_TYPE_SPI, irq    , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1074             GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1075             GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1076             GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1077 
1078     qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1079                      sizeof(irq_names));
1080 
1081     qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1082     qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1083     qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1084 
1085     qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1086 
1087     qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1088     g_free(node);
1089 }
1090 
1091 static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1092 {
1093     hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1094     hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1095     hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1096     hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1097     hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1098     hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1099     hwaddr base_ecam, size_ecam;
1100     hwaddr base = base_mmio;
1101     int nr_pcie_buses;
1102     int irq = vms->irqmap[VIRT_PCIE];
1103     MemoryRegion *mmio_alias;
1104     MemoryRegion *mmio_reg;
1105     MemoryRegion *ecam_alias;
1106     MemoryRegion *ecam_reg;
1107     DeviceState *dev;
1108     char *nodename;
1109     int i, ecam_id;
1110     PCIHostState *pci;
1111 
1112     dev = qdev_create(NULL, TYPE_GPEX_HOST);
1113     qdev_init_nofail(dev);
1114 
1115     ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1116     base_ecam = vms->memmap[ecam_id].base;
1117     size_ecam = vms->memmap[ecam_id].size;
1118     nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1119     /* Map only the first size_ecam bytes of ECAM space */
1120     ecam_alias = g_new0(MemoryRegion, 1);
1121     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1122     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1123                              ecam_reg, 0, size_ecam);
1124     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1125 
1126     /* Map the MMIO window into system address space so as to expose
1127      * the section of PCI MMIO space which starts at the same base address
1128      * (ie 1:1 mapping for that part of PCI MMIO space visible through
1129      * the window).
1130      */
1131     mmio_alias = g_new0(MemoryRegion, 1);
1132     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1133     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1134                              mmio_reg, base_mmio, size_mmio);
1135     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1136 
1137     if (vms->highmem) {
1138         /* Map high MMIO space */
1139         MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1140 
1141         memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1142                                  mmio_reg, base_mmio_high, size_mmio_high);
1143         memory_region_add_subregion(get_system_memory(), base_mmio_high,
1144                                     high_mmio_alias);
1145     }
1146 
1147     /* Map IO port space */
1148     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1149 
1150     for (i = 0; i < GPEX_NUM_IRQS; i++) {
1151         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1152         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1153     }
1154 
1155     pci = PCI_HOST_BRIDGE(dev);
1156     if (pci->bus) {
1157         for (i = 0; i < nb_nics; i++) {
1158             NICInfo *nd = &nd_table[i];
1159 
1160             if (!nd->model) {
1161                 nd->model = g_strdup("virtio");
1162             }
1163 
1164             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1165         }
1166     }
1167 
1168     nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1169     qemu_fdt_add_subnode(vms->fdt, nodename);
1170     qemu_fdt_setprop_string(vms->fdt, nodename,
1171                             "compatible", "pci-host-ecam-generic");
1172     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1173     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1174     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1175     qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1176     qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1177                            nr_pcie_buses - 1);
1178     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1179 
1180     if (vms->msi_phandle) {
1181         qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1182                                vms->msi_phandle);
1183     }
1184 
1185     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1186                                  2, base_ecam, 2, size_ecam);
1187 
1188     if (vms->highmem) {
1189         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1190                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1191                                      2, base_pio, 2, size_pio,
1192                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1193                                      2, base_mmio, 2, size_mmio,
1194                                      1, FDT_PCI_RANGE_MMIO_64BIT,
1195                                      2, base_mmio_high,
1196                                      2, base_mmio_high, 2, size_mmio_high);
1197     } else {
1198         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1199                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1200                                      2, base_pio, 2, size_pio,
1201                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1202                                      2, base_mmio, 2, size_mmio);
1203     }
1204 
1205     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1206     create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1207 
1208     if (vms->iommu) {
1209         vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1210 
1211         create_smmu(vms, pic, pci->bus);
1212 
1213         qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1214                                0x0, vms->iommu_phandle, 0x0, 0x10000);
1215     }
1216 
1217     g_free(nodename);
1218 }
1219 
1220 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1221 {
1222     DeviceState *dev;
1223     SysBusDevice *s;
1224     int i;
1225     MemoryRegion *sysmem = get_system_memory();
1226 
1227     dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1228     dev->id = TYPE_PLATFORM_BUS_DEVICE;
1229     qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1230     qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1231     qdev_init_nofail(dev);
1232     vms->platform_bus_dev = dev;
1233 
1234     s = SYS_BUS_DEVICE(dev);
1235     for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1236         int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1237         sysbus_connect_irq(s, i, pic[irqn]);
1238     }
1239 
1240     memory_region_add_subregion(sysmem,
1241                                 vms->memmap[VIRT_PLATFORM_BUS].base,
1242                                 sysbus_mmio_get_region(s, 0));
1243 }
1244 
1245 static void create_secure_ram(VirtMachineState *vms,
1246                               MemoryRegion *secure_sysmem)
1247 {
1248     MemoryRegion *secram = g_new(MemoryRegion, 1);
1249     char *nodename;
1250     hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1251     hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1252 
1253     memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1254                            &error_fatal);
1255     memory_region_add_subregion(secure_sysmem, base, secram);
1256 
1257     nodename = g_strdup_printf("/secram@%" PRIx64, base);
1258     qemu_fdt_add_subnode(vms->fdt, nodename);
1259     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1260     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1261     qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1262     qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1263 
1264     g_free(nodename);
1265 }
1266 
1267 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1268 {
1269     const VirtMachineState *board = container_of(binfo, VirtMachineState,
1270                                                  bootinfo);
1271 
1272     *fdt_size = board->fdt_size;
1273     return board->fdt;
1274 }
1275 
1276 static void virt_build_smbios(VirtMachineState *vms)
1277 {
1278     MachineClass *mc = MACHINE_GET_CLASS(vms);
1279     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1280     uint8_t *smbios_tables, *smbios_anchor;
1281     size_t smbios_tables_len, smbios_anchor_len;
1282     const char *product = "QEMU Virtual Machine";
1283 
1284     if (!vms->fw_cfg) {
1285         return;
1286     }
1287 
1288     if (kvm_enabled()) {
1289         product = "KVM Virtual Machine";
1290     }
1291 
1292     smbios_set_defaults("QEMU", product,
1293                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1294                         true, SMBIOS_ENTRY_POINT_30);
1295 
1296     smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
1297                       &smbios_anchor, &smbios_anchor_len);
1298 
1299     if (smbios_anchor) {
1300         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1301                         smbios_tables, smbios_tables_len);
1302         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1303                         smbios_anchor, smbios_anchor_len);
1304     }
1305 }
1306 
1307 static
1308 void virt_machine_done(Notifier *notifier, void *data)
1309 {
1310     VirtMachineState *vms = container_of(notifier, VirtMachineState,
1311                                          machine_done);
1312     ARMCPU *cpu = ARM_CPU(first_cpu);
1313     struct arm_boot_info *info = &vms->bootinfo;
1314     AddressSpace *as = arm_boot_address_space(cpu, info);
1315 
1316     /*
1317      * If the user provided a dtb, we assume the dynamic sysbus nodes
1318      * already are integrated there. This corresponds to a use case where
1319      * the dynamic sysbus nodes are complex and their generation is not yet
1320      * supported. In that case the user can take charge of the guest dt
1321      * while qemu takes charge of the qom stuff.
1322      */
1323     if (info->dtb_filename == NULL) {
1324         platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1325                                        vms->memmap[VIRT_PLATFORM_BUS].base,
1326                                        vms->memmap[VIRT_PLATFORM_BUS].size,
1327                                        vms->irqmap[VIRT_PLATFORM_BUS]);
1328     }
1329     if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1330         exit(1);
1331     }
1332 
1333     virt_acpi_setup(vms);
1334     virt_build_smbios(vms);
1335 }
1336 
1337 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1338 {
1339     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1340     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1341 
1342     if (!vmc->disallow_affinity_adjustment) {
1343         /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1344          * GIC's target-list limitations. 32-bit KVM hosts currently
1345          * always create clusters of 4 CPUs, but that is expected to
1346          * change when they gain support for gicv3. When KVM is enabled
1347          * it will override the changes we make here, therefore our
1348          * purposes are to make TCG consistent (with 64-bit KVM hosts)
1349          * and to improve SGI efficiency.
1350          */
1351         if (vms->gic_version == 3) {
1352             clustersz = GICV3_TARGETLIST_BITS;
1353         } else {
1354             clustersz = GIC_TARGETLIST_BITS;
1355         }
1356     }
1357     return arm_cpu_mp_affinity(idx, clustersz);
1358 }
1359 
1360 static void virt_set_memmap(VirtMachineState *vms)
1361 {
1362     MachineState *ms = MACHINE(vms);
1363     hwaddr base, device_memory_base, device_memory_size;
1364     int i;
1365 
1366     vms->memmap = extended_memmap;
1367 
1368     for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1369         vms->memmap[i] = base_memmap[i];
1370     }
1371 
1372     if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1373         error_report("unsupported number of memory slots: %"PRIu64,
1374                      ms->ram_slots);
1375         exit(EXIT_FAILURE);
1376     }
1377 
1378     /*
1379      * We compute the base of the high IO region depending on the
1380      * amount of initial and device memory. The device memory start/size
1381      * is aligned on 1GiB. We never put the high IO region below 256GiB
1382      * so that if maxram_size is < 255GiB we keep the legacy memory map.
1383      * The device region size assumes 1GiB page max alignment per slot.
1384      */
1385     device_memory_base =
1386         ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1387     device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1388 
1389     /* Base address of the high IO region */
1390     base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1391     if (base < device_memory_base) {
1392         error_report("maxmem/slots too huge");
1393         exit(EXIT_FAILURE);
1394     }
1395     if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1396         base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1397     }
1398 
1399     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1400         hwaddr size = extended_memmap[i].size;
1401 
1402         base = ROUND_UP(base, size);
1403         vms->memmap[i].base = base;
1404         vms->memmap[i].size = size;
1405         base += size;
1406     }
1407     vms->highest_gpa = base - 1;
1408     if (device_memory_size > 0) {
1409         ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1410         ms->device_memory->base = device_memory_base;
1411         memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1412                            "device-memory", device_memory_size);
1413     }
1414 }
1415 
1416 static void machvirt_init(MachineState *machine)
1417 {
1418     VirtMachineState *vms = VIRT_MACHINE(machine);
1419     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1420     MachineClass *mc = MACHINE_GET_CLASS(machine);
1421     const CPUArchIdList *possible_cpus;
1422     qemu_irq pic[NUM_IRQS];
1423     MemoryRegion *sysmem = get_system_memory();
1424     MemoryRegion *secure_sysmem = NULL;
1425     int n, virt_max_cpus;
1426     MemoryRegion *ram = g_new(MemoryRegion, 1);
1427     bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1428     bool aarch64 = true;
1429 
1430     /*
1431      * In accelerated mode, the memory map is computed earlier in kvm_type()
1432      * to create a VM with the right number of IPA bits.
1433      */
1434     if (!vms->memmap) {
1435         virt_set_memmap(vms);
1436     }
1437 
1438     /* We can probe only here because during property set
1439      * KVM is not available yet
1440      */
1441     if (vms->gic_version <= 0) {
1442         /* "host" or "max" */
1443         if (!kvm_enabled()) {
1444             if (vms->gic_version == 0) {
1445                 error_report("gic-version=host requires KVM");
1446                 exit(1);
1447             } else {
1448                 /* "max": currently means 3 for TCG */
1449                 vms->gic_version = 3;
1450             }
1451         } else {
1452             vms->gic_version = kvm_arm_vgic_probe();
1453             if (!vms->gic_version) {
1454                 error_report(
1455                     "Unable to determine GIC version supported by host");
1456                 exit(1);
1457             }
1458         }
1459     }
1460 
1461     if (!cpu_type_valid(machine->cpu_type)) {
1462         error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1463         exit(1);
1464     }
1465 
1466     /* If we have an EL3 boot ROM then the assumption is that it will
1467      * implement PSCI itself, so disable QEMU's internal implementation
1468      * so it doesn't get in the way. Instead of starting secondary
1469      * CPUs in PSCI powerdown state we will start them all running and
1470      * let the boot ROM sort them out.
1471      * The usual case is that we do use QEMU's PSCI implementation;
1472      * if the guest has EL2 then we will use SMC as the conduit,
1473      * and otherwise we will use HVC (for backwards compatibility and
1474      * because if we're using KVM then we must use HVC).
1475      */
1476     if (vms->secure && firmware_loaded) {
1477         vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1478     } else if (vms->virt) {
1479         vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1480     } else {
1481         vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1482     }
1483 
1484     /* The maximum number of CPUs depends on the GIC version, or on how
1485      * many redistributors we can fit into the memory map.
1486      */
1487     if (vms->gic_version == 3) {
1488         virt_max_cpus =
1489             vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1490         virt_max_cpus +=
1491             vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1492     } else {
1493         virt_max_cpus = GIC_NCPU;
1494     }
1495 
1496     if (max_cpus > virt_max_cpus) {
1497         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1498                      "supported by machine 'mach-virt' (%d)",
1499                      max_cpus, virt_max_cpus);
1500         exit(1);
1501     }
1502 
1503     vms->smp_cpus = smp_cpus;
1504 
1505     if (vms->virt && kvm_enabled()) {
1506         error_report("mach-virt: KVM does not support providing "
1507                      "Virtualization extensions to the guest CPU");
1508         exit(1);
1509     }
1510 
1511     if (vms->secure) {
1512         if (kvm_enabled()) {
1513             error_report("mach-virt: KVM does not support Security extensions");
1514             exit(1);
1515         }
1516 
1517         /* The Secure view of the world is the same as the NonSecure,
1518          * but with a few extra devices. Create it as a container region
1519          * containing the system memory at low priority; any secure-only
1520          * devices go in at higher priority and take precedence.
1521          */
1522         secure_sysmem = g_new(MemoryRegion, 1);
1523         memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1524                            UINT64_MAX);
1525         memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1526     }
1527 
1528     create_fdt(vms);
1529 
1530     possible_cpus = mc->possible_cpu_arch_ids(machine);
1531     for (n = 0; n < possible_cpus->len; n++) {
1532         Object *cpuobj;
1533         CPUState *cs;
1534 
1535         if (n >= smp_cpus) {
1536             break;
1537         }
1538 
1539         cpuobj = object_new(possible_cpus->cpus[n].type);
1540         object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1541                                 "mp-affinity", NULL);
1542 
1543         cs = CPU(cpuobj);
1544         cs->cpu_index = n;
1545 
1546         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1547                           &error_fatal);
1548 
1549         aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1550 
1551         if (!vms->secure) {
1552             object_property_set_bool(cpuobj, false, "has_el3", NULL);
1553         }
1554 
1555         if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1556             object_property_set_bool(cpuobj, false, "has_el2", NULL);
1557         }
1558 
1559         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1560             object_property_set_int(cpuobj, vms->psci_conduit,
1561                                     "psci-conduit", NULL);
1562 
1563             /* Secondary CPUs start in PSCI powered-down state */
1564             if (n > 0) {
1565                 object_property_set_bool(cpuobj, true,
1566                                          "start-powered-off", NULL);
1567             }
1568         }
1569 
1570         if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1571             object_property_set_bool(cpuobj, false, "pmu", NULL);
1572         }
1573 
1574         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1575             object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1576                                     "reset-cbar", &error_abort);
1577         }
1578 
1579         object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1580                                  &error_abort);
1581         if (vms->secure) {
1582             object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1583                                      "secure-memory", &error_abort);
1584         }
1585 
1586         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1587         object_unref(cpuobj);
1588     }
1589     fdt_add_timer_nodes(vms);
1590     fdt_add_cpu_nodes(vms);
1591 
1592    if (!kvm_enabled()) {
1593         ARMCPU *cpu = ARM_CPU(first_cpu);
1594         bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1595 
1596         if (aarch64 && vms->highmem) {
1597             int requested_pa_size, pamax = arm_pamax(cpu);
1598 
1599             requested_pa_size = 64 - clz64(vms->highest_gpa);
1600             if (pamax < requested_pa_size) {
1601                 error_report("VCPU supports less PA bits (%d) than requested "
1602                             "by the memory map (%d)", pamax, requested_pa_size);
1603                 exit(1);
1604             }
1605         }
1606     }
1607 
1608     memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1609                                          machine->ram_size);
1610     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1611     if (machine->device_memory) {
1612         memory_region_add_subregion(sysmem, machine->device_memory->base,
1613                                     &machine->device_memory->mr);
1614     }
1615 
1616     create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
1617 
1618     create_gic(vms, pic);
1619 
1620     fdt_add_pmu_nodes(vms);
1621 
1622     create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1623 
1624     if (vms->secure) {
1625         create_secure_ram(vms, secure_sysmem);
1626         create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1627     }
1628 
1629     vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1630 
1631     create_rtc(vms, pic);
1632 
1633     create_pcie(vms, pic);
1634 
1635     create_gpio(vms, pic);
1636 
1637     /* Create mmio transports, so the user can create virtio backends
1638      * (which will be automatically plugged in to the transports). If
1639      * no backend is created the transport will just sit harmlessly idle.
1640      */
1641     create_virtio_devices(vms, pic);
1642 
1643     vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1644     rom_set_fw(vms->fw_cfg);
1645 
1646     create_platform_bus(vms, pic);
1647 
1648     vms->bootinfo.ram_size = machine->ram_size;
1649     vms->bootinfo.kernel_filename = machine->kernel_filename;
1650     vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1651     vms->bootinfo.initrd_filename = machine->initrd_filename;
1652     vms->bootinfo.nb_cpus = smp_cpus;
1653     vms->bootinfo.board_id = -1;
1654     vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1655     vms->bootinfo.get_dtb = machvirt_dtb;
1656     vms->bootinfo.skip_dtb_autoload = true;
1657     vms->bootinfo.firmware_loaded = firmware_loaded;
1658     arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1659 
1660     vms->machine_done.notify = virt_machine_done;
1661     qemu_add_machine_init_done_notifier(&vms->machine_done);
1662 }
1663 
1664 static bool virt_get_secure(Object *obj, Error **errp)
1665 {
1666     VirtMachineState *vms = VIRT_MACHINE(obj);
1667 
1668     return vms->secure;
1669 }
1670 
1671 static void virt_set_secure(Object *obj, bool value, Error **errp)
1672 {
1673     VirtMachineState *vms = VIRT_MACHINE(obj);
1674 
1675     vms->secure = value;
1676 }
1677 
1678 static bool virt_get_virt(Object *obj, Error **errp)
1679 {
1680     VirtMachineState *vms = VIRT_MACHINE(obj);
1681 
1682     return vms->virt;
1683 }
1684 
1685 static void virt_set_virt(Object *obj, bool value, Error **errp)
1686 {
1687     VirtMachineState *vms = VIRT_MACHINE(obj);
1688 
1689     vms->virt = value;
1690 }
1691 
1692 static bool virt_get_highmem(Object *obj, Error **errp)
1693 {
1694     VirtMachineState *vms = VIRT_MACHINE(obj);
1695 
1696     return vms->highmem;
1697 }
1698 
1699 static void virt_set_highmem(Object *obj, bool value, Error **errp)
1700 {
1701     VirtMachineState *vms = VIRT_MACHINE(obj);
1702 
1703     vms->highmem = value;
1704 }
1705 
1706 static bool virt_get_its(Object *obj, Error **errp)
1707 {
1708     VirtMachineState *vms = VIRT_MACHINE(obj);
1709 
1710     return vms->its;
1711 }
1712 
1713 static void virt_set_its(Object *obj, bool value, Error **errp)
1714 {
1715     VirtMachineState *vms = VIRT_MACHINE(obj);
1716 
1717     vms->its = value;
1718 }
1719 
1720 static char *virt_get_gic_version(Object *obj, Error **errp)
1721 {
1722     VirtMachineState *vms = VIRT_MACHINE(obj);
1723     const char *val = vms->gic_version == 3 ? "3" : "2";
1724 
1725     return g_strdup(val);
1726 }
1727 
1728 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1729 {
1730     VirtMachineState *vms = VIRT_MACHINE(obj);
1731 
1732     if (!strcmp(value, "3")) {
1733         vms->gic_version = 3;
1734     } else if (!strcmp(value, "2")) {
1735         vms->gic_version = 2;
1736     } else if (!strcmp(value, "host")) {
1737         vms->gic_version = 0; /* Will probe later */
1738     } else if (!strcmp(value, "max")) {
1739         vms->gic_version = -1; /* Will probe later */
1740     } else {
1741         error_setg(errp, "Invalid gic-version value");
1742         error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1743     }
1744 }
1745 
1746 static char *virt_get_iommu(Object *obj, Error **errp)
1747 {
1748     VirtMachineState *vms = VIRT_MACHINE(obj);
1749 
1750     switch (vms->iommu) {
1751     case VIRT_IOMMU_NONE:
1752         return g_strdup("none");
1753     case VIRT_IOMMU_SMMUV3:
1754         return g_strdup("smmuv3");
1755     default:
1756         g_assert_not_reached();
1757     }
1758 }
1759 
1760 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1761 {
1762     VirtMachineState *vms = VIRT_MACHINE(obj);
1763 
1764     if (!strcmp(value, "smmuv3")) {
1765         vms->iommu = VIRT_IOMMU_SMMUV3;
1766     } else if (!strcmp(value, "none")) {
1767         vms->iommu = VIRT_IOMMU_NONE;
1768     } else {
1769         error_setg(errp, "Invalid iommu value");
1770         error_append_hint(errp, "Valid values are none, smmuv3.\n");
1771     }
1772 }
1773 
1774 static CpuInstanceProperties
1775 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1776 {
1777     MachineClass *mc = MACHINE_GET_CLASS(ms);
1778     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1779 
1780     assert(cpu_index < possible_cpus->len);
1781     return possible_cpus->cpus[cpu_index].props;
1782 }
1783 
1784 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1785 {
1786     return idx % nb_numa_nodes;
1787 }
1788 
1789 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1790 {
1791     int n;
1792     VirtMachineState *vms = VIRT_MACHINE(ms);
1793 
1794     if (ms->possible_cpus) {
1795         assert(ms->possible_cpus->len == max_cpus);
1796         return ms->possible_cpus;
1797     }
1798 
1799     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1800                                   sizeof(CPUArchId) * max_cpus);
1801     ms->possible_cpus->len = max_cpus;
1802     for (n = 0; n < ms->possible_cpus->len; n++) {
1803         ms->possible_cpus->cpus[n].type = ms->cpu_type;
1804         ms->possible_cpus->cpus[n].arch_id =
1805             virt_cpu_mp_affinity(vms, n);
1806         ms->possible_cpus->cpus[n].props.has_thread_id = true;
1807         ms->possible_cpus->cpus[n].props.thread_id = n;
1808     }
1809     return ms->possible_cpus;
1810 }
1811 
1812 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1813                                         DeviceState *dev, Error **errp)
1814 {
1815     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1816 
1817     if (vms->platform_bus_dev) {
1818         if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1819             platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1820                                      SYS_BUS_DEVICE(dev));
1821         }
1822     }
1823 }
1824 
1825 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1826                                                         DeviceState *dev)
1827 {
1828     if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1829         return HOTPLUG_HANDLER(machine);
1830     }
1831 
1832     return NULL;
1833 }
1834 
1835 /*
1836  * for arm64 kvm_type [7-0] encodes the requested number of bits
1837  * in the IPA address space
1838  */
1839 static int virt_kvm_type(MachineState *ms, const char *type_str)
1840 {
1841     VirtMachineState *vms = VIRT_MACHINE(ms);
1842     int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
1843     int requested_pa_size;
1844 
1845     /* we freeze the memory map to compute the highest gpa */
1846     virt_set_memmap(vms);
1847 
1848     requested_pa_size = 64 - clz64(vms->highest_gpa);
1849 
1850     if (requested_pa_size > max_vm_pa_size) {
1851         error_report("-m and ,maxmem option values "
1852                      "require an IPA range (%d bits) larger than "
1853                      "the one supported by the host (%d bits)",
1854                      requested_pa_size, max_vm_pa_size);
1855        exit(1);
1856     }
1857     /*
1858      * By default we return 0 which corresponds to an implicit legacy
1859      * 40b IPA setting. Otherwise we return the actual requested PA
1860      * logsize
1861      */
1862     return requested_pa_size > 40 ? requested_pa_size : 0;
1863 }
1864 
1865 static void virt_machine_class_init(ObjectClass *oc, void *data)
1866 {
1867     MachineClass *mc = MACHINE_CLASS(oc);
1868     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1869 
1870     mc->init = machvirt_init;
1871     /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1872      * The value may be reduced later when we have more information about the
1873      * configuration of the particular instance.
1874      */
1875     mc->max_cpus = 512;
1876     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1877     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1878     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1879     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
1880     mc->block_default_type = IF_VIRTIO;
1881     mc->no_cdrom = 1;
1882     mc->pci_allow_0_address = true;
1883     /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1884     mc->minimum_page_bits = 12;
1885     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1886     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1887     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1888     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1889     mc->kvm_type = virt_kvm_type;
1890     assert(!mc->get_hotplug_handler);
1891     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1892     hc->plug = virt_machine_device_plug_cb;
1893 }
1894 
1895 static void virt_instance_init(Object *obj)
1896 {
1897     VirtMachineState *vms = VIRT_MACHINE(obj);
1898     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1899 
1900     /* EL3 is disabled by default on virt: this makes us consistent
1901      * between KVM and TCG for this board, and it also allows us to
1902      * boot UEFI blobs which assume no TrustZone support.
1903      */
1904     vms->secure = false;
1905     object_property_add_bool(obj, "secure", virt_get_secure,
1906                              virt_set_secure, NULL);
1907     object_property_set_description(obj, "secure",
1908                                     "Set on/off to enable/disable the ARM "
1909                                     "Security Extensions (TrustZone)",
1910                                     NULL);
1911 
1912     /* EL2 is also disabled by default, for similar reasons */
1913     vms->virt = false;
1914     object_property_add_bool(obj, "virtualization", virt_get_virt,
1915                              virt_set_virt, NULL);
1916     object_property_set_description(obj, "virtualization",
1917                                     "Set on/off to enable/disable emulating a "
1918                                     "guest CPU which implements the ARM "
1919                                     "Virtualization Extensions",
1920                                     NULL);
1921 
1922     /* High memory is enabled by default */
1923     vms->highmem = true;
1924     object_property_add_bool(obj, "highmem", virt_get_highmem,
1925                              virt_set_highmem, NULL);
1926     object_property_set_description(obj, "highmem",
1927                                     "Set on/off to enable/disable using "
1928                                     "physical address space above 32 bits",
1929                                     NULL);
1930     /* Default GIC type is v2 */
1931     vms->gic_version = 2;
1932     object_property_add_str(obj, "gic-version", virt_get_gic_version,
1933                         virt_set_gic_version, NULL);
1934     object_property_set_description(obj, "gic-version",
1935                                     "Set GIC version. "
1936                                     "Valid values are 2, 3 and host", NULL);
1937 
1938     vms->highmem_ecam = !vmc->no_highmem_ecam;
1939 
1940     if (vmc->no_its) {
1941         vms->its = false;
1942     } else {
1943         /* Default allows ITS instantiation */
1944         vms->its = true;
1945         object_property_add_bool(obj, "its", virt_get_its,
1946                                  virt_set_its, NULL);
1947         object_property_set_description(obj, "its",
1948                                         "Set on/off to enable/disable "
1949                                         "ITS instantiation",
1950                                         NULL);
1951     }
1952 
1953     /* Default disallows iommu instantiation */
1954     vms->iommu = VIRT_IOMMU_NONE;
1955     object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
1956     object_property_set_description(obj, "iommu",
1957                                     "Set the IOMMU type. "
1958                                     "Valid values are none and smmuv3",
1959                                     NULL);
1960 
1961     vms->irqmap = a15irqmap;
1962 }
1963 
1964 static const TypeInfo virt_machine_info = {
1965     .name          = TYPE_VIRT_MACHINE,
1966     .parent        = TYPE_MACHINE,
1967     .abstract      = true,
1968     .instance_size = sizeof(VirtMachineState),
1969     .class_size    = sizeof(VirtMachineClass),
1970     .class_init    = virt_machine_class_init,
1971     .instance_init = virt_instance_init,
1972     .interfaces = (InterfaceInfo[]) {
1973          { TYPE_HOTPLUG_HANDLER },
1974          { }
1975     },
1976 };
1977 
1978 static void machvirt_machine_init(void)
1979 {
1980     type_register_static(&virt_machine_info);
1981 }
1982 type_init(machvirt_machine_init);
1983 
1984 static void virt_machine_4_0_options(MachineClass *mc)
1985 {
1986 }
1987 DEFINE_VIRT_MACHINE_AS_LATEST(4, 0)
1988 
1989 static void virt_machine_3_1_options(MachineClass *mc)
1990 {
1991     virt_machine_4_0_options(mc);
1992     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
1993 }
1994 DEFINE_VIRT_MACHINE(3, 1)
1995 
1996 static void virt_machine_3_0_options(MachineClass *mc)
1997 {
1998     virt_machine_3_1_options(mc);
1999     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2000 }
2001 DEFINE_VIRT_MACHINE(3, 0)
2002 
2003 static void virt_machine_2_12_options(MachineClass *mc)
2004 {
2005     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2006 
2007     virt_machine_3_0_options(mc);
2008     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2009     vmc->no_highmem_ecam = true;
2010     mc->max_cpus = 255;
2011 }
2012 DEFINE_VIRT_MACHINE(2, 12)
2013 
2014 static void virt_machine_2_11_options(MachineClass *mc)
2015 {
2016     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2017 
2018     virt_machine_2_12_options(mc);
2019     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2020     vmc->smbios_old_sys_ver = true;
2021 }
2022 DEFINE_VIRT_MACHINE(2, 11)
2023 
2024 static void virt_machine_2_10_options(MachineClass *mc)
2025 {
2026     virt_machine_2_11_options(mc);
2027     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2028     /* before 2.11 we never faulted accesses to bad addresses */
2029     mc->ignore_memory_transaction_failures = true;
2030 }
2031 DEFINE_VIRT_MACHINE(2, 10)
2032 
2033 static void virt_machine_2_9_options(MachineClass *mc)
2034 {
2035     virt_machine_2_10_options(mc);
2036     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2037 }
2038 DEFINE_VIRT_MACHINE(2, 9)
2039 
2040 static void virt_machine_2_8_options(MachineClass *mc)
2041 {
2042     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2043 
2044     virt_machine_2_9_options(mc);
2045     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2046     /* For 2.8 and earlier we falsely claimed in the DT that
2047      * our timers were edge-triggered, not level-triggered.
2048      */
2049     vmc->claim_edge_triggered_timers = true;
2050 }
2051 DEFINE_VIRT_MACHINE(2, 8)
2052 
2053 static void virt_machine_2_7_options(MachineClass *mc)
2054 {
2055     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2056 
2057     virt_machine_2_8_options(mc);
2058     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2059     /* ITS was introduced with 2.8 */
2060     vmc->no_its = true;
2061     /* Stick with 1K pages for migration compatibility */
2062     mc->minimum_page_bits = 0;
2063 }
2064 DEFINE_VIRT_MACHINE(2, 7)
2065 
2066 static void virt_machine_2_6_options(MachineClass *mc)
2067 {
2068     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2069 
2070     virt_machine_2_7_options(mc);
2071     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2072     vmc->disallow_affinity_adjustment = true;
2073     /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2074     vmc->no_pmu = true;
2075 }
2076 DEFINE_VIRT_MACHINE(2, 6)
2077