1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "qapi/qmp/qlist.h" 73 #include "standard-headers/linux/input.h" 74 #include "hw/arm/smmuv3.h" 75 #include "hw/acpi/acpi.h" 76 #include "target/arm/cpu-qom.h" 77 #include "target/arm/internals.h" 78 #include "target/arm/multiprocessing.h" 79 #include "target/arm/gtimer.h" 80 #include "hw/mem/pc-dimm.h" 81 #include "hw/mem/nvdimm.h" 82 #include "hw/acpi/generic_event_device.h" 83 #include "hw/virtio/virtio-md-pci.h" 84 #include "hw/virtio/virtio-iommu.h" 85 #include "hw/char/pl011.h" 86 #include "qemu/guest-random.h" 87 88 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 89 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 90 void *data) \ 91 { \ 92 MachineClass *mc = MACHINE_CLASS(oc); \ 93 virt_machine_##major##_##minor##_options(mc); \ 94 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 95 if (latest) { \ 96 mc->alias = "virt"; \ 97 } \ 98 } \ 99 static const TypeInfo machvirt_##major##_##minor##_info = { \ 100 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 101 .parent = TYPE_VIRT_MACHINE, \ 102 .class_init = virt_##major##_##minor##_class_init, \ 103 }; \ 104 static void machvirt_machine_##major##_##minor##_init(void) \ 105 { \ 106 type_register_static(&machvirt_##major##_##minor##_info); \ 107 } \ 108 type_init(machvirt_machine_##major##_##minor##_init); 109 110 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 111 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 112 #define DEFINE_VIRT_MACHINE(major, minor) \ 113 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 114 115 116 /* Number of external interrupt lines to configure the GIC with */ 117 #define NUM_IRQS 256 118 119 #define PLATFORM_BUS_NUM_IRQS 64 120 121 /* Legacy RAM limit in GB (< version 4.0) */ 122 #define LEGACY_RAMLIMIT_GB 255 123 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 124 125 /* Addresses and sizes of our components. 126 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 127 * 128MB..256MB is used for miscellaneous device I/O. 128 * 256MB..1GB is reserved for possible future PCI support (ie where the 129 * PCI memory window will go if we add a PCI host controller). 130 * 1GB and up is RAM (which may happily spill over into the 131 * high memory region beyond 4GB). 132 * This represents a compromise between how much RAM can be given to 133 * a 32 bit VM and leaving space for expansion and in particular for PCI. 134 * Note that devices should generally be placed at multiples of 0x10000, 135 * to accommodate guests using 64K pages. 136 */ 137 static const MemMapEntry base_memmap[] = { 138 /* Space up to 0x8000000 is reserved for a boot ROM */ 139 [VIRT_FLASH] = { 0, 0x08000000 }, 140 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 141 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 142 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 143 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 144 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 145 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 146 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 147 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 148 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 149 /* This redistributor space allows up to 2*64kB*123 CPUs */ 150 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 151 [VIRT_UART] = { 0x09000000, 0x00001000 }, 152 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 153 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 154 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 155 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 156 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 157 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 158 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 159 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 160 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 161 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 162 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 163 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 164 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 165 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 166 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 167 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 168 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 169 /* Actual RAM size depends on initial RAM and device memory settings */ 170 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 171 }; 172 173 /* 174 * Highmem IO Regions: This memory map is floating, located after the RAM. 175 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 176 * top of the RAM, so that its base get the same alignment as the size, 177 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 178 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 179 * Note the extended_memmap is sized so that it eventually also includes the 180 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 181 * index of base_memmap). 182 * 183 * The memory map for these Highmem IO Regions can be in legacy or compact 184 * layout, depending on 'compact-highmem' property. With legacy layout, the 185 * PA space for one specific region is always reserved, even if the region 186 * has been disabled or doesn't fit into the PA space. However, the PA space 187 * for the region won't be reserved in these circumstances with compact layout. 188 */ 189 static MemMapEntry extended_memmap[] = { 190 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 191 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 192 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 193 /* Second PCIe window */ 194 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 195 }; 196 197 static const int a15irqmap[] = { 198 [VIRT_UART] = 1, 199 [VIRT_RTC] = 2, 200 [VIRT_PCIE] = 3, /* ... to 6 */ 201 [VIRT_GPIO] = 7, 202 [VIRT_SECURE_UART] = 8, 203 [VIRT_ACPI_GED] = 9, 204 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 205 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 206 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 207 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 208 }; 209 210 static void create_randomness(MachineState *ms, const char *node) 211 { 212 struct { 213 uint64_t kaslr; 214 uint8_t rng[32]; 215 } seed; 216 217 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 218 return; 219 } 220 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 221 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 222 } 223 224 static void create_fdt(VirtMachineState *vms) 225 { 226 MachineState *ms = MACHINE(vms); 227 int nb_numa_nodes = ms->numa_state->num_nodes; 228 void *fdt = create_device_tree(&vms->fdt_size); 229 230 if (!fdt) { 231 error_report("create_device_tree() failed"); 232 exit(1); 233 } 234 235 ms->fdt = fdt; 236 237 /* Header */ 238 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 239 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 240 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 241 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 242 243 /* /chosen must exist for load_dtb to fill in necessary properties later */ 244 qemu_fdt_add_subnode(fdt, "/chosen"); 245 if (vms->dtb_randomness) { 246 create_randomness(ms, "/chosen"); 247 } 248 249 if (vms->secure) { 250 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 251 if (vms->dtb_randomness) { 252 create_randomness(ms, "/secure-chosen"); 253 } 254 } 255 256 /* Clock node, for the benefit of the UART. The kernel device tree 257 * binding documentation claims the PL011 node clock properties are 258 * optional but in practice if you omit them the kernel refuses to 259 * probe for the device. 260 */ 261 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 262 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 263 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 266 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 267 "clk24mhz"); 268 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 269 270 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 271 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 272 uint32_t *matrix = g_malloc0(size); 273 int idx, i, j; 274 275 for (i = 0; i < nb_numa_nodes; i++) { 276 for (j = 0; j < nb_numa_nodes; j++) { 277 idx = (i * nb_numa_nodes + j) * 3; 278 matrix[idx + 0] = cpu_to_be32(i); 279 matrix[idx + 1] = cpu_to_be32(j); 280 matrix[idx + 2] = 281 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 282 } 283 } 284 285 qemu_fdt_add_subnode(fdt, "/distance-map"); 286 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 287 "numa-distance-map-v1"); 288 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 289 matrix, size); 290 g_free(matrix); 291 } 292 } 293 294 static void fdt_add_timer_nodes(const VirtMachineState *vms) 295 { 296 /* On real hardware these interrupts are level-triggered. 297 * On KVM they were edge-triggered before host kernel version 4.4, 298 * and level-triggered afterwards. 299 * On emulated QEMU they are level-triggered. 300 * 301 * Getting the DTB info about them wrong is awkward for some 302 * guest kernels: 303 * pre-4.8 ignore the DT and leave the interrupt configured 304 * with whatever the GIC reset value (or the bootloader) left it at 305 * 4.8 before rc6 honour the incorrect data by programming it back 306 * into the GIC, causing problems 307 * 4.8rc6 and later ignore the DT and always write "level triggered" 308 * into the GIC 309 * 310 * For backwards-compatibility, virt-2.8 and earlier will continue 311 * to say these are edge-triggered, but later machines will report 312 * the correct information. 313 */ 314 ARMCPU *armcpu; 315 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 316 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 317 MachineState *ms = MACHINE(vms); 318 319 if (vmc->claim_edge_triggered_timers) { 320 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 321 } 322 323 if (vms->gic_version == VIRT_GIC_VERSION_2) { 324 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 325 GIC_FDT_IRQ_PPI_CPU_WIDTH, 326 (1 << MACHINE(vms)->smp.cpus) - 1); 327 } 328 329 qemu_fdt_add_subnode(ms->fdt, "/timer"); 330 331 armcpu = ARM_CPU(qemu_get_cpu(0)); 332 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 333 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 334 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 335 compat, sizeof(compat)); 336 } else { 337 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 338 "arm,armv7-timer"); 339 } 340 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 341 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 342 GIC_FDT_IRQ_TYPE_PPI, 343 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 344 GIC_FDT_IRQ_TYPE_PPI, 345 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 346 GIC_FDT_IRQ_TYPE_PPI, 347 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 348 GIC_FDT_IRQ_TYPE_PPI, 349 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 350 } 351 352 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 353 { 354 int cpu; 355 int addr_cells = 1; 356 const MachineState *ms = MACHINE(vms); 357 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 358 int smp_cpus = ms->smp.cpus; 359 360 /* 361 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 362 * On ARM v8 64-bit systems value should be set to 2, 363 * that corresponds to the MPIDR_EL1 register size. 364 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 365 * in the system, #address-cells can be set to 1, since 366 * MPIDR_EL1[63:32] bits are not used for CPUs 367 * identification. 368 * 369 * Here we actually don't know whether our system is 32- or 64-bit one. 370 * The simplest way to go is to examine affinity IDs of all our CPUs. If 371 * at least one of them has Aff3 populated, we set #address-cells to 2. 372 */ 373 for (cpu = 0; cpu < smp_cpus; cpu++) { 374 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 375 376 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 377 addr_cells = 2; 378 break; 379 } 380 } 381 382 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 383 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 384 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 385 386 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 387 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 388 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 389 CPUState *cs = CPU(armcpu); 390 391 qemu_fdt_add_subnode(ms->fdt, nodename); 392 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 393 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 394 armcpu->dtb_compatible); 395 396 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 397 qemu_fdt_setprop_string(ms->fdt, nodename, 398 "enable-method", "psci"); 399 } 400 401 if (addr_cells == 2) { 402 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 403 arm_cpu_mp_affinity(armcpu)); 404 } else { 405 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 406 arm_cpu_mp_affinity(armcpu)); 407 } 408 409 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 410 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 411 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 412 } 413 414 if (!vmc->no_cpu_topology) { 415 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 416 qemu_fdt_alloc_phandle(ms->fdt)); 417 } 418 419 g_free(nodename); 420 } 421 422 if (!vmc->no_cpu_topology) { 423 /* 424 * Add vCPU topology description through fdt node cpu-map. 425 * 426 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 427 * In a SMP system, the hierarchy of CPUs can be defined through 428 * four entities that are used to describe the layout of CPUs in 429 * the system: socket/cluster/core/thread. 430 * 431 * A socket node represents the boundary of system physical package 432 * and its child nodes must be one or more cluster nodes. A system 433 * can contain several layers of clustering within a single physical 434 * package and cluster nodes can be contained in parent cluster nodes. 435 * 436 * Note: currently we only support one layer of clustering within 437 * each physical package. 438 */ 439 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 440 441 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 442 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 443 char *map_path; 444 445 if (ms->smp.threads > 1) { 446 map_path = g_strdup_printf( 447 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 448 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 449 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 450 (cpu / ms->smp.threads) % ms->smp.cores, 451 cpu % ms->smp.threads); 452 } else { 453 map_path = g_strdup_printf( 454 "/cpus/cpu-map/socket%d/cluster%d/core%d", 455 cpu / (ms->smp.clusters * ms->smp.cores), 456 (cpu / ms->smp.cores) % ms->smp.clusters, 457 cpu % ms->smp.cores); 458 } 459 qemu_fdt_add_path(ms->fdt, map_path); 460 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 461 462 g_free(map_path); 463 g_free(cpu_path); 464 } 465 } 466 } 467 468 static void fdt_add_its_gic_node(VirtMachineState *vms) 469 { 470 char *nodename; 471 MachineState *ms = MACHINE(vms); 472 473 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 474 nodename = g_strdup_printf("/intc/its@%" PRIx64, 475 vms->memmap[VIRT_GIC_ITS].base); 476 qemu_fdt_add_subnode(ms->fdt, nodename); 477 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 478 "arm,gic-v3-its"); 479 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 480 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 481 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 482 2, vms->memmap[VIRT_GIC_ITS].base, 483 2, vms->memmap[VIRT_GIC_ITS].size); 484 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 485 g_free(nodename); 486 } 487 488 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 489 { 490 MachineState *ms = MACHINE(vms); 491 char *nodename; 492 493 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 494 vms->memmap[VIRT_GIC_V2M].base); 495 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 496 qemu_fdt_add_subnode(ms->fdt, nodename); 497 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 498 "arm,gic-v2m-frame"); 499 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 500 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 501 2, vms->memmap[VIRT_GIC_V2M].base, 502 2, vms->memmap[VIRT_GIC_V2M].size); 503 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 504 g_free(nodename); 505 } 506 507 static void fdt_add_gic_node(VirtMachineState *vms) 508 { 509 MachineState *ms = MACHINE(vms); 510 char *nodename; 511 512 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 513 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 514 515 nodename = g_strdup_printf("/intc@%" PRIx64, 516 vms->memmap[VIRT_GIC_DIST].base); 517 qemu_fdt_add_subnode(ms->fdt, nodename); 518 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 519 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 520 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 521 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 522 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 523 if (vms->gic_version != VIRT_GIC_VERSION_2) { 524 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 525 526 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 527 "arm,gic-v3"); 528 529 qemu_fdt_setprop_cell(ms->fdt, nodename, 530 "#redistributor-regions", nb_redist_regions); 531 532 if (nb_redist_regions == 1) { 533 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 534 2, vms->memmap[VIRT_GIC_DIST].base, 535 2, vms->memmap[VIRT_GIC_DIST].size, 536 2, vms->memmap[VIRT_GIC_REDIST].base, 537 2, vms->memmap[VIRT_GIC_REDIST].size); 538 } else { 539 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 540 2, vms->memmap[VIRT_GIC_DIST].base, 541 2, vms->memmap[VIRT_GIC_DIST].size, 542 2, vms->memmap[VIRT_GIC_REDIST].base, 543 2, vms->memmap[VIRT_GIC_REDIST].size, 544 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 545 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 546 } 547 548 if (vms->virt) { 549 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 550 GIC_FDT_IRQ_TYPE_PPI, 551 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 552 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 553 } 554 } else { 555 /* 'cortex-a15-gic' means 'GIC v2' */ 556 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 557 "arm,cortex-a15-gic"); 558 if (!vms->virt) { 559 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 560 2, vms->memmap[VIRT_GIC_DIST].base, 561 2, vms->memmap[VIRT_GIC_DIST].size, 562 2, vms->memmap[VIRT_GIC_CPU].base, 563 2, vms->memmap[VIRT_GIC_CPU].size); 564 } else { 565 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 566 2, vms->memmap[VIRT_GIC_DIST].base, 567 2, vms->memmap[VIRT_GIC_DIST].size, 568 2, vms->memmap[VIRT_GIC_CPU].base, 569 2, vms->memmap[VIRT_GIC_CPU].size, 570 2, vms->memmap[VIRT_GIC_HYP].base, 571 2, vms->memmap[VIRT_GIC_HYP].size, 572 2, vms->memmap[VIRT_GIC_VCPU].base, 573 2, vms->memmap[VIRT_GIC_VCPU].size); 574 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 575 GIC_FDT_IRQ_TYPE_PPI, 576 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 577 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 578 } 579 } 580 581 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 582 g_free(nodename); 583 } 584 585 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 586 { 587 ARMCPU *armcpu = ARM_CPU(first_cpu); 588 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 589 MachineState *ms = MACHINE(vms); 590 591 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 592 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 593 return; 594 } 595 596 if (vms->gic_version == VIRT_GIC_VERSION_2) { 597 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 598 GIC_FDT_IRQ_PPI_CPU_WIDTH, 599 (1 << MACHINE(vms)->smp.cpus) - 1); 600 } 601 602 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 603 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 604 const char compat[] = "arm,armv8-pmuv3"; 605 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 606 compat, sizeof(compat)); 607 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 608 GIC_FDT_IRQ_TYPE_PPI, 609 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 610 } 611 } 612 613 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 614 { 615 DeviceState *dev; 616 MachineState *ms = MACHINE(vms); 617 int irq = vms->irqmap[VIRT_ACPI_GED]; 618 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 619 620 if (ms->ram_slots) { 621 event |= ACPI_GED_MEM_HOTPLUG_EVT; 622 } 623 624 if (ms->nvdimms_state->is_enabled) { 625 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 626 } 627 628 dev = qdev_new(TYPE_ACPI_GED); 629 qdev_prop_set_uint32(dev, "ged-event", event); 630 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 631 632 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 633 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 634 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 635 636 return dev; 637 } 638 639 static void create_its(VirtMachineState *vms) 640 { 641 const char *itsclass = its_class_name(); 642 DeviceState *dev; 643 644 if (!strcmp(itsclass, "arm-gicv3-its")) { 645 if (!vms->tcg_its) { 646 itsclass = NULL; 647 } 648 } 649 650 if (!itsclass) { 651 /* Do nothing if not supported */ 652 return; 653 } 654 655 dev = qdev_new(itsclass); 656 657 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 658 &error_abort); 659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 660 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 661 662 fdt_add_its_gic_node(vms); 663 vms->msi_controller = VIRT_MSI_CTRL_ITS; 664 } 665 666 static void create_v2m(VirtMachineState *vms) 667 { 668 int i; 669 int irq = vms->irqmap[VIRT_GIC_V2M]; 670 DeviceState *dev; 671 672 dev = qdev_new("arm-gicv2m"); 673 qdev_prop_set_uint32(dev, "base-spi", irq); 674 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 675 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 676 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 677 678 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 679 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 680 qdev_get_gpio_in(vms->gic, irq + i)); 681 } 682 683 fdt_add_v2m_gic_node(vms); 684 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 685 } 686 687 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 688 { 689 MachineState *ms = MACHINE(vms); 690 /* We create a standalone GIC */ 691 SysBusDevice *gicbusdev; 692 const char *gictype; 693 int i; 694 unsigned int smp_cpus = ms->smp.cpus; 695 uint32_t nb_redist_regions = 0; 696 int revision; 697 698 if (vms->gic_version == VIRT_GIC_VERSION_2) { 699 gictype = gic_class_name(); 700 } else { 701 gictype = gicv3_class_name(); 702 } 703 704 switch (vms->gic_version) { 705 case VIRT_GIC_VERSION_2: 706 revision = 2; 707 break; 708 case VIRT_GIC_VERSION_3: 709 revision = 3; 710 break; 711 case VIRT_GIC_VERSION_4: 712 revision = 4; 713 break; 714 default: 715 g_assert_not_reached(); 716 } 717 vms->gic = qdev_new(gictype); 718 qdev_prop_set_uint32(vms->gic, "revision", revision); 719 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 720 /* Note that the num-irq property counts both internal and external 721 * interrupts; there are always 32 of the former (mandated by GIC spec). 722 */ 723 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 724 if (!kvm_irqchip_in_kernel()) { 725 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 726 } 727 728 if (vms->gic_version != VIRT_GIC_VERSION_2) { 729 QList *redist_region_count; 730 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 731 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 732 733 nb_redist_regions = virt_gicv3_redist_region_count(vms); 734 735 redist_region_count = qlist_new(); 736 qlist_append_int(redist_region_count, redist0_count); 737 if (nb_redist_regions == 2) { 738 uint32_t redist1_capacity = 739 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 740 741 qlist_append_int(redist_region_count, 742 MIN(smp_cpus - redist0_count, redist1_capacity)); 743 } 744 qdev_prop_set_array(vms->gic, "redist-region-count", 745 redist_region_count); 746 747 if (!kvm_irqchip_in_kernel()) { 748 if (vms->tcg_its) { 749 object_property_set_link(OBJECT(vms->gic), "sysmem", 750 OBJECT(mem), &error_fatal); 751 qdev_prop_set_bit(vms->gic, "has-lpi", true); 752 } 753 } 754 } else { 755 if (!kvm_irqchip_in_kernel()) { 756 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 757 vms->virt); 758 } 759 } 760 gicbusdev = SYS_BUS_DEVICE(vms->gic); 761 sysbus_realize_and_unref(gicbusdev, &error_fatal); 762 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 763 if (vms->gic_version != VIRT_GIC_VERSION_2) { 764 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 765 if (nb_redist_regions == 2) { 766 sysbus_mmio_map(gicbusdev, 2, 767 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 768 } 769 } else { 770 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 771 if (vms->virt) { 772 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 773 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 774 } 775 } 776 777 /* Wire the outputs from each CPU's generic timer and the GICv3 778 * maintenance interrupt signal to the appropriate GIC PPI inputs, 779 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 780 */ 781 for (i = 0; i < smp_cpus; i++) { 782 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 783 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 784 /* Mapping from the output timer irq lines from the CPU to the 785 * GIC PPI inputs we use for the virt board. 786 */ 787 const int timer_irq[] = { 788 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 789 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 790 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 791 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 792 }; 793 794 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 795 qdev_connect_gpio_out(cpudev, irq, 796 qdev_get_gpio_in(vms->gic, 797 intidbase + timer_irq[irq])); 798 } 799 800 if (vms->gic_version != VIRT_GIC_VERSION_2) { 801 qemu_irq irq = qdev_get_gpio_in(vms->gic, 802 intidbase + ARCH_GIC_MAINT_IRQ); 803 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 804 0, irq); 805 } else if (vms->virt) { 806 qemu_irq irq = qdev_get_gpio_in(vms->gic, 807 intidbase + ARCH_GIC_MAINT_IRQ); 808 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 809 } 810 811 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 812 qdev_get_gpio_in(vms->gic, intidbase 813 + VIRTUAL_PMU_IRQ)); 814 815 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 816 sysbus_connect_irq(gicbusdev, i + smp_cpus, 817 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 818 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 819 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 820 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 821 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 822 } 823 824 fdt_add_gic_node(vms); 825 826 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 827 create_its(vms); 828 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 829 create_v2m(vms); 830 } 831 } 832 833 static void create_uart(const VirtMachineState *vms, int uart, 834 MemoryRegion *mem, Chardev *chr) 835 { 836 char *nodename; 837 hwaddr base = vms->memmap[uart].base; 838 hwaddr size = vms->memmap[uart].size; 839 int irq = vms->irqmap[uart]; 840 const char compat[] = "arm,pl011\0arm,primecell"; 841 const char clocknames[] = "uartclk\0apb_pclk"; 842 DeviceState *dev = qdev_new(TYPE_PL011); 843 SysBusDevice *s = SYS_BUS_DEVICE(dev); 844 MachineState *ms = MACHINE(vms); 845 846 qdev_prop_set_chr(dev, "chardev", chr); 847 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 848 memory_region_add_subregion(mem, base, 849 sysbus_mmio_get_region(s, 0)); 850 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 851 852 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 853 qemu_fdt_add_subnode(ms->fdt, nodename); 854 /* Note that we can't use setprop_string because of the embedded NUL */ 855 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 856 compat, sizeof(compat)); 857 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 858 2, base, 2, size); 859 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 860 GIC_FDT_IRQ_TYPE_SPI, irq, 861 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 862 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 863 vms->clock_phandle, vms->clock_phandle); 864 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 865 clocknames, sizeof(clocknames)); 866 867 if (uart == VIRT_UART) { 868 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 869 } else { 870 /* Mark as not usable by the normal world */ 871 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 872 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 873 874 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 875 nodename); 876 } 877 878 g_free(nodename); 879 } 880 881 static void create_rtc(const VirtMachineState *vms) 882 { 883 char *nodename; 884 hwaddr base = vms->memmap[VIRT_RTC].base; 885 hwaddr size = vms->memmap[VIRT_RTC].size; 886 int irq = vms->irqmap[VIRT_RTC]; 887 const char compat[] = "arm,pl031\0arm,primecell"; 888 MachineState *ms = MACHINE(vms); 889 890 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 891 892 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 893 qemu_fdt_add_subnode(ms->fdt, nodename); 894 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 895 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 896 2, base, 2, size); 897 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 898 GIC_FDT_IRQ_TYPE_SPI, irq, 899 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 900 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 901 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 902 g_free(nodename); 903 } 904 905 static DeviceState *gpio_key_dev; 906 static void virt_powerdown_req(Notifier *n, void *opaque) 907 { 908 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 909 910 if (s->acpi_dev) { 911 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 912 } else { 913 /* use gpio Pin 3 for power button event */ 914 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 915 } 916 } 917 918 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 919 uint32_t phandle) 920 { 921 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 922 qdev_get_gpio_in(pl061_dev, 3)); 923 924 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 925 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 926 927 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 928 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 929 "label", "GPIO Key Poweroff"); 930 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 931 KEY_POWER); 932 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 933 "gpios", phandle, 3, 0); 934 } 935 936 #define SECURE_GPIO_POWEROFF 0 937 #define SECURE_GPIO_RESET 1 938 939 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 940 uint32_t phandle) 941 { 942 DeviceState *gpio_pwr_dev; 943 944 /* gpio-pwr */ 945 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 946 947 /* connect secure pl061 to gpio-pwr */ 948 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 949 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 950 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 951 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 952 953 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 954 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 955 "gpio-poweroff"); 956 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 957 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 958 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 959 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 960 "okay"); 961 962 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 963 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 964 "gpio-restart"); 965 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 966 "gpios", phandle, SECURE_GPIO_RESET, 0); 967 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 968 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 969 "okay"); 970 } 971 972 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 973 MemoryRegion *mem) 974 { 975 char *nodename; 976 DeviceState *pl061_dev; 977 hwaddr base = vms->memmap[gpio].base; 978 hwaddr size = vms->memmap[gpio].size; 979 int irq = vms->irqmap[gpio]; 980 const char compat[] = "arm,pl061\0arm,primecell"; 981 SysBusDevice *s; 982 MachineState *ms = MACHINE(vms); 983 984 pl061_dev = qdev_new("pl061"); 985 /* Pull lines down to 0 if not driven by the PL061 */ 986 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 987 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 988 s = SYS_BUS_DEVICE(pl061_dev); 989 sysbus_realize_and_unref(s, &error_fatal); 990 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 991 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 992 993 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 994 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 995 qemu_fdt_add_subnode(ms->fdt, nodename); 996 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 997 2, base, 2, size); 998 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 999 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1000 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1001 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1002 GIC_FDT_IRQ_TYPE_SPI, irq, 1003 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1004 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1005 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1007 1008 if (gpio != VIRT_GPIO) { 1009 /* Mark as not usable by the normal world */ 1010 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1011 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1012 } 1013 g_free(nodename); 1014 1015 /* Child gpio devices */ 1016 if (gpio == VIRT_GPIO) { 1017 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1018 } else { 1019 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1020 } 1021 } 1022 1023 static void create_virtio_devices(const VirtMachineState *vms) 1024 { 1025 int i; 1026 hwaddr size = vms->memmap[VIRT_MMIO].size; 1027 MachineState *ms = MACHINE(vms); 1028 1029 /* We create the transports in forwards order. Since qbus_realize() 1030 * prepends (not appends) new child buses, the incrementing loop below will 1031 * create a list of virtio-mmio buses with decreasing base addresses. 1032 * 1033 * When a -device option is processed from the command line, 1034 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1035 * order. The upshot is that -device options in increasing command line 1036 * order are mapped to virtio-mmio buses with decreasing base addresses. 1037 * 1038 * When this code was originally written, that arrangement ensured that the 1039 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1040 * the first -device on the command line. (The end-to-end order is a 1041 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1042 * guest kernel's name-to-address assignment strategy.) 1043 * 1044 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1045 * the message, if not necessarily the code, of commit 70161ff336. 1046 * Therefore the loop now establishes the inverse of the original intent. 1047 * 1048 * Unfortunately, we can't counteract the kernel change by reversing the 1049 * loop; it would break existing command lines. 1050 * 1051 * In any case, the kernel makes no guarantee about the stability of 1052 * enumeration order of virtio devices (as demonstrated by it changing 1053 * between kernel versions). For reliable and stable identification 1054 * of disks users must use UUIDs or similar mechanisms. 1055 */ 1056 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1057 int irq = vms->irqmap[VIRT_MMIO] + i; 1058 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1059 1060 sysbus_create_simple("virtio-mmio", base, 1061 qdev_get_gpio_in(vms->gic, irq)); 1062 } 1063 1064 /* We add dtb nodes in reverse order so that they appear in the finished 1065 * device tree lowest address first. 1066 * 1067 * Note that this mapping is independent of the loop above. The previous 1068 * loop influences virtio device to virtio transport assignment, whereas 1069 * this loop controls how virtio transports are laid out in the dtb. 1070 */ 1071 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1072 char *nodename; 1073 int irq = vms->irqmap[VIRT_MMIO] + i; 1074 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1075 1076 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1077 qemu_fdt_add_subnode(ms->fdt, nodename); 1078 qemu_fdt_setprop_string(ms->fdt, nodename, 1079 "compatible", "virtio,mmio"); 1080 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1081 2, base, 2, size); 1082 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1083 GIC_FDT_IRQ_TYPE_SPI, irq, 1084 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1085 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1086 g_free(nodename); 1087 } 1088 } 1089 1090 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1091 1092 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1093 const char *name, 1094 const char *alias_prop_name) 1095 { 1096 /* 1097 * Create a single flash device. We use the same parameters as 1098 * the flash devices on the Versatile Express board. 1099 */ 1100 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1101 1102 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1103 qdev_prop_set_uint8(dev, "width", 4); 1104 qdev_prop_set_uint8(dev, "device-width", 2); 1105 qdev_prop_set_bit(dev, "big-endian", false); 1106 qdev_prop_set_uint16(dev, "id0", 0x89); 1107 qdev_prop_set_uint16(dev, "id1", 0x18); 1108 qdev_prop_set_uint16(dev, "id2", 0x00); 1109 qdev_prop_set_uint16(dev, "id3", 0x00); 1110 qdev_prop_set_string(dev, "name", name); 1111 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1112 object_property_add_alias(OBJECT(vms), alias_prop_name, 1113 OBJECT(dev), "drive"); 1114 return PFLASH_CFI01(dev); 1115 } 1116 1117 static void virt_flash_create(VirtMachineState *vms) 1118 { 1119 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1120 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1121 } 1122 1123 static void virt_flash_map1(PFlashCFI01 *flash, 1124 hwaddr base, hwaddr size, 1125 MemoryRegion *sysmem) 1126 { 1127 DeviceState *dev = DEVICE(flash); 1128 1129 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1130 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1131 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1132 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1133 1134 memory_region_add_subregion(sysmem, base, 1135 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1136 0)); 1137 } 1138 1139 static void virt_flash_map(VirtMachineState *vms, 1140 MemoryRegion *sysmem, 1141 MemoryRegion *secure_sysmem) 1142 { 1143 /* 1144 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1145 * sysmem is the system memory space. secure_sysmem is the secure view 1146 * of the system, and the first flash device should be made visible only 1147 * there. The second flash device is visible to both secure and nonsecure. 1148 * If sysmem == secure_sysmem this means there is no separate Secure 1149 * address space and both flash devices are generally visible. 1150 */ 1151 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1152 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1153 1154 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1155 secure_sysmem); 1156 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1157 sysmem); 1158 } 1159 1160 static void virt_flash_fdt(VirtMachineState *vms, 1161 MemoryRegion *sysmem, 1162 MemoryRegion *secure_sysmem) 1163 { 1164 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1165 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1166 MachineState *ms = MACHINE(vms); 1167 char *nodename; 1168 1169 if (sysmem == secure_sysmem) { 1170 /* Report both flash devices as a single node in the DT */ 1171 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1172 qemu_fdt_add_subnode(ms->fdt, nodename); 1173 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1174 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1175 2, flashbase, 2, flashsize, 1176 2, flashbase + flashsize, 2, flashsize); 1177 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1178 g_free(nodename); 1179 } else { 1180 /* 1181 * Report the devices as separate nodes so we can mark one as 1182 * only visible to the secure world. 1183 */ 1184 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1185 qemu_fdt_add_subnode(ms->fdt, nodename); 1186 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1187 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1188 2, flashbase, 2, flashsize); 1189 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1190 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1191 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1192 g_free(nodename); 1193 1194 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1195 qemu_fdt_add_subnode(ms->fdt, nodename); 1196 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1197 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1198 2, flashbase + flashsize, 2, flashsize); 1199 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1200 g_free(nodename); 1201 } 1202 } 1203 1204 static bool virt_firmware_init(VirtMachineState *vms, 1205 MemoryRegion *sysmem, 1206 MemoryRegion *secure_sysmem) 1207 { 1208 int i; 1209 const char *bios_name; 1210 BlockBackend *pflash_blk0; 1211 1212 /* Map legacy -drive if=pflash to machine properties */ 1213 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1214 pflash_cfi01_legacy_drive(vms->flash[i], 1215 drive_get(IF_PFLASH, 0, i)); 1216 } 1217 1218 virt_flash_map(vms, sysmem, secure_sysmem); 1219 1220 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1221 1222 bios_name = MACHINE(vms)->firmware; 1223 if (bios_name) { 1224 char *fname; 1225 MemoryRegion *mr; 1226 int image_size; 1227 1228 if (pflash_blk0) { 1229 error_report("The contents of the first flash device may be " 1230 "specified with -bios or with -drive if=pflash... " 1231 "but you cannot use both options at once"); 1232 exit(1); 1233 } 1234 1235 /* Fall back to -bios */ 1236 1237 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1238 if (!fname) { 1239 error_report("Could not find ROM image '%s'", bios_name); 1240 exit(1); 1241 } 1242 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1243 image_size = load_image_mr(fname, mr); 1244 g_free(fname); 1245 if (image_size < 0) { 1246 error_report("Could not load ROM image '%s'", bios_name); 1247 exit(1); 1248 } 1249 } 1250 1251 return pflash_blk0 || bios_name; 1252 } 1253 1254 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1255 { 1256 MachineState *ms = MACHINE(vms); 1257 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1258 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1259 FWCfgState *fw_cfg; 1260 char *nodename; 1261 1262 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1263 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1264 1265 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1266 qemu_fdt_add_subnode(ms->fdt, nodename); 1267 qemu_fdt_setprop_string(ms->fdt, nodename, 1268 "compatible", "qemu,fw-cfg-mmio"); 1269 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1270 2, base, 2, size); 1271 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1272 g_free(nodename); 1273 return fw_cfg; 1274 } 1275 1276 static void create_pcie_irq_map(const MachineState *ms, 1277 uint32_t gic_phandle, 1278 int first_irq, const char *nodename) 1279 { 1280 int devfn, pin; 1281 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1282 uint32_t *irq_map = full_irq_map; 1283 1284 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1285 for (pin = 0; pin < 4; pin++) { 1286 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1287 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1288 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1289 int i; 1290 1291 uint32_t map[] = { 1292 devfn << 8, 0, 0, /* devfn */ 1293 pin + 1, /* PCI pin */ 1294 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1295 1296 /* Convert map to big endian */ 1297 for (i = 0; i < 10; i++) { 1298 irq_map[i] = cpu_to_be32(map[i]); 1299 } 1300 irq_map += 10; 1301 } 1302 } 1303 1304 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1305 full_irq_map, sizeof(full_irq_map)); 1306 1307 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1308 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1309 0, 0, 1310 0x7 /* PCI irq */); 1311 } 1312 1313 static void create_smmu(const VirtMachineState *vms, 1314 PCIBus *bus) 1315 { 1316 char *node; 1317 const char compat[] = "arm,smmu-v3"; 1318 int irq = vms->irqmap[VIRT_SMMU]; 1319 int i; 1320 hwaddr base = vms->memmap[VIRT_SMMU].base; 1321 hwaddr size = vms->memmap[VIRT_SMMU].size; 1322 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1323 DeviceState *dev; 1324 MachineState *ms = MACHINE(vms); 1325 1326 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1327 return; 1328 } 1329 1330 dev = qdev_new(TYPE_ARM_SMMUV3); 1331 1332 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1333 &error_abort); 1334 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1335 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1336 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1337 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1338 qdev_get_gpio_in(vms->gic, irq + i)); 1339 } 1340 1341 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1342 qemu_fdt_add_subnode(ms->fdt, node); 1343 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1344 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1345 1346 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1347 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1348 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1349 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1350 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1351 1352 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1353 sizeof(irq_names)); 1354 1355 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1356 1357 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1358 1359 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1360 g_free(node); 1361 } 1362 1363 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1364 { 1365 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1366 uint16_t bdf = vms->virtio_iommu_bdf; 1367 MachineState *ms = MACHINE(vms); 1368 char *node; 1369 1370 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1371 1372 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1373 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1374 qemu_fdt_add_subnode(ms->fdt, node); 1375 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1376 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1377 1, bdf << 8, 1, 0, 1, 0, 1378 1, 0, 1, 0); 1379 1380 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1381 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1382 g_free(node); 1383 1384 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1385 0x0, vms->iommu_phandle, 0x0, bdf, 1386 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1387 } 1388 1389 static void create_pcie(VirtMachineState *vms) 1390 { 1391 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1392 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1393 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1394 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1395 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1396 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1397 hwaddr base_ecam, size_ecam; 1398 hwaddr base = base_mmio; 1399 int nr_pcie_buses; 1400 int irq = vms->irqmap[VIRT_PCIE]; 1401 MemoryRegion *mmio_alias; 1402 MemoryRegion *mmio_reg; 1403 MemoryRegion *ecam_alias; 1404 MemoryRegion *ecam_reg; 1405 DeviceState *dev; 1406 char *nodename; 1407 int i, ecam_id; 1408 PCIHostState *pci; 1409 MachineState *ms = MACHINE(vms); 1410 MachineClass *mc = MACHINE_GET_CLASS(ms); 1411 1412 dev = qdev_new(TYPE_GPEX_HOST); 1413 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1414 1415 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1416 base_ecam = vms->memmap[ecam_id].base; 1417 size_ecam = vms->memmap[ecam_id].size; 1418 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1419 /* Map only the first size_ecam bytes of ECAM space */ 1420 ecam_alias = g_new0(MemoryRegion, 1); 1421 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1422 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1423 ecam_reg, 0, size_ecam); 1424 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1425 1426 /* Map the MMIO window into system address space so as to expose 1427 * the section of PCI MMIO space which starts at the same base address 1428 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1429 * the window). 1430 */ 1431 mmio_alias = g_new0(MemoryRegion, 1); 1432 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1433 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1434 mmio_reg, base_mmio, size_mmio); 1435 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1436 1437 if (vms->highmem_mmio) { 1438 /* Map high MMIO space */ 1439 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1440 1441 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1442 mmio_reg, base_mmio_high, size_mmio_high); 1443 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1444 high_mmio_alias); 1445 } 1446 1447 /* Map IO port space */ 1448 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1449 1450 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1451 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1452 qdev_get_gpio_in(vms->gic, irq + i)); 1453 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1454 } 1455 1456 pci = PCI_HOST_BRIDGE(dev); 1457 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1458 vms->bus = pci->bus; 1459 if (vms->bus) { 1460 pci_init_nic_devices(pci->bus, mc->default_nic); 1461 } 1462 1463 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1464 qemu_fdt_add_subnode(ms->fdt, nodename); 1465 qemu_fdt_setprop_string(ms->fdt, nodename, 1466 "compatible", "pci-host-ecam-generic"); 1467 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1468 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1469 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1470 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1471 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1472 nr_pcie_buses - 1); 1473 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1474 1475 if (vms->msi_phandle) { 1476 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1477 0, vms->msi_phandle, 0, 0x10000); 1478 } 1479 1480 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1481 2, base_ecam, 2, size_ecam); 1482 1483 if (vms->highmem_mmio) { 1484 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1485 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1486 2, base_pio, 2, size_pio, 1487 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1488 2, base_mmio, 2, size_mmio, 1489 1, FDT_PCI_RANGE_MMIO_64BIT, 1490 2, base_mmio_high, 1491 2, base_mmio_high, 2, size_mmio_high); 1492 } else { 1493 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1494 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1495 2, base_pio, 2, size_pio, 1496 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1497 2, base_mmio, 2, size_mmio); 1498 } 1499 1500 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1501 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1502 1503 if (vms->iommu) { 1504 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1505 1506 switch (vms->iommu) { 1507 case VIRT_IOMMU_SMMUV3: 1508 create_smmu(vms, vms->bus); 1509 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1510 0x0, vms->iommu_phandle, 0x0, 0x10000); 1511 break; 1512 default: 1513 g_assert_not_reached(); 1514 } 1515 } 1516 } 1517 1518 static void create_platform_bus(VirtMachineState *vms) 1519 { 1520 DeviceState *dev; 1521 SysBusDevice *s; 1522 int i; 1523 MemoryRegion *sysmem = get_system_memory(); 1524 1525 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1526 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1527 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1528 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1529 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1530 vms->platform_bus_dev = dev; 1531 1532 s = SYS_BUS_DEVICE(dev); 1533 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1534 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1535 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1536 } 1537 1538 memory_region_add_subregion(sysmem, 1539 vms->memmap[VIRT_PLATFORM_BUS].base, 1540 sysbus_mmio_get_region(s, 0)); 1541 } 1542 1543 static void create_tag_ram(MemoryRegion *tag_sysmem, 1544 hwaddr base, hwaddr size, 1545 const char *name) 1546 { 1547 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1548 1549 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1550 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1551 } 1552 1553 static void create_secure_ram(VirtMachineState *vms, 1554 MemoryRegion *secure_sysmem, 1555 MemoryRegion *secure_tag_sysmem) 1556 { 1557 MemoryRegion *secram = g_new(MemoryRegion, 1); 1558 char *nodename; 1559 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1560 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1561 MachineState *ms = MACHINE(vms); 1562 1563 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1564 &error_fatal); 1565 memory_region_add_subregion(secure_sysmem, base, secram); 1566 1567 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1568 qemu_fdt_add_subnode(ms->fdt, nodename); 1569 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1570 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1571 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1572 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1573 1574 if (secure_tag_sysmem) { 1575 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1576 } 1577 1578 g_free(nodename); 1579 } 1580 1581 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1582 { 1583 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1584 bootinfo); 1585 MachineState *ms = MACHINE(board); 1586 1587 1588 *fdt_size = board->fdt_size; 1589 return ms->fdt; 1590 } 1591 1592 static void virt_build_smbios(VirtMachineState *vms) 1593 { 1594 MachineClass *mc = MACHINE_GET_CLASS(vms); 1595 MachineState *ms = MACHINE(vms); 1596 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1597 uint8_t *smbios_tables, *smbios_anchor; 1598 size_t smbios_tables_len, smbios_anchor_len; 1599 struct smbios_phys_mem_area mem_array; 1600 const char *product = "QEMU Virtual Machine"; 1601 1602 if (kvm_enabled()) { 1603 product = "KVM Virtual Machine"; 1604 } 1605 1606 smbios_set_defaults("QEMU", product, 1607 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1608 true, SMBIOS_ENTRY_POINT_TYPE_64); 1609 1610 /* build the array of physical mem area from base_memmap */ 1611 mem_array.address = vms->memmap[VIRT_MEM].base; 1612 mem_array.length = ms->ram_size; 1613 1614 smbios_get_tables(ms, &mem_array, 1, 1615 &smbios_tables, &smbios_tables_len, 1616 &smbios_anchor, &smbios_anchor_len, 1617 &error_fatal); 1618 1619 if (smbios_anchor) { 1620 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1621 smbios_tables, smbios_tables_len); 1622 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1623 smbios_anchor, smbios_anchor_len); 1624 } 1625 } 1626 1627 static 1628 void virt_machine_done(Notifier *notifier, void *data) 1629 { 1630 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1631 machine_done); 1632 MachineState *ms = MACHINE(vms); 1633 ARMCPU *cpu = ARM_CPU(first_cpu); 1634 struct arm_boot_info *info = &vms->bootinfo; 1635 AddressSpace *as = arm_boot_address_space(cpu, info); 1636 1637 /* 1638 * If the user provided a dtb, we assume the dynamic sysbus nodes 1639 * already are integrated there. This corresponds to a use case where 1640 * the dynamic sysbus nodes are complex and their generation is not yet 1641 * supported. In that case the user can take charge of the guest dt 1642 * while qemu takes charge of the qom stuff. 1643 */ 1644 if (info->dtb_filename == NULL) { 1645 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1646 vms->memmap[VIRT_PLATFORM_BUS].base, 1647 vms->memmap[VIRT_PLATFORM_BUS].size, 1648 vms->irqmap[VIRT_PLATFORM_BUS]); 1649 } 1650 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1651 exit(1); 1652 } 1653 1654 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1655 1656 virt_acpi_setup(vms); 1657 virt_build_smbios(vms); 1658 } 1659 1660 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1661 { 1662 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1663 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1664 1665 if (!vmc->disallow_affinity_adjustment) { 1666 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1667 * GIC's target-list limitations. 32-bit KVM hosts currently 1668 * always create clusters of 4 CPUs, but that is expected to 1669 * change when they gain support for gicv3. When KVM is enabled 1670 * it will override the changes we make here, therefore our 1671 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1672 * and to improve SGI efficiency. 1673 */ 1674 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1675 clustersz = GIC_TARGETLIST_BITS; 1676 } else { 1677 clustersz = GICV3_TARGETLIST_BITS; 1678 } 1679 } 1680 return arm_build_mp_affinity(idx, clustersz); 1681 } 1682 1683 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1684 int index) 1685 { 1686 bool *enabled_array[] = { 1687 &vms->highmem_redists, 1688 &vms->highmem_ecam, 1689 &vms->highmem_mmio, 1690 }; 1691 1692 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1693 ARRAY_SIZE(enabled_array)); 1694 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1695 1696 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1697 } 1698 1699 static void virt_set_high_memmap(VirtMachineState *vms, 1700 hwaddr base, int pa_bits) 1701 { 1702 hwaddr region_base, region_size; 1703 bool *region_enabled, fits; 1704 int i; 1705 1706 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1707 region_enabled = virt_get_high_memmap_enabled(vms, i); 1708 region_base = ROUND_UP(base, extended_memmap[i].size); 1709 region_size = extended_memmap[i].size; 1710 1711 vms->memmap[i].base = region_base; 1712 vms->memmap[i].size = region_size; 1713 1714 /* 1715 * Check each device to see if it fits in the PA space, 1716 * moving highest_gpa as we go. For compatibility, move 1717 * highest_gpa for disabled fitting devices as well, if 1718 * the compact layout has been disabled. 1719 * 1720 * For each device that doesn't fit, disable it. 1721 */ 1722 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1723 *region_enabled &= fits; 1724 if (vms->highmem_compact && !*region_enabled) { 1725 continue; 1726 } 1727 1728 base = region_base + region_size; 1729 if (fits) { 1730 vms->highest_gpa = base - 1; 1731 } 1732 } 1733 } 1734 1735 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1736 { 1737 MachineState *ms = MACHINE(vms); 1738 hwaddr base, device_memory_base, device_memory_size, memtop; 1739 int i; 1740 1741 vms->memmap = extended_memmap; 1742 1743 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1744 vms->memmap[i] = base_memmap[i]; 1745 } 1746 1747 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1748 error_report("unsupported number of memory slots: %"PRIu64, 1749 ms->ram_slots); 1750 exit(EXIT_FAILURE); 1751 } 1752 1753 /* 1754 * !highmem is exactly the same as limiting the PA space to 32bit, 1755 * irrespective of the underlying capabilities of the HW. 1756 */ 1757 if (!vms->highmem) { 1758 pa_bits = 32; 1759 } 1760 1761 /* 1762 * We compute the base of the high IO region depending on the 1763 * amount of initial and device memory. The device memory start/size 1764 * is aligned on 1GiB. We never put the high IO region below 256GiB 1765 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1766 * The device region size assumes 1GiB page max alignment per slot. 1767 */ 1768 device_memory_base = 1769 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1770 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1771 1772 /* Base address of the high IO region */ 1773 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1774 if (memtop > BIT_ULL(pa_bits)) { 1775 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1776 pa_bits, memtop - BIT_ULL(pa_bits)); 1777 exit(EXIT_FAILURE); 1778 } 1779 if (base < device_memory_base) { 1780 error_report("maxmem/slots too huge"); 1781 exit(EXIT_FAILURE); 1782 } 1783 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1784 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1785 } 1786 1787 /* We know for sure that at least the memory fits in the PA space */ 1788 vms->highest_gpa = memtop - 1; 1789 1790 virt_set_high_memmap(vms, base, pa_bits); 1791 1792 if (device_memory_size > 0) { 1793 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1794 } 1795 } 1796 1797 static VirtGICType finalize_gic_version_do(const char *accel_name, 1798 VirtGICType gic_version, 1799 int gics_supported, 1800 unsigned int max_cpus) 1801 { 1802 /* Convert host/max/nosel to GIC version number */ 1803 switch (gic_version) { 1804 case VIRT_GIC_VERSION_HOST: 1805 if (!kvm_enabled()) { 1806 error_report("gic-version=host requires KVM"); 1807 exit(1); 1808 } 1809 1810 /* For KVM, gic-version=host means gic-version=max */ 1811 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1812 gics_supported, max_cpus); 1813 case VIRT_GIC_VERSION_MAX: 1814 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1815 gic_version = VIRT_GIC_VERSION_4; 1816 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1817 gic_version = VIRT_GIC_VERSION_3; 1818 } else { 1819 gic_version = VIRT_GIC_VERSION_2; 1820 } 1821 break; 1822 case VIRT_GIC_VERSION_NOSEL: 1823 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1824 max_cpus <= GIC_NCPU) { 1825 gic_version = VIRT_GIC_VERSION_2; 1826 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1827 /* 1828 * in case the host does not support v2 emulation or 1829 * the end-user requested more than 8 VCPUs we now default 1830 * to v3. In any case defaulting to v2 would be broken. 1831 */ 1832 gic_version = VIRT_GIC_VERSION_3; 1833 } else if (max_cpus > GIC_NCPU) { 1834 error_report("%s only supports GICv2 emulation but more than 8 " 1835 "vcpus are requested", accel_name); 1836 exit(1); 1837 } 1838 break; 1839 case VIRT_GIC_VERSION_2: 1840 case VIRT_GIC_VERSION_3: 1841 case VIRT_GIC_VERSION_4: 1842 break; 1843 } 1844 1845 /* Check chosen version is effectively supported */ 1846 switch (gic_version) { 1847 case VIRT_GIC_VERSION_2: 1848 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1849 error_report("%s does not support GICv2 emulation", accel_name); 1850 exit(1); 1851 } 1852 break; 1853 case VIRT_GIC_VERSION_3: 1854 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1855 error_report("%s does not support GICv3 emulation", accel_name); 1856 exit(1); 1857 } 1858 break; 1859 case VIRT_GIC_VERSION_4: 1860 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1861 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1862 accel_name); 1863 exit(1); 1864 } 1865 break; 1866 default: 1867 error_report("logic error in finalize_gic_version"); 1868 exit(1); 1869 break; 1870 } 1871 1872 return gic_version; 1873 } 1874 1875 /* 1876 * finalize_gic_version - Determines the final gic_version 1877 * according to the gic-version property 1878 * 1879 * Default GIC type is v2 1880 */ 1881 static void finalize_gic_version(VirtMachineState *vms) 1882 { 1883 const char *accel_name = current_accel_name(); 1884 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1885 int gics_supported = 0; 1886 1887 /* Determine which GIC versions the current environment supports */ 1888 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1889 int probe_bitmap = kvm_arm_vgic_probe(); 1890 1891 if (!probe_bitmap) { 1892 error_report("Unable to determine GIC version supported by host"); 1893 exit(1); 1894 } 1895 1896 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1897 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1898 } 1899 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1900 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1901 } 1902 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1903 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1904 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1905 accel_name = "KVM with kernel-irqchip=off"; 1906 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1907 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1908 if (module_object_class_by_name("arm-gicv3")) { 1909 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1910 if (vms->virt) { 1911 /* GICv4 only makes sense if CPU has EL2 */ 1912 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1913 } 1914 } 1915 } else { 1916 error_report("Unsupported accelerator, can not determine GIC support"); 1917 exit(1); 1918 } 1919 1920 /* 1921 * Then convert helpers like host/max to concrete GIC versions and ensure 1922 * the desired version is supported 1923 */ 1924 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1925 gics_supported, max_cpus); 1926 } 1927 1928 /* 1929 * virt_cpu_post_init() must be called after the CPUs have 1930 * been realized and the GIC has been created. 1931 */ 1932 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1933 { 1934 int max_cpus = MACHINE(vms)->smp.max_cpus; 1935 bool aarch64, pmu, steal_time; 1936 CPUState *cpu; 1937 1938 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1939 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1940 steal_time = object_property_get_bool(OBJECT(first_cpu), 1941 "kvm-steal-time", NULL); 1942 1943 if (kvm_enabled()) { 1944 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1945 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1946 1947 if (steal_time) { 1948 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1949 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1950 1951 /* The memory region size must be a multiple of host page size. */ 1952 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1953 1954 if (pvtime_size > pvtime_reg_size) { 1955 error_report("pvtime requires a %" HWADDR_PRId 1956 " byte memory region for %d CPUs," 1957 " but only %" HWADDR_PRId " has been reserved", 1958 pvtime_size, max_cpus, pvtime_reg_size); 1959 exit(1); 1960 } 1961 1962 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1963 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1964 } 1965 1966 CPU_FOREACH(cpu) { 1967 if (pmu) { 1968 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1969 if (kvm_irqchip_in_kernel()) { 1970 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 1971 } 1972 kvm_arm_pmu_init(ARM_CPU(cpu)); 1973 } 1974 if (steal_time) { 1975 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 1976 + cpu->cpu_index 1977 * PVTIME_SIZE_PER_CPU); 1978 } 1979 } 1980 } else { 1981 if (aarch64 && vms->highmem) { 1982 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1983 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1984 1985 if (pamax < requested_pa_size) { 1986 error_report("VCPU supports less PA bits (%d) than " 1987 "requested by the memory map (%d)", 1988 pamax, requested_pa_size); 1989 exit(1); 1990 } 1991 } 1992 } 1993 } 1994 1995 static void machvirt_init(MachineState *machine) 1996 { 1997 VirtMachineState *vms = VIRT_MACHINE(machine); 1998 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1999 MachineClass *mc = MACHINE_GET_CLASS(machine); 2000 const CPUArchIdList *possible_cpus; 2001 MemoryRegion *sysmem = get_system_memory(); 2002 MemoryRegion *secure_sysmem = NULL; 2003 MemoryRegion *tag_sysmem = NULL; 2004 MemoryRegion *secure_tag_sysmem = NULL; 2005 int n, virt_max_cpus; 2006 bool firmware_loaded; 2007 bool aarch64 = true; 2008 bool has_ged = !vmc->no_ged; 2009 unsigned int smp_cpus = machine->smp.cpus; 2010 unsigned int max_cpus = machine->smp.max_cpus; 2011 2012 possible_cpus = mc->possible_cpu_arch_ids(machine); 2013 2014 /* 2015 * In accelerated mode, the memory map is computed earlier in kvm_type() 2016 * to create a VM with the right number of IPA bits. 2017 */ 2018 if (!vms->memmap) { 2019 Object *cpuobj; 2020 ARMCPU *armcpu; 2021 int pa_bits; 2022 2023 /* 2024 * Instantiate a temporary CPU object to find out about what 2025 * we are about to deal with. Once this is done, get rid of 2026 * the object. 2027 */ 2028 cpuobj = object_new(possible_cpus->cpus[0].type); 2029 armcpu = ARM_CPU(cpuobj); 2030 2031 pa_bits = arm_pamax(armcpu); 2032 2033 object_unref(cpuobj); 2034 2035 virt_set_memmap(vms, pa_bits); 2036 } 2037 2038 /* We can probe only here because during property set 2039 * KVM is not available yet 2040 */ 2041 finalize_gic_version(vms); 2042 2043 if (vms->secure) { 2044 /* 2045 * The Secure view of the world is the same as the NonSecure, 2046 * but with a few extra devices. Create it as a container region 2047 * containing the system memory at low priority; any secure-only 2048 * devices go in at higher priority and take precedence. 2049 */ 2050 secure_sysmem = g_new(MemoryRegion, 1); 2051 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2052 UINT64_MAX); 2053 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2054 } 2055 2056 firmware_loaded = virt_firmware_init(vms, sysmem, 2057 secure_sysmem ?: sysmem); 2058 2059 /* If we have an EL3 boot ROM then the assumption is that it will 2060 * implement PSCI itself, so disable QEMU's internal implementation 2061 * so it doesn't get in the way. Instead of starting secondary 2062 * CPUs in PSCI powerdown state we will start them all running and 2063 * let the boot ROM sort them out. 2064 * The usual case is that we do use QEMU's PSCI implementation; 2065 * if the guest has EL2 then we will use SMC as the conduit, 2066 * and otherwise we will use HVC (for backwards compatibility and 2067 * because if we're using KVM then we must use HVC). 2068 */ 2069 if (vms->secure && firmware_loaded) { 2070 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2071 } else if (vms->virt) { 2072 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2073 } else { 2074 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2075 } 2076 2077 /* 2078 * The maximum number of CPUs depends on the GIC version, or on how 2079 * many redistributors we can fit into the memory map (which in turn 2080 * depends on whether this is a GICv3 or v4). 2081 */ 2082 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2083 virt_max_cpus = GIC_NCPU; 2084 } else { 2085 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2086 if (vms->highmem_redists) { 2087 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2088 } 2089 } 2090 2091 if (max_cpus > virt_max_cpus) { 2092 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2093 "supported by machine 'mach-virt' (%d)", 2094 max_cpus, virt_max_cpus); 2095 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2096 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2097 } 2098 2099 exit(1); 2100 } 2101 2102 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2103 error_report("mach-virt: %s does not support providing " 2104 "Security extensions (TrustZone) to the guest CPU", 2105 current_accel_name()); 2106 exit(1); 2107 } 2108 2109 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2110 error_report("mach-virt: %s does not support providing " 2111 "Virtualization extensions to the guest CPU", 2112 current_accel_name()); 2113 exit(1); 2114 } 2115 2116 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2117 error_report("mach-virt: %s does not support providing " 2118 "MTE to the guest CPU", 2119 current_accel_name()); 2120 exit(1); 2121 } 2122 2123 create_fdt(vms); 2124 2125 assert(possible_cpus->len == max_cpus); 2126 for (n = 0; n < possible_cpus->len; n++) { 2127 Object *cpuobj; 2128 CPUState *cs; 2129 2130 if (n >= smp_cpus) { 2131 break; 2132 } 2133 2134 cpuobj = object_new(possible_cpus->cpus[n].type); 2135 object_property_set_int(cpuobj, "mp-affinity", 2136 possible_cpus->cpus[n].arch_id, NULL); 2137 2138 cs = CPU(cpuobj); 2139 cs->cpu_index = n; 2140 2141 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2142 &error_fatal); 2143 2144 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2145 2146 if (!vms->secure) { 2147 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2148 } 2149 2150 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2151 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2152 } 2153 2154 if (vmc->kvm_no_adjvtime && 2155 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2156 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2157 } 2158 2159 if (vmc->no_kvm_steal_time && 2160 object_property_find(cpuobj, "kvm-steal-time")) { 2161 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2162 } 2163 2164 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2165 object_property_set_bool(cpuobj, "pmu", false, NULL); 2166 } 2167 2168 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2169 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2170 } 2171 2172 if (object_property_find(cpuobj, "reset-cbar")) { 2173 object_property_set_int(cpuobj, "reset-cbar", 2174 vms->memmap[VIRT_CPUPERIPHS].base, 2175 &error_abort); 2176 } 2177 2178 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2179 &error_abort); 2180 if (vms->secure) { 2181 object_property_set_link(cpuobj, "secure-memory", 2182 OBJECT(secure_sysmem), &error_abort); 2183 } 2184 2185 if (vms->mte) { 2186 /* Create the memory region only once, but link to all cpus. */ 2187 if (!tag_sysmem) { 2188 /* 2189 * The property exists only if MemTag is supported. 2190 * If it is, we must allocate the ram to back that up. 2191 */ 2192 if (!object_property_find(cpuobj, "tag-memory")) { 2193 error_report("MTE requested, but not supported " 2194 "by the guest CPU"); 2195 exit(1); 2196 } 2197 2198 tag_sysmem = g_new(MemoryRegion, 1); 2199 memory_region_init(tag_sysmem, OBJECT(machine), 2200 "tag-memory", UINT64_MAX / 32); 2201 2202 if (vms->secure) { 2203 secure_tag_sysmem = g_new(MemoryRegion, 1); 2204 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2205 "secure-tag-memory", UINT64_MAX / 32); 2206 2207 /* As with ram, secure-tag takes precedence over tag. */ 2208 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2209 tag_sysmem, -1); 2210 } 2211 } 2212 2213 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2214 &error_abort); 2215 if (vms->secure) { 2216 object_property_set_link(cpuobj, "secure-tag-memory", 2217 OBJECT(secure_tag_sysmem), 2218 &error_abort); 2219 } 2220 } 2221 2222 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2223 object_unref(cpuobj); 2224 } 2225 fdt_add_timer_nodes(vms); 2226 fdt_add_cpu_nodes(vms); 2227 2228 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2229 machine->ram); 2230 2231 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2232 2233 create_gic(vms, sysmem); 2234 2235 virt_cpu_post_init(vms, sysmem); 2236 2237 fdt_add_pmu_nodes(vms); 2238 2239 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2240 2241 if (vms->secure) { 2242 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2243 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2244 } 2245 2246 if (tag_sysmem) { 2247 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2248 machine->ram_size, "mach-virt.tag"); 2249 } 2250 2251 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2252 2253 create_rtc(vms); 2254 2255 create_pcie(vms); 2256 2257 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2258 vms->acpi_dev = create_acpi_ged(vms); 2259 } else { 2260 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2261 } 2262 2263 if (vms->secure && !vmc->no_secure_gpio) { 2264 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2265 } 2266 2267 /* connect powerdown request */ 2268 vms->powerdown_notifier.notify = virt_powerdown_req; 2269 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2270 2271 /* Create mmio transports, so the user can create virtio backends 2272 * (which will be automatically plugged in to the transports). If 2273 * no backend is created the transport will just sit harmlessly idle. 2274 */ 2275 create_virtio_devices(vms); 2276 2277 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2278 rom_set_fw(vms->fw_cfg); 2279 2280 create_platform_bus(vms); 2281 2282 if (machine->nvdimms_state->is_enabled) { 2283 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2284 .space_id = AML_AS_SYSTEM_MEMORY, 2285 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2286 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2287 }; 2288 2289 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2290 arm_virt_nvdimm_acpi_dsmio, 2291 vms->fw_cfg, OBJECT(vms)); 2292 } 2293 2294 vms->bootinfo.ram_size = machine->ram_size; 2295 vms->bootinfo.board_id = -1; 2296 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2297 vms->bootinfo.get_dtb = machvirt_dtb; 2298 vms->bootinfo.skip_dtb_autoload = true; 2299 vms->bootinfo.firmware_loaded = firmware_loaded; 2300 vms->bootinfo.psci_conduit = vms->psci_conduit; 2301 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2302 2303 vms->machine_done.notify = virt_machine_done; 2304 qemu_add_machine_init_done_notifier(&vms->machine_done); 2305 } 2306 2307 static bool virt_get_secure(Object *obj, Error **errp) 2308 { 2309 VirtMachineState *vms = VIRT_MACHINE(obj); 2310 2311 return vms->secure; 2312 } 2313 2314 static void virt_set_secure(Object *obj, bool value, Error **errp) 2315 { 2316 VirtMachineState *vms = VIRT_MACHINE(obj); 2317 2318 vms->secure = value; 2319 } 2320 2321 static bool virt_get_virt(Object *obj, Error **errp) 2322 { 2323 VirtMachineState *vms = VIRT_MACHINE(obj); 2324 2325 return vms->virt; 2326 } 2327 2328 static void virt_set_virt(Object *obj, bool value, Error **errp) 2329 { 2330 VirtMachineState *vms = VIRT_MACHINE(obj); 2331 2332 vms->virt = value; 2333 } 2334 2335 static bool virt_get_highmem(Object *obj, Error **errp) 2336 { 2337 VirtMachineState *vms = VIRT_MACHINE(obj); 2338 2339 return vms->highmem; 2340 } 2341 2342 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2343 { 2344 VirtMachineState *vms = VIRT_MACHINE(obj); 2345 2346 vms->highmem = value; 2347 } 2348 2349 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2350 { 2351 VirtMachineState *vms = VIRT_MACHINE(obj); 2352 2353 return vms->highmem_compact; 2354 } 2355 2356 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2357 { 2358 VirtMachineState *vms = VIRT_MACHINE(obj); 2359 2360 vms->highmem_compact = value; 2361 } 2362 2363 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2364 { 2365 VirtMachineState *vms = VIRT_MACHINE(obj); 2366 2367 return vms->highmem_redists; 2368 } 2369 2370 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2371 { 2372 VirtMachineState *vms = VIRT_MACHINE(obj); 2373 2374 vms->highmem_redists = value; 2375 } 2376 2377 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2378 { 2379 VirtMachineState *vms = VIRT_MACHINE(obj); 2380 2381 return vms->highmem_ecam; 2382 } 2383 2384 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2385 { 2386 VirtMachineState *vms = VIRT_MACHINE(obj); 2387 2388 vms->highmem_ecam = value; 2389 } 2390 2391 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2392 { 2393 VirtMachineState *vms = VIRT_MACHINE(obj); 2394 2395 return vms->highmem_mmio; 2396 } 2397 2398 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2399 { 2400 VirtMachineState *vms = VIRT_MACHINE(obj); 2401 2402 vms->highmem_mmio = value; 2403 } 2404 2405 2406 static bool virt_get_its(Object *obj, Error **errp) 2407 { 2408 VirtMachineState *vms = VIRT_MACHINE(obj); 2409 2410 return vms->its; 2411 } 2412 2413 static void virt_set_its(Object *obj, bool value, Error **errp) 2414 { 2415 VirtMachineState *vms = VIRT_MACHINE(obj); 2416 2417 vms->its = value; 2418 } 2419 2420 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2421 { 2422 VirtMachineState *vms = VIRT_MACHINE(obj); 2423 2424 return vms->dtb_randomness; 2425 } 2426 2427 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2428 { 2429 VirtMachineState *vms = VIRT_MACHINE(obj); 2430 2431 vms->dtb_randomness = value; 2432 } 2433 2434 static char *virt_get_oem_id(Object *obj, Error **errp) 2435 { 2436 VirtMachineState *vms = VIRT_MACHINE(obj); 2437 2438 return g_strdup(vms->oem_id); 2439 } 2440 2441 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2442 { 2443 VirtMachineState *vms = VIRT_MACHINE(obj); 2444 size_t len = strlen(value); 2445 2446 if (len > 6) { 2447 error_setg(errp, 2448 "User specified oem-id value is bigger than 6 bytes in size"); 2449 return; 2450 } 2451 2452 strncpy(vms->oem_id, value, 6); 2453 } 2454 2455 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2456 { 2457 VirtMachineState *vms = VIRT_MACHINE(obj); 2458 2459 return g_strdup(vms->oem_table_id); 2460 } 2461 2462 static void virt_set_oem_table_id(Object *obj, const char *value, 2463 Error **errp) 2464 { 2465 VirtMachineState *vms = VIRT_MACHINE(obj); 2466 size_t len = strlen(value); 2467 2468 if (len > 8) { 2469 error_setg(errp, 2470 "User specified oem-table-id value is bigger than 8 bytes in size"); 2471 return; 2472 } 2473 strncpy(vms->oem_table_id, value, 8); 2474 } 2475 2476 2477 bool virt_is_acpi_enabled(VirtMachineState *vms) 2478 { 2479 if (vms->acpi == ON_OFF_AUTO_OFF) { 2480 return false; 2481 } 2482 return true; 2483 } 2484 2485 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2486 void *opaque, Error **errp) 2487 { 2488 VirtMachineState *vms = VIRT_MACHINE(obj); 2489 OnOffAuto acpi = vms->acpi; 2490 2491 visit_type_OnOffAuto(v, name, &acpi, errp); 2492 } 2493 2494 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2495 void *opaque, Error **errp) 2496 { 2497 VirtMachineState *vms = VIRT_MACHINE(obj); 2498 2499 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2500 } 2501 2502 static bool virt_get_ras(Object *obj, Error **errp) 2503 { 2504 VirtMachineState *vms = VIRT_MACHINE(obj); 2505 2506 return vms->ras; 2507 } 2508 2509 static void virt_set_ras(Object *obj, bool value, Error **errp) 2510 { 2511 VirtMachineState *vms = VIRT_MACHINE(obj); 2512 2513 vms->ras = value; 2514 } 2515 2516 static bool virt_get_mte(Object *obj, Error **errp) 2517 { 2518 VirtMachineState *vms = VIRT_MACHINE(obj); 2519 2520 return vms->mte; 2521 } 2522 2523 static void virt_set_mte(Object *obj, bool value, Error **errp) 2524 { 2525 VirtMachineState *vms = VIRT_MACHINE(obj); 2526 2527 vms->mte = value; 2528 } 2529 2530 static char *virt_get_gic_version(Object *obj, Error **errp) 2531 { 2532 VirtMachineState *vms = VIRT_MACHINE(obj); 2533 const char *val; 2534 2535 switch (vms->gic_version) { 2536 case VIRT_GIC_VERSION_4: 2537 val = "4"; 2538 break; 2539 case VIRT_GIC_VERSION_3: 2540 val = "3"; 2541 break; 2542 default: 2543 val = "2"; 2544 break; 2545 } 2546 return g_strdup(val); 2547 } 2548 2549 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2550 { 2551 VirtMachineState *vms = VIRT_MACHINE(obj); 2552 2553 if (!strcmp(value, "4")) { 2554 vms->gic_version = VIRT_GIC_VERSION_4; 2555 } else if (!strcmp(value, "3")) { 2556 vms->gic_version = VIRT_GIC_VERSION_3; 2557 } else if (!strcmp(value, "2")) { 2558 vms->gic_version = VIRT_GIC_VERSION_2; 2559 } else if (!strcmp(value, "host")) { 2560 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2561 } else if (!strcmp(value, "max")) { 2562 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2563 } else { 2564 error_setg(errp, "Invalid gic-version value"); 2565 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2566 } 2567 } 2568 2569 static char *virt_get_iommu(Object *obj, Error **errp) 2570 { 2571 VirtMachineState *vms = VIRT_MACHINE(obj); 2572 2573 switch (vms->iommu) { 2574 case VIRT_IOMMU_NONE: 2575 return g_strdup("none"); 2576 case VIRT_IOMMU_SMMUV3: 2577 return g_strdup("smmuv3"); 2578 default: 2579 g_assert_not_reached(); 2580 } 2581 } 2582 2583 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2584 { 2585 VirtMachineState *vms = VIRT_MACHINE(obj); 2586 2587 if (!strcmp(value, "smmuv3")) { 2588 vms->iommu = VIRT_IOMMU_SMMUV3; 2589 } else if (!strcmp(value, "none")) { 2590 vms->iommu = VIRT_IOMMU_NONE; 2591 } else { 2592 error_setg(errp, "Invalid iommu value"); 2593 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2594 } 2595 } 2596 2597 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2598 { 2599 VirtMachineState *vms = VIRT_MACHINE(obj); 2600 2601 return vms->default_bus_bypass_iommu; 2602 } 2603 2604 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2605 Error **errp) 2606 { 2607 VirtMachineState *vms = VIRT_MACHINE(obj); 2608 2609 vms->default_bus_bypass_iommu = value; 2610 } 2611 2612 static CpuInstanceProperties 2613 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2614 { 2615 MachineClass *mc = MACHINE_GET_CLASS(ms); 2616 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2617 2618 assert(cpu_index < possible_cpus->len); 2619 return possible_cpus->cpus[cpu_index].props; 2620 } 2621 2622 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2623 { 2624 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2625 2626 return socket_id % ms->numa_state->num_nodes; 2627 } 2628 2629 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2630 { 2631 int n; 2632 unsigned int max_cpus = ms->smp.max_cpus; 2633 VirtMachineState *vms = VIRT_MACHINE(ms); 2634 MachineClass *mc = MACHINE_GET_CLASS(vms); 2635 2636 if (ms->possible_cpus) { 2637 assert(ms->possible_cpus->len == max_cpus); 2638 return ms->possible_cpus; 2639 } 2640 2641 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2642 sizeof(CPUArchId) * max_cpus); 2643 ms->possible_cpus->len = max_cpus; 2644 for (n = 0; n < ms->possible_cpus->len; n++) { 2645 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2646 ms->possible_cpus->cpus[n].arch_id = 2647 virt_cpu_mp_affinity(vms, n); 2648 2649 assert(!mc->smp_props.dies_supported); 2650 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2651 ms->possible_cpus->cpus[n].props.socket_id = 2652 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2653 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2654 ms->possible_cpus->cpus[n].props.cluster_id = 2655 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2656 ms->possible_cpus->cpus[n].props.has_core_id = true; 2657 ms->possible_cpus->cpus[n].props.core_id = 2658 (n / ms->smp.threads) % ms->smp.cores; 2659 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2660 ms->possible_cpus->cpus[n].props.thread_id = 2661 n % ms->smp.threads; 2662 } 2663 return ms->possible_cpus; 2664 } 2665 2666 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2667 Error **errp) 2668 { 2669 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2670 const MachineState *ms = MACHINE(hotplug_dev); 2671 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2672 2673 if (!vms->acpi_dev) { 2674 error_setg(errp, 2675 "memory hotplug is not enabled: missing acpi-ged device"); 2676 return; 2677 } 2678 2679 if (vms->mte) { 2680 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2681 return; 2682 } 2683 2684 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2685 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2686 return; 2687 } 2688 2689 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2690 } 2691 2692 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2693 DeviceState *dev, Error **errp) 2694 { 2695 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2696 MachineState *ms = MACHINE(hotplug_dev); 2697 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2698 2699 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2700 2701 if (is_nvdimm) { 2702 nvdimm_plug(ms->nvdimms_state); 2703 } 2704 2705 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2706 dev, &error_abort); 2707 } 2708 2709 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2710 DeviceState *dev, Error **errp) 2711 { 2712 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2713 2714 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2715 virt_memory_pre_plug(hotplug_dev, dev, errp); 2716 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2717 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2718 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2719 hwaddr db_start = 0, db_end = 0; 2720 QList *reserved_regions; 2721 char *resv_prop_str; 2722 2723 if (vms->iommu != VIRT_IOMMU_NONE) { 2724 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2725 return; 2726 } 2727 2728 switch (vms->msi_controller) { 2729 case VIRT_MSI_CTRL_NONE: 2730 return; 2731 case VIRT_MSI_CTRL_ITS: 2732 /* GITS_TRANSLATER page */ 2733 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2734 db_end = base_memmap[VIRT_GIC_ITS].base + 2735 base_memmap[VIRT_GIC_ITS].size - 1; 2736 break; 2737 case VIRT_MSI_CTRL_GICV2M: 2738 /* MSI_SETSPI_NS page */ 2739 db_start = base_memmap[VIRT_GIC_V2M].base; 2740 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2741 break; 2742 } 2743 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2744 db_start, db_end, 2745 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2746 2747 reserved_regions = qlist_new(); 2748 qlist_append_str(reserved_regions, resv_prop_str); 2749 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2750 g_free(resv_prop_str); 2751 } 2752 } 2753 2754 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2755 DeviceState *dev, Error **errp) 2756 { 2757 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2758 2759 if (vms->platform_bus_dev) { 2760 MachineClass *mc = MACHINE_GET_CLASS(vms); 2761 2762 if (device_is_dynamic_sysbus(mc, dev)) { 2763 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2764 SYS_BUS_DEVICE(dev)); 2765 } 2766 } 2767 2768 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2769 virt_memory_plug(hotplug_dev, dev, errp); 2770 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2771 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2772 } 2773 2774 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2775 PCIDevice *pdev = PCI_DEVICE(dev); 2776 2777 vms->iommu = VIRT_IOMMU_VIRTIO; 2778 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2779 create_virtio_iommu_dt_bindings(vms); 2780 } 2781 } 2782 2783 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2784 DeviceState *dev, Error **errp) 2785 { 2786 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2787 2788 if (!vms->acpi_dev) { 2789 error_setg(errp, 2790 "memory hotplug is not enabled: missing acpi-ged device"); 2791 return; 2792 } 2793 2794 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2795 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2796 return; 2797 } 2798 2799 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2800 errp); 2801 } 2802 2803 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2804 DeviceState *dev, Error **errp) 2805 { 2806 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2807 Error *local_err = NULL; 2808 2809 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2810 if (local_err) { 2811 goto out; 2812 } 2813 2814 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2815 qdev_unrealize(dev); 2816 2817 out: 2818 error_propagate(errp, local_err); 2819 } 2820 2821 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2822 DeviceState *dev, Error **errp) 2823 { 2824 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2825 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2826 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2827 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2828 errp); 2829 } else { 2830 error_setg(errp, "device unplug request for unsupported device" 2831 " type: %s", object_get_typename(OBJECT(dev))); 2832 } 2833 } 2834 2835 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2836 DeviceState *dev, Error **errp) 2837 { 2838 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2839 virt_dimm_unplug(hotplug_dev, dev, errp); 2840 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2841 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2842 } else { 2843 error_setg(errp, "virt: device unplug for unsupported device" 2844 " type: %s", object_get_typename(OBJECT(dev))); 2845 } 2846 } 2847 2848 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2849 DeviceState *dev) 2850 { 2851 MachineClass *mc = MACHINE_GET_CLASS(machine); 2852 2853 if (device_is_dynamic_sysbus(mc, dev) || 2854 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2855 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2856 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2857 return HOTPLUG_HANDLER(machine); 2858 } 2859 return NULL; 2860 } 2861 2862 /* 2863 * for arm64 kvm_type [7-0] encodes the requested number of bits 2864 * in the IPA address space 2865 */ 2866 static int virt_kvm_type(MachineState *ms, const char *type_str) 2867 { 2868 VirtMachineState *vms = VIRT_MACHINE(ms); 2869 int max_vm_pa_size, requested_pa_size; 2870 bool fixed_ipa; 2871 2872 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2873 2874 /* we freeze the memory map to compute the highest gpa */ 2875 virt_set_memmap(vms, max_vm_pa_size); 2876 2877 requested_pa_size = 64 - clz64(vms->highest_gpa); 2878 2879 /* 2880 * KVM requires the IPA size to be at least 32 bits. 2881 */ 2882 if (requested_pa_size < 32) { 2883 requested_pa_size = 32; 2884 } 2885 2886 if (requested_pa_size > max_vm_pa_size) { 2887 error_report("-m and ,maxmem option values " 2888 "require an IPA range (%d bits) larger than " 2889 "the one supported by the host (%d bits)", 2890 requested_pa_size, max_vm_pa_size); 2891 return -1; 2892 } 2893 /* 2894 * We return the requested PA log size, unless KVM only supports 2895 * the implicit legacy 40b IPA setting, in which case the kvm_type 2896 * must be 0. 2897 */ 2898 return fixed_ipa ? 0 : requested_pa_size; 2899 } 2900 2901 static void virt_machine_class_init(ObjectClass *oc, void *data) 2902 { 2903 MachineClass *mc = MACHINE_CLASS(oc); 2904 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2905 static const char * const valid_cpu_types[] = { 2906 #ifdef CONFIG_TCG 2907 ARM_CPU_TYPE_NAME("cortex-a7"), 2908 ARM_CPU_TYPE_NAME("cortex-a15"), 2909 #ifdef TARGET_AARCH64 2910 ARM_CPU_TYPE_NAME("cortex-a35"), 2911 ARM_CPU_TYPE_NAME("cortex-a55"), 2912 ARM_CPU_TYPE_NAME("cortex-a72"), 2913 ARM_CPU_TYPE_NAME("cortex-a76"), 2914 ARM_CPU_TYPE_NAME("cortex-a710"), 2915 ARM_CPU_TYPE_NAME("a64fx"), 2916 ARM_CPU_TYPE_NAME("neoverse-n1"), 2917 ARM_CPU_TYPE_NAME("neoverse-v1"), 2918 ARM_CPU_TYPE_NAME("neoverse-n2"), 2919 #endif /* TARGET_AARCH64 */ 2920 #endif /* CONFIG_TCG */ 2921 #ifdef TARGET_AARCH64 2922 ARM_CPU_TYPE_NAME("cortex-a53"), 2923 ARM_CPU_TYPE_NAME("cortex-a57"), 2924 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 2925 ARM_CPU_TYPE_NAME("host"), 2926 #endif /* CONFIG_KVM || CONFIG_HVF */ 2927 #endif /* TARGET_AARCH64 */ 2928 ARM_CPU_TYPE_NAME("max"), 2929 NULL 2930 }; 2931 2932 mc->init = machvirt_init; 2933 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2934 * The value may be reduced later when we have more information about the 2935 * configuration of the particular instance. 2936 */ 2937 mc->max_cpus = 512; 2938 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2942 #ifdef CONFIG_TPM 2943 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2944 #endif 2945 mc->block_default_type = IF_VIRTIO; 2946 mc->no_cdrom = 1; 2947 mc->pci_allow_0_address = true; 2948 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2949 mc->minimum_page_bits = 12; 2950 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2951 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2952 #ifdef CONFIG_TCG 2953 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2954 #else 2955 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2956 #endif 2957 mc->valid_cpu_types = valid_cpu_types; 2958 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2959 mc->kvm_type = virt_kvm_type; 2960 assert(!mc->get_hotplug_handler); 2961 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2962 hc->pre_plug = virt_machine_device_pre_plug_cb; 2963 hc->plug = virt_machine_device_plug_cb; 2964 hc->unplug_request = virt_machine_device_unplug_request_cb; 2965 hc->unplug = virt_machine_device_unplug_cb; 2966 mc->nvdimm_supported = true; 2967 mc->smp_props.clusters_supported = true; 2968 mc->auto_enable_numa_with_memhp = true; 2969 mc->auto_enable_numa_with_memdev = true; 2970 /* platform instead of architectural choice */ 2971 mc->cpu_cluster_has_numa_boundary = true; 2972 mc->default_ram_id = "mach-virt.ram"; 2973 mc->default_nic = "virtio-net-pci"; 2974 2975 object_class_property_add(oc, "acpi", "OnOffAuto", 2976 virt_get_acpi, virt_set_acpi, 2977 NULL, NULL); 2978 object_class_property_set_description(oc, "acpi", 2979 "Enable ACPI"); 2980 object_class_property_add_bool(oc, "secure", virt_get_secure, 2981 virt_set_secure); 2982 object_class_property_set_description(oc, "secure", 2983 "Set on/off to enable/disable the ARM " 2984 "Security Extensions (TrustZone)"); 2985 2986 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2987 virt_set_virt); 2988 object_class_property_set_description(oc, "virtualization", 2989 "Set on/off to enable/disable emulating a " 2990 "guest CPU which implements the ARM " 2991 "Virtualization Extensions"); 2992 2993 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2994 virt_set_highmem); 2995 object_class_property_set_description(oc, "highmem", 2996 "Set on/off to enable/disable using " 2997 "physical address space above 32 bits"); 2998 2999 object_class_property_add_bool(oc, "compact-highmem", 3000 virt_get_compact_highmem, 3001 virt_set_compact_highmem); 3002 object_class_property_set_description(oc, "compact-highmem", 3003 "Set on/off to enable/disable compact " 3004 "layout for high memory regions"); 3005 3006 object_class_property_add_bool(oc, "highmem-redists", 3007 virt_get_highmem_redists, 3008 virt_set_highmem_redists); 3009 object_class_property_set_description(oc, "highmem-redists", 3010 "Set on/off to enable/disable high " 3011 "memory region for GICv3 or GICv4 " 3012 "redistributor"); 3013 3014 object_class_property_add_bool(oc, "highmem-ecam", 3015 virt_get_highmem_ecam, 3016 virt_set_highmem_ecam); 3017 object_class_property_set_description(oc, "highmem-ecam", 3018 "Set on/off to enable/disable high " 3019 "memory region for PCI ECAM"); 3020 3021 object_class_property_add_bool(oc, "highmem-mmio", 3022 virt_get_highmem_mmio, 3023 virt_set_highmem_mmio); 3024 object_class_property_set_description(oc, "highmem-mmio", 3025 "Set on/off to enable/disable high " 3026 "memory region for PCI MMIO"); 3027 3028 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3029 virt_set_gic_version); 3030 object_class_property_set_description(oc, "gic-version", 3031 "Set GIC version. " 3032 "Valid values are 2, 3, 4, host and max"); 3033 3034 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3035 object_class_property_set_description(oc, "iommu", 3036 "Set the IOMMU type. " 3037 "Valid values are none and smmuv3"); 3038 3039 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3040 virt_get_default_bus_bypass_iommu, 3041 virt_set_default_bus_bypass_iommu); 3042 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3043 "Set on/off to enable/disable " 3044 "bypass_iommu for default root bus"); 3045 3046 object_class_property_add_bool(oc, "ras", virt_get_ras, 3047 virt_set_ras); 3048 object_class_property_set_description(oc, "ras", 3049 "Set on/off to enable/disable reporting host memory errors " 3050 "to a KVM guest using ACPI and guest external abort exceptions"); 3051 3052 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3053 object_class_property_set_description(oc, "mte", 3054 "Set on/off to enable/disable emulating a " 3055 "guest CPU which implements the ARM " 3056 "Memory Tagging Extension"); 3057 3058 object_class_property_add_bool(oc, "its", virt_get_its, 3059 virt_set_its); 3060 object_class_property_set_description(oc, "its", 3061 "Set on/off to enable/disable " 3062 "ITS instantiation"); 3063 3064 object_class_property_add_bool(oc, "dtb-randomness", 3065 virt_get_dtb_randomness, 3066 virt_set_dtb_randomness); 3067 object_class_property_set_description(oc, "dtb-randomness", 3068 "Set off to disable passing random or " 3069 "non-deterministic dtb nodes to guest"); 3070 3071 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3072 virt_get_dtb_randomness, 3073 virt_set_dtb_randomness); 3074 object_class_property_set_description(oc, "dtb-kaslr-seed", 3075 "Deprecated synonym of dtb-randomness"); 3076 3077 object_class_property_add_str(oc, "x-oem-id", 3078 virt_get_oem_id, 3079 virt_set_oem_id); 3080 object_class_property_set_description(oc, "x-oem-id", 3081 "Override the default value of field OEMID " 3082 "in ACPI table header." 3083 "The string may be up to 6 bytes in size"); 3084 3085 3086 object_class_property_add_str(oc, "x-oem-table-id", 3087 virt_get_oem_table_id, 3088 virt_set_oem_table_id); 3089 object_class_property_set_description(oc, "x-oem-table-id", 3090 "Override the default value of field OEM Table ID " 3091 "in ACPI table header." 3092 "The string may be up to 8 bytes in size"); 3093 3094 } 3095 3096 static void virt_instance_init(Object *obj) 3097 { 3098 VirtMachineState *vms = VIRT_MACHINE(obj); 3099 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3100 3101 /* EL3 is disabled by default on virt: this makes us consistent 3102 * between KVM and TCG for this board, and it also allows us to 3103 * boot UEFI blobs which assume no TrustZone support. 3104 */ 3105 vms->secure = false; 3106 3107 /* EL2 is also disabled by default, for similar reasons */ 3108 vms->virt = false; 3109 3110 /* High memory is enabled by default */ 3111 vms->highmem = true; 3112 vms->highmem_compact = !vmc->no_highmem_compact; 3113 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3114 3115 vms->highmem_ecam = !vmc->no_highmem_ecam; 3116 vms->highmem_mmio = true; 3117 vms->highmem_redists = true; 3118 3119 if (vmc->no_its) { 3120 vms->its = false; 3121 } else { 3122 /* Default allows ITS instantiation */ 3123 vms->its = true; 3124 3125 if (vmc->no_tcg_its) { 3126 vms->tcg_its = false; 3127 } else { 3128 vms->tcg_its = true; 3129 } 3130 } 3131 3132 /* Default disallows iommu instantiation */ 3133 vms->iommu = VIRT_IOMMU_NONE; 3134 3135 /* The default root bus is attached to iommu by default */ 3136 vms->default_bus_bypass_iommu = false; 3137 3138 /* Default disallows RAS instantiation */ 3139 vms->ras = false; 3140 3141 /* MTE is disabled by default. */ 3142 vms->mte = false; 3143 3144 /* Supply kaslr-seed and rng-seed by default */ 3145 vms->dtb_randomness = true; 3146 3147 vms->irqmap = a15irqmap; 3148 3149 virt_flash_create(vms); 3150 3151 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3152 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3153 } 3154 3155 static const TypeInfo virt_machine_info = { 3156 .name = TYPE_VIRT_MACHINE, 3157 .parent = TYPE_MACHINE, 3158 .abstract = true, 3159 .instance_size = sizeof(VirtMachineState), 3160 .class_size = sizeof(VirtMachineClass), 3161 .class_init = virt_machine_class_init, 3162 .instance_init = virt_instance_init, 3163 .interfaces = (InterfaceInfo[]) { 3164 { TYPE_HOTPLUG_HANDLER }, 3165 { } 3166 }, 3167 }; 3168 3169 static void machvirt_machine_init(void) 3170 { 3171 type_register_static(&virt_machine_info); 3172 } 3173 type_init(machvirt_machine_init); 3174 3175 static void virt_machine_9_0_options(MachineClass *mc) 3176 { 3177 } 3178 DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) 3179 3180 static void virt_machine_8_2_options(MachineClass *mc) 3181 { 3182 virt_machine_9_0_options(mc); 3183 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3184 } 3185 DEFINE_VIRT_MACHINE(8, 2) 3186 3187 static void virt_machine_8_1_options(MachineClass *mc) 3188 { 3189 virt_machine_8_2_options(mc); 3190 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3191 } 3192 DEFINE_VIRT_MACHINE(8, 1) 3193 3194 static void virt_machine_8_0_options(MachineClass *mc) 3195 { 3196 virt_machine_8_1_options(mc); 3197 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3198 } 3199 DEFINE_VIRT_MACHINE(8, 0) 3200 3201 static void virt_machine_7_2_options(MachineClass *mc) 3202 { 3203 virt_machine_8_0_options(mc); 3204 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3205 } 3206 DEFINE_VIRT_MACHINE(7, 2) 3207 3208 static void virt_machine_7_1_options(MachineClass *mc) 3209 { 3210 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3211 3212 virt_machine_7_2_options(mc); 3213 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3214 /* Compact layout for high memory regions was introduced with 7.2 */ 3215 vmc->no_highmem_compact = true; 3216 } 3217 DEFINE_VIRT_MACHINE(7, 1) 3218 3219 static void virt_machine_7_0_options(MachineClass *mc) 3220 { 3221 virt_machine_7_1_options(mc); 3222 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3223 } 3224 DEFINE_VIRT_MACHINE(7, 0) 3225 3226 static void virt_machine_6_2_options(MachineClass *mc) 3227 { 3228 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3229 3230 virt_machine_7_0_options(mc); 3231 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3232 vmc->no_tcg_lpa2 = true; 3233 } 3234 DEFINE_VIRT_MACHINE(6, 2) 3235 3236 static void virt_machine_6_1_options(MachineClass *mc) 3237 { 3238 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3239 3240 virt_machine_6_2_options(mc); 3241 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3242 mc->smp_props.prefer_sockets = true; 3243 vmc->no_cpu_topology = true; 3244 3245 /* qemu ITS was introduced with 6.2 */ 3246 vmc->no_tcg_its = true; 3247 } 3248 DEFINE_VIRT_MACHINE(6, 1) 3249 3250 static void virt_machine_6_0_options(MachineClass *mc) 3251 { 3252 virt_machine_6_1_options(mc); 3253 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3254 } 3255 DEFINE_VIRT_MACHINE(6, 0) 3256 3257 static void virt_machine_5_2_options(MachineClass *mc) 3258 { 3259 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3260 3261 virt_machine_6_0_options(mc); 3262 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3263 vmc->no_secure_gpio = true; 3264 } 3265 DEFINE_VIRT_MACHINE(5, 2) 3266 3267 static void virt_machine_5_1_options(MachineClass *mc) 3268 { 3269 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3270 3271 virt_machine_5_2_options(mc); 3272 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3273 vmc->no_kvm_steal_time = true; 3274 } 3275 DEFINE_VIRT_MACHINE(5, 1) 3276 3277 static void virt_machine_5_0_options(MachineClass *mc) 3278 { 3279 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3280 3281 virt_machine_5_1_options(mc); 3282 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3283 mc->numa_mem_supported = true; 3284 vmc->acpi_expose_flash = true; 3285 mc->auto_enable_numa_with_memdev = false; 3286 } 3287 DEFINE_VIRT_MACHINE(5, 0) 3288 3289 static void virt_machine_4_2_options(MachineClass *mc) 3290 { 3291 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3292 3293 virt_machine_5_0_options(mc); 3294 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3295 vmc->kvm_no_adjvtime = true; 3296 } 3297 DEFINE_VIRT_MACHINE(4, 2) 3298 3299 static void virt_machine_4_1_options(MachineClass *mc) 3300 { 3301 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3302 3303 virt_machine_4_2_options(mc); 3304 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3305 vmc->no_ged = true; 3306 mc->auto_enable_numa_with_memhp = false; 3307 } 3308 DEFINE_VIRT_MACHINE(4, 1) 3309 3310 static void virt_machine_4_0_options(MachineClass *mc) 3311 { 3312 virt_machine_4_1_options(mc); 3313 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3314 } 3315 DEFINE_VIRT_MACHINE(4, 0) 3316 3317 static void virt_machine_3_1_options(MachineClass *mc) 3318 { 3319 virt_machine_4_0_options(mc); 3320 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3321 } 3322 DEFINE_VIRT_MACHINE(3, 1) 3323 3324 static void virt_machine_3_0_options(MachineClass *mc) 3325 { 3326 virt_machine_3_1_options(mc); 3327 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3328 } 3329 DEFINE_VIRT_MACHINE(3, 0) 3330 3331 static void virt_machine_2_12_options(MachineClass *mc) 3332 { 3333 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3334 3335 virt_machine_3_0_options(mc); 3336 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3337 vmc->no_highmem_ecam = true; 3338 mc->max_cpus = 255; 3339 } 3340 DEFINE_VIRT_MACHINE(2, 12) 3341 3342 static void virt_machine_2_11_options(MachineClass *mc) 3343 { 3344 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3345 3346 virt_machine_2_12_options(mc); 3347 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3348 vmc->smbios_old_sys_ver = true; 3349 } 3350 DEFINE_VIRT_MACHINE(2, 11) 3351 3352 static void virt_machine_2_10_options(MachineClass *mc) 3353 { 3354 virt_machine_2_11_options(mc); 3355 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3356 /* before 2.11 we never faulted accesses to bad addresses */ 3357 mc->ignore_memory_transaction_failures = true; 3358 } 3359 DEFINE_VIRT_MACHINE(2, 10) 3360 3361 static void virt_machine_2_9_options(MachineClass *mc) 3362 { 3363 virt_machine_2_10_options(mc); 3364 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3365 } 3366 DEFINE_VIRT_MACHINE(2, 9) 3367 3368 static void virt_machine_2_8_options(MachineClass *mc) 3369 { 3370 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3371 3372 virt_machine_2_9_options(mc); 3373 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3374 /* For 2.8 and earlier we falsely claimed in the DT that 3375 * our timers were edge-triggered, not level-triggered. 3376 */ 3377 vmc->claim_edge_triggered_timers = true; 3378 } 3379 DEFINE_VIRT_MACHINE(2, 8) 3380 3381 static void virt_machine_2_7_options(MachineClass *mc) 3382 { 3383 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3384 3385 virt_machine_2_8_options(mc); 3386 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3387 /* ITS was introduced with 2.8 */ 3388 vmc->no_its = true; 3389 /* Stick with 1K pages for migration compatibility */ 3390 mc->minimum_page_bits = 0; 3391 } 3392 DEFINE_VIRT_MACHINE(2, 7) 3393 3394 static void virt_machine_2_6_options(MachineClass *mc) 3395 { 3396 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3397 3398 virt_machine_2_7_options(mc); 3399 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3400 vmc->disallow_affinity_adjustment = true; 3401 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3402 vmc->no_pmu = true; 3403 } 3404 DEFINE_VIRT_MACHINE(2, 6) 3405