1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/boards.h" 39 #include "hw/arm/boot.h" 40 #include "hw/arm/primecell.h" 41 #include "hw/arm/virt.h" 42 #include "hw/block/flash.h" 43 #include "hw/vfio/vfio-calxeda-xgmac.h" 44 #include "hw/vfio/vfio-amd-xgbe.h" 45 #include "hw/display/ramfb.h" 46 #include "net/net.h" 47 #include "sysemu/device_tree.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "sysemu/tpm.h" 52 #include "sysemu/kvm.h" 53 #include "hw/loader.h" 54 #include "exec/address-spaces.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/arm/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/irq.h" 67 #include "kvm_arm.h" 68 #include "hw/firmware/smbios.h" 69 #include "qapi/visitor.h" 70 #include "qapi/qapi-visit-common.h" 71 #include "standard-headers/linux/input.h" 72 #include "hw/arm/smmuv3.h" 73 #include "hw/acpi/acpi.h" 74 #include "target/arm/internals.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-iommu.h" 79 #include "hw/char/pl011.h" 80 #include "qemu/guest-random.h" 81 82 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 83 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 84 void *data) \ 85 { \ 86 MachineClass *mc = MACHINE_CLASS(oc); \ 87 virt_machine_##major##_##minor##_options(mc); \ 88 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 89 if (latest) { \ 90 mc->alias = "virt"; \ 91 } \ 92 } \ 93 static const TypeInfo machvirt_##major##_##minor##_info = { \ 94 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 95 .parent = TYPE_VIRT_MACHINE, \ 96 .class_init = virt_##major##_##minor##_class_init, \ 97 }; \ 98 static void machvirt_machine_##major##_##minor##_init(void) \ 99 { \ 100 type_register_static(&machvirt_##major##_##minor##_info); \ 101 } \ 102 type_init(machvirt_machine_##major##_##minor##_init); 103 104 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 105 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 106 #define DEFINE_VIRT_MACHINE(major, minor) \ 107 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 108 109 110 /* Number of external interrupt lines to configure the GIC with */ 111 #define NUM_IRQS 256 112 113 #define PLATFORM_BUS_NUM_IRQS 64 114 115 /* Legacy RAM limit in GB (< version 4.0) */ 116 #define LEGACY_RAMLIMIT_GB 255 117 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 118 119 /* Addresses and sizes of our components. 120 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 121 * 128MB..256MB is used for miscellaneous device I/O. 122 * 256MB..1GB is reserved for possible future PCI support (ie where the 123 * PCI memory window will go if we add a PCI host controller). 124 * 1GB and up is RAM (which may happily spill over into the 125 * high memory region beyond 4GB). 126 * This represents a compromise between how much RAM can be given to 127 * a 32 bit VM and leaving space for expansion and in particular for PCI. 128 * Note that devices should generally be placed at multiples of 0x10000, 129 * to accommodate guests using 64K pages. 130 */ 131 static const MemMapEntry base_memmap[] = { 132 /* Space up to 0x8000000 is reserved for a boot ROM */ 133 [VIRT_FLASH] = { 0, 0x08000000 }, 134 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 135 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 136 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 137 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 138 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 139 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 140 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 141 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 142 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 143 /* This redistributor space allows up to 2*64kB*123 CPUs */ 144 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 145 [VIRT_UART] = { 0x09000000, 0x00001000 }, 146 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 147 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 148 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 149 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 150 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 151 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 152 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 153 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 154 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 155 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 156 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 157 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 158 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 159 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 160 /* Actual RAM size depends on initial RAM and device memory settings */ 161 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 162 }; 163 164 /* 165 * Highmem IO Regions: This memory map is floating, located after the RAM. 166 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 167 * top of the RAM, so that its base get the same alignment as the size, 168 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 169 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 170 * Note the extended_memmap is sized so that it eventually also includes the 171 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 172 * index of base_memmap). 173 */ 174 static MemMapEntry extended_memmap[] = { 175 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 176 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 177 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 178 /* Second PCIe window */ 179 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 180 }; 181 182 static const int a15irqmap[] = { 183 [VIRT_UART] = 1, 184 [VIRT_RTC] = 2, 185 [VIRT_PCIE] = 3, /* ... to 6 */ 186 [VIRT_GPIO] = 7, 187 [VIRT_SECURE_UART] = 8, 188 [VIRT_ACPI_GED] = 9, 189 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 190 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 191 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 192 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 193 }; 194 195 static const char *valid_cpus[] = { 196 ARM_CPU_TYPE_NAME("cortex-a7"), 197 ARM_CPU_TYPE_NAME("cortex-a15"), 198 ARM_CPU_TYPE_NAME("cortex-a53"), 199 ARM_CPU_TYPE_NAME("cortex-a57"), 200 ARM_CPU_TYPE_NAME("cortex-a72"), 201 ARM_CPU_TYPE_NAME("host"), 202 ARM_CPU_TYPE_NAME("max"), 203 }; 204 205 static bool cpu_type_valid(const char *cpu) 206 { 207 int i; 208 209 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 210 if (strcmp(cpu, valid_cpus[i]) == 0) { 211 return true; 212 } 213 } 214 return false; 215 } 216 217 static void create_kaslr_seed(VirtMachineState *vms, const char *node) 218 { 219 Error *err = NULL; 220 uint64_t seed; 221 222 if (qemu_guest_getrandom(&seed, sizeof(seed), &err)) { 223 error_free(err); 224 return; 225 } 226 qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed); 227 } 228 229 static void create_fdt(VirtMachineState *vms) 230 { 231 MachineState *ms = MACHINE(vms); 232 int nb_numa_nodes = ms->numa_state->num_nodes; 233 void *fdt = create_device_tree(&vms->fdt_size); 234 235 if (!fdt) { 236 error_report("create_device_tree() failed"); 237 exit(1); 238 } 239 240 vms->fdt = fdt; 241 242 /* Header */ 243 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 244 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 245 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 246 247 /* /chosen must exist for load_dtb to fill in necessary properties later */ 248 qemu_fdt_add_subnode(fdt, "/chosen"); 249 create_kaslr_seed(vms, "/chosen"); 250 251 if (vms->secure) { 252 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 253 create_kaslr_seed(vms, "/secure-chosen"); 254 } 255 256 /* Clock node, for the benefit of the UART. The kernel device tree 257 * binding documentation claims the PL011 node clock properties are 258 * optional but in practice if you omit them the kernel refuses to 259 * probe for the device. 260 */ 261 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 262 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 263 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 266 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 267 "clk24mhz"); 268 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 269 270 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 271 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 272 uint32_t *matrix = g_malloc0(size); 273 int idx, i, j; 274 275 for (i = 0; i < nb_numa_nodes; i++) { 276 for (j = 0; j < nb_numa_nodes; j++) { 277 idx = (i * nb_numa_nodes + j) * 3; 278 matrix[idx + 0] = cpu_to_be32(i); 279 matrix[idx + 1] = cpu_to_be32(j); 280 matrix[idx + 2] = 281 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 282 } 283 } 284 285 qemu_fdt_add_subnode(fdt, "/distance-map"); 286 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 287 "numa-distance-map-v1"); 288 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 289 matrix, size); 290 g_free(matrix); 291 } 292 } 293 294 static void fdt_add_timer_nodes(const VirtMachineState *vms) 295 { 296 /* On real hardware these interrupts are level-triggered. 297 * On KVM they were edge-triggered before host kernel version 4.4, 298 * and level-triggered afterwards. 299 * On emulated QEMU they are level-triggered. 300 * 301 * Getting the DTB info about them wrong is awkward for some 302 * guest kernels: 303 * pre-4.8 ignore the DT and leave the interrupt configured 304 * with whatever the GIC reset value (or the bootloader) left it at 305 * 4.8 before rc6 honour the incorrect data by programming it back 306 * into the GIC, causing problems 307 * 4.8rc6 and later ignore the DT and always write "level triggered" 308 * into the GIC 309 * 310 * For backwards-compatibility, virt-2.8 and earlier will continue 311 * to say these are edge-triggered, but later machines will report 312 * the correct information. 313 */ 314 ARMCPU *armcpu; 315 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 316 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 317 318 if (vmc->claim_edge_triggered_timers) { 319 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 320 } 321 322 if (vms->gic_version == VIRT_GIC_VERSION_2) { 323 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 324 GIC_FDT_IRQ_PPI_CPU_WIDTH, 325 (1 << vms->smp_cpus) - 1); 326 } 327 328 qemu_fdt_add_subnode(vms->fdt, "/timer"); 329 330 armcpu = ARM_CPU(qemu_get_cpu(0)); 331 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 332 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 333 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 334 compat, sizeof(compat)); 335 } else { 336 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 337 "arm,armv7-timer"); 338 } 339 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 340 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 341 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 342 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 343 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 345 } 346 347 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 348 { 349 int cpu; 350 int addr_cells = 1; 351 const MachineState *ms = MACHINE(vms); 352 353 /* 354 * From Documentation/devicetree/bindings/arm/cpus.txt 355 * On ARM v8 64-bit systems value should be set to 2, 356 * that corresponds to the MPIDR_EL1 register size. 357 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 358 * in the system, #address-cells can be set to 1, since 359 * MPIDR_EL1[63:32] bits are not used for CPUs 360 * identification. 361 * 362 * Here we actually don't know whether our system is 32- or 64-bit one. 363 * The simplest way to go is to examine affinity IDs of all our CPUs. If 364 * at least one of them has Aff3 populated, we set #address-cells to 2. 365 */ 366 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 367 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 368 369 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 370 addr_cells = 2; 371 break; 372 } 373 } 374 375 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 376 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 377 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 378 379 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 380 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 381 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 382 CPUState *cs = CPU(armcpu); 383 384 qemu_fdt_add_subnode(vms->fdt, nodename); 385 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 386 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 387 armcpu->dtb_compatible); 388 389 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 390 && vms->smp_cpus > 1) { 391 qemu_fdt_setprop_string(vms->fdt, nodename, 392 "enable-method", "psci"); 393 } 394 395 if (addr_cells == 2) { 396 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 397 armcpu->mp_affinity); 398 } else { 399 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 400 armcpu->mp_affinity); 401 } 402 403 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 404 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 405 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 406 } 407 408 g_free(nodename); 409 } 410 } 411 412 static void fdt_add_its_gic_node(VirtMachineState *vms) 413 { 414 char *nodename; 415 416 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 417 nodename = g_strdup_printf("/intc/its@%" PRIx64, 418 vms->memmap[VIRT_GIC_ITS].base); 419 qemu_fdt_add_subnode(vms->fdt, nodename); 420 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 421 "arm,gic-v3-its"); 422 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 423 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 424 2, vms->memmap[VIRT_GIC_ITS].base, 425 2, vms->memmap[VIRT_GIC_ITS].size); 426 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 427 g_free(nodename); 428 } 429 430 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 431 { 432 char *nodename; 433 434 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 435 vms->memmap[VIRT_GIC_V2M].base); 436 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 437 qemu_fdt_add_subnode(vms->fdt, nodename); 438 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 439 "arm,gic-v2m-frame"); 440 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 441 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 442 2, vms->memmap[VIRT_GIC_V2M].base, 443 2, vms->memmap[VIRT_GIC_V2M].size); 444 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 445 g_free(nodename); 446 } 447 448 static void fdt_add_gic_node(VirtMachineState *vms) 449 { 450 char *nodename; 451 452 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 453 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 454 455 nodename = g_strdup_printf("/intc@%" PRIx64, 456 vms->memmap[VIRT_GIC_DIST].base); 457 qemu_fdt_add_subnode(vms->fdt, nodename); 458 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 459 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 460 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 461 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 462 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 463 if (vms->gic_version == VIRT_GIC_VERSION_3) { 464 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 465 466 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 467 "arm,gic-v3"); 468 469 qemu_fdt_setprop_cell(vms->fdt, nodename, 470 "#redistributor-regions", nb_redist_regions); 471 472 if (nb_redist_regions == 1) { 473 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 474 2, vms->memmap[VIRT_GIC_DIST].base, 475 2, vms->memmap[VIRT_GIC_DIST].size, 476 2, vms->memmap[VIRT_GIC_REDIST].base, 477 2, vms->memmap[VIRT_GIC_REDIST].size); 478 } else { 479 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 480 2, vms->memmap[VIRT_GIC_DIST].base, 481 2, vms->memmap[VIRT_GIC_DIST].size, 482 2, vms->memmap[VIRT_GIC_REDIST].base, 483 2, vms->memmap[VIRT_GIC_REDIST].size, 484 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 485 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 486 } 487 488 if (vms->virt) { 489 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 490 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 491 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 492 } 493 } else { 494 /* 'cortex-a15-gic' means 'GIC v2' */ 495 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 496 "arm,cortex-a15-gic"); 497 if (!vms->virt) { 498 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 499 2, vms->memmap[VIRT_GIC_DIST].base, 500 2, vms->memmap[VIRT_GIC_DIST].size, 501 2, vms->memmap[VIRT_GIC_CPU].base, 502 2, vms->memmap[VIRT_GIC_CPU].size); 503 } else { 504 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 505 2, vms->memmap[VIRT_GIC_DIST].base, 506 2, vms->memmap[VIRT_GIC_DIST].size, 507 2, vms->memmap[VIRT_GIC_CPU].base, 508 2, vms->memmap[VIRT_GIC_CPU].size, 509 2, vms->memmap[VIRT_GIC_HYP].base, 510 2, vms->memmap[VIRT_GIC_HYP].size, 511 2, vms->memmap[VIRT_GIC_VCPU].base, 512 2, vms->memmap[VIRT_GIC_VCPU].size); 513 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 514 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 515 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 516 } 517 } 518 519 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 520 g_free(nodename); 521 } 522 523 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 524 { 525 CPUState *cpu; 526 ARMCPU *armcpu; 527 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 528 529 CPU_FOREACH(cpu) { 530 armcpu = ARM_CPU(cpu); 531 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 532 return; 533 } 534 if (kvm_enabled()) { 535 if (kvm_irqchip_in_kernel()) { 536 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 537 } 538 kvm_arm_pmu_init(cpu); 539 } 540 } 541 542 if (vms->gic_version == VIRT_GIC_VERSION_2) { 543 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 544 GIC_FDT_IRQ_PPI_CPU_WIDTH, 545 (1 << vms->smp_cpus) - 1); 546 } 547 548 armcpu = ARM_CPU(qemu_get_cpu(0)); 549 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 550 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 551 const char compat[] = "arm,armv8-pmuv3"; 552 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 553 compat, sizeof(compat)); 554 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 555 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 556 } 557 } 558 559 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 560 { 561 DeviceState *dev; 562 MachineState *ms = MACHINE(vms); 563 int irq = vms->irqmap[VIRT_ACPI_GED]; 564 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 565 566 if (ms->ram_slots) { 567 event |= ACPI_GED_MEM_HOTPLUG_EVT; 568 } 569 570 dev = qdev_create(NULL, TYPE_ACPI_GED); 571 qdev_prop_set_uint32(dev, "ged-event", event); 572 573 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 574 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 575 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 576 577 qdev_init_nofail(dev); 578 579 return dev; 580 } 581 582 static void create_its(VirtMachineState *vms) 583 { 584 const char *itsclass = its_class_name(); 585 DeviceState *dev; 586 587 if (!itsclass) { 588 /* Do nothing if not supported */ 589 return; 590 } 591 592 dev = qdev_create(NULL, itsclass); 593 594 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 595 &error_abort); 596 qdev_init_nofail(dev); 597 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 598 599 fdt_add_its_gic_node(vms); 600 } 601 602 static void create_v2m(VirtMachineState *vms) 603 { 604 int i; 605 int irq = vms->irqmap[VIRT_GIC_V2M]; 606 DeviceState *dev; 607 608 dev = qdev_create(NULL, "arm-gicv2m"); 609 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 610 qdev_prop_set_uint32(dev, "base-spi", irq); 611 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 612 qdev_init_nofail(dev); 613 614 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 615 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 616 qdev_get_gpio_in(vms->gic, irq + i)); 617 } 618 619 fdt_add_v2m_gic_node(vms); 620 } 621 622 static void create_gic(VirtMachineState *vms) 623 { 624 MachineState *ms = MACHINE(vms); 625 /* We create a standalone GIC */ 626 SysBusDevice *gicbusdev; 627 const char *gictype; 628 int type = vms->gic_version, i; 629 unsigned int smp_cpus = ms->smp.cpus; 630 uint32_t nb_redist_regions = 0; 631 632 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 633 634 vms->gic = qdev_create(NULL, gictype); 635 qdev_prop_set_uint32(vms->gic, "revision", type); 636 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 637 /* Note that the num-irq property counts both internal and external 638 * interrupts; there are always 32 of the former (mandated by GIC spec). 639 */ 640 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 641 if (!kvm_irqchip_in_kernel()) { 642 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 643 } 644 645 if (type == 3) { 646 uint32_t redist0_capacity = 647 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 648 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 649 650 nb_redist_regions = virt_gicv3_redist_region_count(vms); 651 652 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 653 nb_redist_regions); 654 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 655 656 if (nb_redist_regions == 2) { 657 uint32_t redist1_capacity = 658 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 659 660 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 661 MIN(smp_cpus - redist0_count, redist1_capacity)); 662 } 663 } else { 664 if (!kvm_irqchip_in_kernel()) { 665 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 666 vms->virt); 667 } 668 } 669 qdev_init_nofail(vms->gic); 670 gicbusdev = SYS_BUS_DEVICE(vms->gic); 671 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 672 if (type == 3) { 673 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 674 if (nb_redist_regions == 2) { 675 sysbus_mmio_map(gicbusdev, 2, 676 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 677 } 678 } else { 679 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 680 if (vms->virt) { 681 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 682 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 683 } 684 } 685 686 /* Wire the outputs from each CPU's generic timer and the GICv3 687 * maintenance interrupt signal to the appropriate GIC PPI inputs, 688 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 689 */ 690 for (i = 0; i < smp_cpus; i++) { 691 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 692 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 693 int irq; 694 /* Mapping from the output timer irq lines from the CPU to the 695 * GIC PPI inputs we use for the virt board. 696 */ 697 const int timer_irq[] = { 698 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 699 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 700 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 701 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 702 }; 703 704 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 705 qdev_connect_gpio_out(cpudev, irq, 706 qdev_get_gpio_in(vms->gic, 707 ppibase + timer_irq[irq])); 708 } 709 710 if (type == 3) { 711 qemu_irq irq = qdev_get_gpio_in(vms->gic, 712 ppibase + ARCH_GIC_MAINT_IRQ); 713 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 714 0, irq); 715 } else if (vms->virt) { 716 qemu_irq irq = qdev_get_gpio_in(vms->gic, 717 ppibase + ARCH_GIC_MAINT_IRQ); 718 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 719 } 720 721 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 722 qdev_get_gpio_in(vms->gic, ppibase 723 + VIRTUAL_PMU_IRQ)); 724 725 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 726 sysbus_connect_irq(gicbusdev, i + smp_cpus, 727 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 728 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 729 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 730 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 731 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 732 } 733 734 fdt_add_gic_node(vms); 735 736 if (type == 3 && vms->its) { 737 create_its(vms); 738 } else if (type == 2) { 739 create_v2m(vms); 740 } 741 } 742 743 static void create_uart(const VirtMachineState *vms, int uart, 744 MemoryRegion *mem, Chardev *chr) 745 { 746 char *nodename; 747 hwaddr base = vms->memmap[uart].base; 748 hwaddr size = vms->memmap[uart].size; 749 int irq = vms->irqmap[uart]; 750 const char compat[] = "arm,pl011\0arm,primecell"; 751 const char clocknames[] = "uartclk\0apb_pclk"; 752 DeviceState *dev = qdev_create(NULL, TYPE_PL011); 753 SysBusDevice *s = SYS_BUS_DEVICE(dev); 754 755 qdev_prop_set_chr(dev, "chardev", chr); 756 qdev_init_nofail(dev); 757 memory_region_add_subregion(mem, base, 758 sysbus_mmio_get_region(s, 0)); 759 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 760 761 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 762 qemu_fdt_add_subnode(vms->fdt, nodename); 763 /* Note that we can't use setprop_string because of the embedded NUL */ 764 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 765 compat, sizeof(compat)); 766 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 767 2, base, 2, size); 768 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 769 GIC_FDT_IRQ_TYPE_SPI, irq, 770 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 771 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 772 vms->clock_phandle, vms->clock_phandle); 773 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 774 clocknames, sizeof(clocknames)); 775 776 if (uart == VIRT_UART) { 777 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 778 } else { 779 /* Mark as not usable by the normal world */ 780 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 781 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 782 783 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 784 nodename); 785 } 786 787 g_free(nodename); 788 } 789 790 static void create_rtc(const VirtMachineState *vms) 791 { 792 char *nodename; 793 hwaddr base = vms->memmap[VIRT_RTC].base; 794 hwaddr size = vms->memmap[VIRT_RTC].size; 795 int irq = vms->irqmap[VIRT_RTC]; 796 const char compat[] = "arm,pl031\0arm,primecell"; 797 798 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 799 800 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 801 qemu_fdt_add_subnode(vms->fdt, nodename); 802 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 803 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 804 2, base, 2, size); 805 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 806 GIC_FDT_IRQ_TYPE_SPI, irq, 807 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 808 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 809 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 810 g_free(nodename); 811 } 812 813 static DeviceState *gpio_key_dev; 814 static void virt_powerdown_req(Notifier *n, void *opaque) 815 { 816 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 817 818 if (s->acpi_dev) { 819 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 820 } else { 821 /* use gpio Pin 3 for power button event */ 822 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 823 } 824 } 825 826 static void create_gpio(const VirtMachineState *vms) 827 { 828 char *nodename; 829 DeviceState *pl061_dev; 830 hwaddr base = vms->memmap[VIRT_GPIO].base; 831 hwaddr size = vms->memmap[VIRT_GPIO].size; 832 int irq = vms->irqmap[VIRT_GPIO]; 833 const char compat[] = "arm,pl061\0arm,primecell"; 834 835 pl061_dev = sysbus_create_simple("pl061", base, 836 qdev_get_gpio_in(vms->gic, irq)); 837 838 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 839 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 840 qemu_fdt_add_subnode(vms->fdt, nodename); 841 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 842 2, base, 2, size); 843 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 844 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 845 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 846 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 847 GIC_FDT_IRQ_TYPE_SPI, irq, 848 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 849 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 850 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 851 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 852 853 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 854 qdev_get_gpio_in(pl061_dev, 3)); 855 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 856 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 857 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 858 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 859 860 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 861 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 862 "label", "GPIO Key Poweroff"); 863 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 864 KEY_POWER); 865 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 866 "gpios", phandle, 3, 0); 867 g_free(nodename); 868 } 869 870 static void create_virtio_devices(const VirtMachineState *vms) 871 { 872 int i; 873 hwaddr size = vms->memmap[VIRT_MMIO].size; 874 875 /* We create the transports in forwards order. Since qbus_realize() 876 * prepends (not appends) new child buses, the incrementing loop below will 877 * create a list of virtio-mmio buses with decreasing base addresses. 878 * 879 * When a -device option is processed from the command line, 880 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 881 * order. The upshot is that -device options in increasing command line 882 * order are mapped to virtio-mmio buses with decreasing base addresses. 883 * 884 * When this code was originally written, that arrangement ensured that the 885 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 886 * the first -device on the command line. (The end-to-end order is a 887 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 888 * guest kernel's name-to-address assignment strategy.) 889 * 890 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 891 * the message, if not necessarily the code, of commit 70161ff336. 892 * Therefore the loop now establishes the inverse of the original intent. 893 * 894 * Unfortunately, we can't counteract the kernel change by reversing the 895 * loop; it would break existing command lines. 896 * 897 * In any case, the kernel makes no guarantee about the stability of 898 * enumeration order of virtio devices (as demonstrated by it changing 899 * between kernel versions). For reliable and stable identification 900 * of disks users must use UUIDs or similar mechanisms. 901 */ 902 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 903 int irq = vms->irqmap[VIRT_MMIO] + i; 904 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 905 906 sysbus_create_simple("virtio-mmio", base, 907 qdev_get_gpio_in(vms->gic, irq)); 908 } 909 910 /* We add dtb nodes in reverse order so that they appear in the finished 911 * device tree lowest address first. 912 * 913 * Note that this mapping is independent of the loop above. The previous 914 * loop influences virtio device to virtio transport assignment, whereas 915 * this loop controls how virtio transports are laid out in the dtb. 916 */ 917 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 918 char *nodename; 919 int irq = vms->irqmap[VIRT_MMIO] + i; 920 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 921 922 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 923 qemu_fdt_add_subnode(vms->fdt, nodename); 924 qemu_fdt_setprop_string(vms->fdt, nodename, 925 "compatible", "virtio,mmio"); 926 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 927 2, base, 2, size); 928 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 929 GIC_FDT_IRQ_TYPE_SPI, irq, 930 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 931 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 932 g_free(nodename); 933 } 934 } 935 936 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 937 938 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 939 const char *name, 940 const char *alias_prop_name) 941 { 942 /* 943 * Create a single flash device. We use the same parameters as 944 * the flash devices on the Versatile Express board. 945 */ 946 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 947 948 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 949 qdev_prop_set_uint8(dev, "width", 4); 950 qdev_prop_set_uint8(dev, "device-width", 2); 951 qdev_prop_set_bit(dev, "big-endian", false); 952 qdev_prop_set_uint16(dev, "id0", 0x89); 953 qdev_prop_set_uint16(dev, "id1", 0x18); 954 qdev_prop_set_uint16(dev, "id2", 0x00); 955 qdev_prop_set_uint16(dev, "id3", 0x00); 956 qdev_prop_set_string(dev, "name", name); 957 object_property_add_child(OBJECT(vms), name, OBJECT(dev), 958 &error_abort); 959 object_property_add_alias(OBJECT(vms), alias_prop_name, 960 OBJECT(dev), "drive", &error_abort); 961 return PFLASH_CFI01(dev); 962 } 963 964 static void virt_flash_create(VirtMachineState *vms) 965 { 966 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 967 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 968 } 969 970 static void virt_flash_map1(PFlashCFI01 *flash, 971 hwaddr base, hwaddr size, 972 MemoryRegion *sysmem) 973 { 974 DeviceState *dev = DEVICE(flash); 975 976 assert(size % VIRT_FLASH_SECTOR_SIZE == 0); 977 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 978 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 979 qdev_init_nofail(dev); 980 981 memory_region_add_subregion(sysmem, base, 982 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 983 0)); 984 } 985 986 static void virt_flash_map(VirtMachineState *vms, 987 MemoryRegion *sysmem, 988 MemoryRegion *secure_sysmem) 989 { 990 /* 991 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 992 * sysmem is the system memory space. secure_sysmem is the secure view 993 * of the system, and the first flash device should be made visible only 994 * there. The second flash device is visible to both secure and nonsecure. 995 * If sysmem == secure_sysmem this means there is no separate Secure 996 * address space and both flash devices are generally visible. 997 */ 998 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 999 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1000 1001 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1002 secure_sysmem); 1003 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1004 sysmem); 1005 } 1006 1007 static void virt_flash_fdt(VirtMachineState *vms, 1008 MemoryRegion *sysmem, 1009 MemoryRegion *secure_sysmem) 1010 { 1011 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1012 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1013 char *nodename; 1014 1015 if (sysmem == secure_sysmem) { 1016 /* Report both flash devices as a single node in the DT */ 1017 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1018 qemu_fdt_add_subnode(vms->fdt, nodename); 1019 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1020 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1021 2, flashbase, 2, flashsize, 1022 2, flashbase + flashsize, 2, flashsize); 1023 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1024 g_free(nodename); 1025 } else { 1026 /* 1027 * Report the devices as separate nodes so we can mark one as 1028 * only visible to the secure world. 1029 */ 1030 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1031 qemu_fdt_add_subnode(vms->fdt, nodename); 1032 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1033 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1034 2, flashbase, 2, flashsize); 1035 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1036 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1037 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1038 g_free(nodename); 1039 1040 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1041 qemu_fdt_add_subnode(vms->fdt, nodename); 1042 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1043 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1044 2, flashbase + flashsize, 2, flashsize); 1045 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1046 g_free(nodename); 1047 } 1048 } 1049 1050 static bool virt_firmware_init(VirtMachineState *vms, 1051 MemoryRegion *sysmem, 1052 MemoryRegion *secure_sysmem) 1053 { 1054 int i; 1055 BlockBackend *pflash_blk0; 1056 1057 /* Map legacy -drive if=pflash to machine properties */ 1058 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1059 pflash_cfi01_legacy_drive(vms->flash[i], 1060 drive_get(IF_PFLASH, 0, i)); 1061 } 1062 1063 virt_flash_map(vms, sysmem, secure_sysmem); 1064 1065 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1066 1067 if (bios_name) { 1068 char *fname; 1069 MemoryRegion *mr; 1070 int image_size; 1071 1072 if (pflash_blk0) { 1073 error_report("The contents of the first flash device may be " 1074 "specified with -bios or with -drive if=pflash... " 1075 "but you cannot use both options at once"); 1076 exit(1); 1077 } 1078 1079 /* Fall back to -bios */ 1080 1081 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1082 if (!fname) { 1083 error_report("Could not find ROM image '%s'", bios_name); 1084 exit(1); 1085 } 1086 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1087 image_size = load_image_mr(fname, mr); 1088 g_free(fname); 1089 if (image_size < 0) { 1090 error_report("Could not load ROM image '%s'", bios_name); 1091 exit(1); 1092 } 1093 } 1094 1095 return pflash_blk0 || bios_name; 1096 } 1097 1098 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1099 { 1100 MachineState *ms = MACHINE(vms); 1101 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1102 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1103 FWCfgState *fw_cfg; 1104 char *nodename; 1105 1106 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1107 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1108 1109 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1110 qemu_fdt_add_subnode(vms->fdt, nodename); 1111 qemu_fdt_setprop_string(vms->fdt, nodename, 1112 "compatible", "qemu,fw-cfg-mmio"); 1113 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1114 2, base, 2, size); 1115 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1116 g_free(nodename); 1117 return fw_cfg; 1118 } 1119 1120 static void create_pcie_irq_map(const VirtMachineState *vms, 1121 uint32_t gic_phandle, 1122 int first_irq, const char *nodename) 1123 { 1124 int devfn, pin; 1125 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1126 uint32_t *irq_map = full_irq_map; 1127 1128 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1129 for (pin = 0; pin < 4; pin++) { 1130 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1131 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1132 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1133 int i; 1134 1135 uint32_t map[] = { 1136 devfn << 8, 0, 0, /* devfn */ 1137 pin + 1, /* PCI pin */ 1138 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1139 1140 /* Convert map to big endian */ 1141 for (i = 0; i < 10; i++) { 1142 irq_map[i] = cpu_to_be32(map[i]); 1143 } 1144 irq_map += 10; 1145 } 1146 } 1147 1148 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1149 full_irq_map, sizeof(full_irq_map)); 1150 1151 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1152 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1153 0x7 /* PCI irq */); 1154 } 1155 1156 static void create_smmu(const VirtMachineState *vms, 1157 PCIBus *bus) 1158 { 1159 char *node; 1160 const char compat[] = "arm,smmu-v3"; 1161 int irq = vms->irqmap[VIRT_SMMU]; 1162 int i; 1163 hwaddr base = vms->memmap[VIRT_SMMU].base; 1164 hwaddr size = vms->memmap[VIRT_SMMU].size; 1165 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1166 DeviceState *dev; 1167 1168 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1169 return; 1170 } 1171 1172 dev = qdev_create(NULL, "arm-smmuv3"); 1173 1174 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1175 &error_abort); 1176 qdev_init_nofail(dev); 1177 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1178 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1179 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1180 qdev_get_gpio_in(vms->gic, irq + i)); 1181 } 1182 1183 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1184 qemu_fdt_add_subnode(vms->fdt, node); 1185 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1186 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1187 1188 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1189 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1190 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1191 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1192 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1193 1194 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1195 sizeof(irq_names)); 1196 1197 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1198 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1199 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1200 1201 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1202 1203 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1204 g_free(node); 1205 } 1206 1207 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1208 { 1209 const char compat[] = "virtio,pci-iommu"; 1210 uint16_t bdf = vms->virtio_iommu_bdf; 1211 char *node; 1212 1213 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1214 1215 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1216 qemu_fdt_add_subnode(vms->fdt, node); 1217 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1218 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 1219 1, bdf << 8, 1, 0, 1, 0, 1220 1, 0, 1, 0); 1221 1222 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1223 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1224 g_free(node); 1225 1226 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map", 1227 0x0, vms->iommu_phandle, 0x0, bdf, 1228 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1229 } 1230 1231 static void create_pcie(VirtMachineState *vms) 1232 { 1233 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1234 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1235 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1236 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1237 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1238 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1239 hwaddr base_ecam, size_ecam; 1240 hwaddr base = base_mmio; 1241 int nr_pcie_buses; 1242 int irq = vms->irqmap[VIRT_PCIE]; 1243 MemoryRegion *mmio_alias; 1244 MemoryRegion *mmio_reg; 1245 MemoryRegion *ecam_alias; 1246 MemoryRegion *ecam_reg; 1247 DeviceState *dev; 1248 char *nodename; 1249 int i, ecam_id; 1250 PCIHostState *pci; 1251 1252 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1253 qdev_init_nofail(dev); 1254 1255 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1256 base_ecam = vms->memmap[ecam_id].base; 1257 size_ecam = vms->memmap[ecam_id].size; 1258 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1259 /* Map only the first size_ecam bytes of ECAM space */ 1260 ecam_alias = g_new0(MemoryRegion, 1); 1261 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1262 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1263 ecam_reg, 0, size_ecam); 1264 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1265 1266 /* Map the MMIO window into system address space so as to expose 1267 * the section of PCI MMIO space which starts at the same base address 1268 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1269 * the window). 1270 */ 1271 mmio_alias = g_new0(MemoryRegion, 1); 1272 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1273 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1274 mmio_reg, base_mmio, size_mmio); 1275 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1276 1277 if (vms->highmem) { 1278 /* Map high MMIO space */ 1279 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1280 1281 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1282 mmio_reg, base_mmio_high, size_mmio_high); 1283 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1284 high_mmio_alias); 1285 } 1286 1287 /* Map IO port space */ 1288 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1289 1290 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1291 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1292 qdev_get_gpio_in(vms->gic, irq + i)); 1293 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1294 } 1295 1296 pci = PCI_HOST_BRIDGE(dev); 1297 if (pci->bus) { 1298 for (i = 0; i < nb_nics; i++) { 1299 NICInfo *nd = &nd_table[i]; 1300 1301 if (!nd->model) { 1302 nd->model = g_strdup("virtio"); 1303 } 1304 1305 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1306 } 1307 } 1308 1309 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1310 qemu_fdt_add_subnode(vms->fdt, nodename); 1311 qemu_fdt_setprop_string(vms->fdt, nodename, 1312 "compatible", "pci-host-ecam-generic"); 1313 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1314 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1315 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1316 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1317 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1318 nr_pcie_buses - 1); 1319 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1320 1321 if (vms->msi_phandle) { 1322 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1323 vms->msi_phandle); 1324 } 1325 1326 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1327 2, base_ecam, 2, size_ecam); 1328 1329 if (vms->highmem) { 1330 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1331 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1332 2, base_pio, 2, size_pio, 1333 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1334 2, base_mmio, 2, size_mmio, 1335 1, FDT_PCI_RANGE_MMIO_64BIT, 1336 2, base_mmio_high, 1337 2, base_mmio_high, 2, size_mmio_high); 1338 } else { 1339 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1340 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1341 2, base_pio, 2, size_pio, 1342 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1343 2, base_mmio, 2, size_mmio); 1344 } 1345 1346 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1347 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1348 1349 if (vms->iommu) { 1350 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1351 1352 switch (vms->iommu) { 1353 case VIRT_IOMMU_SMMUV3: 1354 create_smmu(vms, pci->bus); 1355 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1356 0x0, vms->iommu_phandle, 0x0, 0x10000); 1357 break; 1358 default: 1359 g_assert_not_reached(); 1360 } 1361 } 1362 } 1363 1364 static void create_platform_bus(VirtMachineState *vms) 1365 { 1366 DeviceState *dev; 1367 SysBusDevice *s; 1368 int i; 1369 MemoryRegion *sysmem = get_system_memory(); 1370 1371 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1372 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1373 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1374 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1375 qdev_init_nofail(dev); 1376 vms->platform_bus_dev = dev; 1377 1378 s = SYS_BUS_DEVICE(dev); 1379 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1380 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1381 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1382 } 1383 1384 memory_region_add_subregion(sysmem, 1385 vms->memmap[VIRT_PLATFORM_BUS].base, 1386 sysbus_mmio_get_region(s, 0)); 1387 } 1388 1389 static void create_secure_ram(VirtMachineState *vms, 1390 MemoryRegion *secure_sysmem) 1391 { 1392 MemoryRegion *secram = g_new(MemoryRegion, 1); 1393 char *nodename; 1394 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1395 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1396 1397 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1398 &error_fatal); 1399 memory_region_add_subregion(secure_sysmem, base, secram); 1400 1401 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1402 qemu_fdt_add_subnode(vms->fdt, nodename); 1403 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1404 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1405 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1406 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1407 1408 g_free(nodename); 1409 } 1410 1411 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1412 { 1413 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1414 bootinfo); 1415 1416 *fdt_size = board->fdt_size; 1417 return board->fdt; 1418 } 1419 1420 static void virt_build_smbios(VirtMachineState *vms) 1421 { 1422 MachineClass *mc = MACHINE_GET_CLASS(vms); 1423 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1424 uint8_t *smbios_tables, *smbios_anchor; 1425 size_t smbios_tables_len, smbios_anchor_len; 1426 const char *product = "QEMU Virtual Machine"; 1427 1428 if (kvm_enabled()) { 1429 product = "KVM Virtual Machine"; 1430 } 1431 1432 smbios_set_defaults("QEMU", product, 1433 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1434 true, SMBIOS_ENTRY_POINT_30); 1435 1436 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, 1437 &smbios_anchor, &smbios_anchor_len); 1438 1439 if (smbios_anchor) { 1440 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1441 smbios_tables, smbios_tables_len); 1442 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1443 smbios_anchor, smbios_anchor_len); 1444 } 1445 } 1446 1447 static 1448 void virt_machine_done(Notifier *notifier, void *data) 1449 { 1450 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1451 machine_done); 1452 MachineState *ms = MACHINE(vms); 1453 ARMCPU *cpu = ARM_CPU(first_cpu); 1454 struct arm_boot_info *info = &vms->bootinfo; 1455 AddressSpace *as = arm_boot_address_space(cpu, info); 1456 1457 /* 1458 * If the user provided a dtb, we assume the dynamic sysbus nodes 1459 * already are integrated there. This corresponds to a use case where 1460 * the dynamic sysbus nodes are complex and their generation is not yet 1461 * supported. In that case the user can take charge of the guest dt 1462 * while qemu takes charge of the qom stuff. 1463 */ 1464 if (info->dtb_filename == NULL) { 1465 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1466 vms->memmap[VIRT_PLATFORM_BUS].base, 1467 vms->memmap[VIRT_PLATFORM_BUS].size, 1468 vms->irqmap[VIRT_PLATFORM_BUS]); 1469 } 1470 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1471 exit(1); 1472 } 1473 1474 virt_acpi_setup(vms); 1475 virt_build_smbios(vms); 1476 } 1477 1478 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1479 { 1480 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1481 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1482 1483 if (!vmc->disallow_affinity_adjustment) { 1484 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1485 * GIC's target-list limitations. 32-bit KVM hosts currently 1486 * always create clusters of 4 CPUs, but that is expected to 1487 * change when they gain support for gicv3. When KVM is enabled 1488 * it will override the changes we make here, therefore our 1489 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1490 * and to improve SGI efficiency. 1491 */ 1492 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1493 clustersz = GICV3_TARGETLIST_BITS; 1494 } else { 1495 clustersz = GIC_TARGETLIST_BITS; 1496 } 1497 } 1498 return arm_cpu_mp_affinity(idx, clustersz); 1499 } 1500 1501 static void virt_set_memmap(VirtMachineState *vms) 1502 { 1503 MachineState *ms = MACHINE(vms); 1504 hwaddr base, device_memory_base, device_memory_size; 1505 int i; 1506 1507 vms->memmap = extended_memmap; 1508 1509 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1510 vms->memmap[i] = base_memmap[i]; 1511 } 1512 1513 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1514 error_report("unsupported number of memory slots: %"PRIu64, 1515 ms->ram_slots); 1516 exit(EXIT_FAILURE); 1517 } 1518 1519 /* 1520 * We compute the base of the high IO region depending on the 1521 * amount of initial and device memory. The device memory start/size 1522 * is aligned on 1GiB. We never put the high IO region below 256GiB 1523 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1524 * The device region size assumes 1GiB page max alignment per slot. 1525 */ 1526 device_memory_base = 1527 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1528 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1529 1530 /* Base address of the high IO region */ 1531 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1532 if (base < device_memory_base) { 1533 error_report("maxmem/slots too huge"); 1534 exit(EXIT_FAILURE); 1535 } 1536 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1537 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1538 } 1539 1540 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1541 hwaddr size = extended_memmap[i].size; 1542 1543 base = ROUND_UP(base, size); 1544 vms->memmap[i].base = base; 1545 vms->memmap[i].size = size; 1546 base += size; 1547 } 1548 vms->highest_gpa = base - 1; 1549 if (device_memory_size > 0) { 1550 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1551 ms->device_memory->base = device_memory_base; 1552 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1553 "device-memory", device_memory_size); 1554 } 1555 } 1556 1557 /* 1558 * finalize_gic_version - Determines the final gic_version 1559 * according to the gic-version property 1560 * 1561 * Default GIC type is v2 1562 */ 1563 static void finalize_gic_version(VirtMachineState *vms) 1564 { 1565 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1566 1567 if (kvm_enabled()) { 1568 int probe_bitmap; 1569 1570 if (!kvm_irqchip_in_kernel()) { 1571 switch (vms->gic_version) { 1572 case VIRT_GIC_VERSION_HOST: 1573 warn_report( 1574 "gic-version=host not relevant with kernel-irqchip=off " 1575 "as only userspace GICv2 is supported. Using v2 ..."); 1576 return; 1577 case VIRT_GIC_VERSION_MAX: 1578 case VIRT_GIC_VERSION_NOSEL: 1579 vms->gic_version = VIRT_GIC_VERSION_2; 1580 return; 1581 case VIRT_GIC_VERSION_2: 1582 return; 1583 case VIRT_GIC_VERSION_3: 1584 error_report( 1585 "gic-version=3 is not supported with kernel-irqchip=off"); 1586 exit(1); 1587 } 1588 } 1589 1590 probe_bitmap = kvm_arm_vgic_probe(); 1591 if (!probe_bitmap) { 1592 error_report("Unable to determine GIC version supported by host"); 1593 exit(1); 1594 } 1595 1596 switch (vms->gic_version) { 1597 case VIRT_GIC_VERSION_HOST: 1598 case VIRT_GIC_VERSION_MAX: 1599 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1600 vms->gic_version = VIRT_GIC_VERSION_3; 1601 } else { 1602 vms->gic_version = VIRT_GIC_VERSION_2; 1603 } 1604 return; 1605 case VIRT_GIC_VERSION_NOSEL: 1606 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1607 vms->gic_version = VIRT_GIC_VERSION_2; 1608 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1609 /* 1610 * in case the host does not support v2 in-kernel emulation or 1611 * the end-user requested more than 8 VCPUs we now default 1612 * to v3. In any case defaulting to v2 would be broken. 1613 */ 1614 vms->gic_version = VIRT_GIC_VERSION_3; 1615 } else if (max_cpus > GIC_NCPU) { 1616 error_report("host only supports in-kernel GICv2 emulation " 1617 "but more than 8 vcpus are requested"); 1618 exit(1); 1619 } 1620 break; 1621 case VIRT_GIC_VERSION_2: 1622 case VIRT_GIC_VERSION_3: 1623 break; 1624 } 1625 1626 /* Check chosen version is effectively supported by the host */ 1627 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1628 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1629 error_report("host does not support in-kernel GICv2 emulation"); 1630 exit(1); 1631 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1632 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1633 error_report("host does not support in-kernel GICv3 emulation"); 1634 exit(1); 1635 } 1636 return; 1637 } 1638 1639 /* TCG mode */ 1640 switch (vms->gic_version) { 1641 case VIRT_GIC_VERSION_NOSEL: 1642 vms->gic_version = VIRT_GIC_VERSION_2; 1643 break; 1644 case VIRT_GIC_VERSION_MAX: 1645 vms->gic_version = VIRT_GIC_VERSION_3; 1646 break; 1647 case VIRT_GIC_VERSION_HOST: 1648 error_report("gic-version=host requires KVM"); 1649 exit(1); 1650 case VIRT_GIC_VERSION_2: 1651 case VIRT_GIC_VERSION_3: 1652 break; 1653 } 1654 } 1655 1656 static void machvirt_init(MachineState *machine) 1657 { 1658 VirtMachineState *vms = VIRT_MACHINE(machine); 1659 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1660 MachineClass *mc = MACHINE_GET_CLASS(machine); 1661 const CPUArchIdList *possible_cpus; 1662 MemoryRegion *sysmem = get_system_memory(); 1663 MemoryRegion *secure_sysmem = NULL; 1664 int n, virt_max_cpus; 1665 bool firmware_loaded; 1666 bool aarch64 = true; 1667 bool has_ged = !vmc->no_ged; 1668 unsigned int smp_cpus = machine->smp.cpus; 1669 unsigned int max_cpus = machine->smp.max_cpus; 1670 1671 /* 1672 * In accelerated mode, the memory map is computed earlier in kvm_type() 1673 * to create a VM with the right number of IPA bits. 1674 */ 1675 if (!vms->memmap) { 1676 virt_set_memmap(vms); 1677 } 1678 1679 /* We can probe only here because during property set 1680 * KVM is not available yet 1681 */ 1682 finalize_gic_version(vms); 1683 1684 if (!cpu_type_valid(machine->cpu_type)) { 1685 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1686 exit(1); 1687 } 1688 1689 if (vms->secure) { 1690 if (kvm_enabled()) { 1691 error_report("mach-virt: KVM does not support Security extensions"); 1692 exit(1); 1693 } 1694 1695 /* 1696 * The Secure view of the world is the same as the NonSecure, 1697 * but with a few extra devices. Create it as a container region 1698 * containing the system memory at low priority; any secure-only 1699 * devices go in at higher priority and take precedence. 1700 */ 1701 secure_sysmem = g_new(MemoryRegion, 1); 1702 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1703 UINT64_MAX); 1704 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1705 } 1706 1707 firmware_loaded = virt_firmware_init(vms, sysmem, 1708 secure_sysmem ?: sysmem); 1709 1710 /* If we have an EL3 boot ROM then the assumption is that it will 1711 * implement PSCI itself, so disable QEMU's internal implementation 1712 * so it doesn't get in the way. Instead of starting secondary 1713 * CPUs in PSCI powerdown state we will start them all running and 1714 * let the boot ROM sort them out. 1715 * The usual case is that we do use QEMU's PSCI implementation; 1716 * if the guest has EL2 then we will use SMC as the conduit, 1717 * and otherwise we will use HVC (for backwards compatibility and 1718 * because if we're using KVM then we must use HVC). 1719 */ 1720 if (vms->secure && firmware_loaded) { 1721 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1722 } else if (vms->virt) { 1723 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1724 } else { 1725 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1726 } 1727 1728 /* The maximum number of CPUs depends on the GIC version, or on how 1729 * many redistributors we can fit into the memory map. 1730 */ 1731 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1732 virt_max_cpus = 1733 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1734 virt_max_cpus += 1735 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1736 } else { 1737 virt_max_cpus = GIC_NCPU; 1738 } 1739 1740 if (max_cpus > virt_max_cpus) { 1741 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1742 "supported by machine 'mach-virt' (%d)", 1743 max_cpus, virt_max_cpus); 1744 exit(1); 1745 } 1746 1747 vms->smp_cpus = smp_cpus; 1748 1749 if (vms->virt && kvm_enabled()) { 1750 error_report("mach-virt: KVM does not support providing " 1751 "Virtualization extensions to the guest CPU"); 1752 exit(1); 1753 } 1754 1755 create_fdt(vms); 1756 1757 possible_cpus = mc->possible_cpu_arch_ids(machine); 1758 for (n = 0; n < possible_cpus->len; n++) { 1759 Object *cpuobj; 1760 CPUState *cs; 1761 1762 if (n >= smp_cpus) { 1763 break; 1764 } 1765 1766 cpuobj = object_new(possible_cpus->cpus[n].type); 1767 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1768 "mp-affinity", NULL); 1769 1770 cs = CPU(cpuobj); 1771 cs->cpu_index = n; 1772 1773 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1774 &error_fatal); 1775 1776 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1777 1778 if (!vms->secure) { 1779 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1780 } 1781 1782 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1783 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1784 } 1785 1786 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1787 object_property_set_int(cpuobj, vms->psci_conduit, 1788 "psci-conduit", NULL); 1789 1790 /* Secondary CPUs start in PSCI powered-down state */ 1791 if (n > 0) { 1792 object_property_set_bool(cpuobj, true, 1793 "start-powered-off", NULL); 1794 } 1795 } 1796 1797 if (vmc->kvm_no_adjvtime && 1798 object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { 1799 object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); 1800 } 1801 1802 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1803 object_property_set_bool(cpuobj, false, "pmu", NULL); 1804 } 1805 1806 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1807 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1808 "reset-cbar", &error_abort); 1809 } 1810 1811 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1812 &error_abort); 1813 if (vms->secure) { 1814 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1815 "secure-memory", &error_abort); 1816 } 1817 1818 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1819 object_unref(cpuobj); 1820 } 1821 fdt_add_timer_nodes(vms); 1822 fdt_add_cpu_nodes(vms); 1823 1824 if (!kvm_enabled()) { 1825 ARMCPU *cpu = ARM_CPU(first_cpu); 1826 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1827 1828 if (aarch64 && vms->highmem) { 1829 int requested_pa_size, pamax = arm_pamax(cpu); 1830 1831 requested_pa_size = 64 - clz64(vms->highest_gpa); 1832 if (pamax < requested_pa_size) { 1833 error_report("VCPU supports less PA bits (%d) than requested " 1834 "by the memory map (%d)", pamax, requested_pa_size); 1835 exit(1); 1836 } 1837 } 1838 } 1839 1840 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 1841 machine->ram); 1842 if (machine->device_memory) { 1843 memory_region_add_subregion(sysmem, machine->device_memory->base, 1844 &machine->device_memory->mr); 1845 } 1846 1847 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 1848 1849 create_gic(vms); 1850 1851 fdt_add_pmu_nodes(vms); 1852 1853 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 1854 1855 if (vms->secure) { 1856 create_secure_ram(vms, secure_sysmem); 1857 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1858 } 1859 1860 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1861 1862 create_rtc(vms); 1863 1864 create_pcie(vms); 1865 1866 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 1867 vms->acpi_dev = create_acpi_ged(vms); 1868 } else { 1869 create_gpio(vms); 1870 } 1871 1872 /* connect powerdown request */ 1873 vms->powerdown_notifier.notify = virt_powerdown_req; 1874 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 1875 1876 /* Create mmio transports, so the user can create virtio backends 1877 * (which will be automatically plugged in to the transports). If 1878 * no backend is created the transport will just sit harmlessly idle. 1879 */ 1880 create_virtio_devices(vms); 1881 1882 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1883 rom_set_fw(vms->fw_cfg); 1884 1885 create_platform_bus(vms); 1886 1887 vms->bootinfo.ram_size = machine->ram_size; 1888 vms->bootinfo.nb_cpus = smp_cpus; 1889 vms->bootinfo.board_id = -1; 1890 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1891 vms->bootinfo.get_dtb = machvirt_dtb; 1892 vms->bootinfo.skip_dtb_autoload = true; 1893 vms->bootinfo.firmware_loaded = firmware_loaded; 1894 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 1895 1896 vms->machine_done.notify = virt_machine_done; 1897 qemu_add_machine_init_done_notifier(&vms->machine_done); 1898 } 1899 1900 static bool virt_get_secure(Object *obj, Error **errp) 1901 { 1902 VirtMachineState *vms = VIRT_MACHINE(obj); 1903 1904 return vms->secure; 1905 } 1906 1907 static void virt_set_secure(Object *obj, bool value, Error **errp) 1908 { 1909 VirtMachineState *vms = VIRT_MACHINE(obj); 1910 1911 vms->secure = value; 1912 } 1913 1914 static bool virt_get_virt(Object *obj, Error **errp) 1915 { 1916 VirtMachineState *vms = VIRT_MACHINE(obj); 1917 1918 return vms->virt; 1919 } 1920 1921 static void virt_set_virt(Object *obj, bool value, Error **errp) 1922 { 1923 VirtMachineState *vms = VIRT_MACHINE(obj); 1924 1925 vms->virt = value; 1926 } 1927 1928 static bool virt_get_highmem(Object *obj, Error **errp) 1929 { 1930 VirtMachineState *vms = VIRT_MACHINE(obj); 1931 1932 return vms->highmem; 1933 } 1934 1935 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1936 { 1937 VirtMachineState *vms = VIRT_MACHINE(obj); 1938 1939 vms->highmem = value; 1940 } 1941 1942 static bool virt_get_its(Object *obj, Error **errp) 1943 { 1944 VirtMachineState *vms = VIRT_MACHINE(obj); 1945 1946 return vms->its; 1947 } 1948 1949 static void virt_set_its(Object *obj, bool value, Error **errp) 1950 { 1951 VirtMachineState *vms = VIRT_MACHINE(obj); 1952 1953 vms->its = value; 1954 } 1955 1956 bool virt_is_acpi_enabled(VirtMachineState *vms) 1957 { 1958 if (vms->acpi == ON_OFF_AUTO_OFF) { 1959 return false; 1960 } 1961 return true; 1962 } 1963 1964 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1965 void *opaque, Error **errp) 1966 { 1967 VirtMachineState *vms = VIRT_MACHINE(obj); 1968 OnOffAuto acpi = vms->acpi; 1969 1970 visit_type_OnOffAuto(v, name, &acpi, errp); 1971 } 1972 1973 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1974 void *opaque, Error **errp) 1975 { 1976 VirtMachineState *vms = VIRT_MACHINE(obj); 1977 1978 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 1979 } 1980 1981 static char *virt_get_gic_version(Object *obj, Error **errp) 1982 { 1983 VirtMachineState *vms = VIRT_MACHINE(obj); 1984 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; 1985 1986 return g_strdup(val); 1987 } 1988 1989 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1990 { 1991 VirtMachineState *vms = VIRT_MACHINE(obj); 1992 1993 if (!strcmp(value, "3")) { 1994 vms->gic_version = VIRT_GIC_VERSION_3; 1995 } else if (!strcmp(value, "2")) { 1996 vms->gic_version = VIRT_GIC_VERSION_2; 1997 } else if (!strcmp(value, "host")) { 1998 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 1999 } else if (!strcmp(value, "max")) { 2000 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2001 } else { 2002 error_setg(errp, "Invalid gic-version value"); 2003 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2004 } 2005 } 2006 2007 static char *virt_get_iommu(Object *obj, Error **errp) 2008 { 2009 VirtMachineState *vms = VIRT_MACHINE(obj); 2010 2011 switch (vms->iommu) { 2012 case VIRT_IOMMU_NONE: 2013 return g_strdup("none"); 2014 case VIRT_IOMMU_SMMUV3: 2015 return g_strdup("smmuv3"); 2016 default: 2017 g_assert_not_reached(); 2018 } 2019 } 2020 2021 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2022 { 2023 VirtMachineState *vms = VIRT_MACHINE(obj); 2024 2025 if (!strcmp(value, "smmuv3")) { 2026 vms->iommu = VIRT_IOMMU_SMMUV3; 2027 } else if (!strcmp(value, "none")) { 2028 vms->iommu = VIRT_IOMMU_NONE; 2029 } else { 2030 error_setg(errp, "Invalid iommu value"); 2031 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2032 } 2033 } 2034 2035 static CpuInstanceProperties 2036 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2037 { 2038 MachineClass *mc = MACHINE_GET_CLASS(ms); 2039 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2040 2041 assert(cpu_index < possible_cpus->len); 2042 return possible_cpus->cpus[cpu_index].props; 2043 } 2044 2045 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2046 { 2047 return idx % ms->numa_state->num_nodes; 2048 } 2049 2050 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2051 { 2052 int n; 2053 unsigned int max_cpus = ms->smp.max_cpus; 2054 VirtMachineState *vms = VIRT_MACHINE(ms); 2055 2056 if (ms->possible_cpus) { 2057 assert(ms->possible_cpus->len == max_cpus); 2058 return ms->possible_cpus; 2059 } 2060 2061 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2062 sizeof(CPUArchId) * max_cpus); 2063 ms->possible_cpus->len = max_cpus; 2064 for (n = 0; n < ms->possible_cpus->len; n++) { 2065 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2066 ms->possible_cpus->cpus[n].arch_id = 2067 virt_cpu_mp_affinity(vms, n); 2068 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2069 ms->possible_cpus->cpus[n].props.thread_id = n; 2070 } 2071 return ms->possible_cpus; 2072 } 2073 2074 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2075 Error **errp) 2076 { 2077 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2078 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2079 2080 if (is_nvdimm) { 2081 error_setg(errp, "nvdimm is not yet supported"); 2082 return; 2083 } 2084 2085 if (!vms->acpi_dev) { 2086 error_setg(errp, 2087 "memory hotplug is not enabled: missing acpi-ged device"); 2088 return; 2089 } 2090 2091 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2092 } 2093 2094 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2095 DeviceState *dev, Error **errp) 2096 { 2097 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2098 Error *local_err = NULL; 2099 2100 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err); 2101 if (local_err) { 2102 goto out; 2103 } 2104 2105 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2106 dev, &error_abort); 2107 2108 out: 2109 error_propagate(errp, local_err); 2110 } 2111 2112 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2113 DeviceState *dev, Error **errp) 2114 { 2115 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2116 virt_memory_pre_plug(hotplug_dev, dev, errp); 2117 } 2118 } 2119 2120 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2121 DeviceState *dev, Error **errp) 2122 { 2123 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2124 2125 if (vms->platform_bus_dev) { 2126 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 2127 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2128 SYS_BUS_DEVICE(dev)); 2129 } 2130 } 2131 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2132 virt_memory_plug(hotplug_dev, dev, errp); 2133 } 2134 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2135 PCIDevice *pdev = PCI_DEVICE(dev); 2136 2137 vms->iommu = VIRT_IOMMU_VIRTIO; 2138 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2139 create_virtio_iommu_dt_bindings(vms); 2140 } 2141 } 2142 2143 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2144 DeviceState *dev, Error **errp) 2145 { 2146 error_setg(errp, "device unplug request for unsupported device" 2147 " type: %s", object_get_typename(OBJECT(dev))); 2148 } 2149 2150 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2151 DeviceState *dev) 2152 { 2153 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) || 2154 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { 2155 return HOTPLUG_HANDLER(machine); 2156 } 2157 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2158 VirtMachineState *vms = VIRT_MACHINE(machine); 2159 2160 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { 2161 return HOTPLUG_HANDLER(machine); 2162 } 2163 } 2164 return NULL; 2165 } 2166 2167 /* 2168 * for arm64 kvm_type [7-0] encodes the requested number of bits 2169 * in the IPA address space 2170 */ 2171 static int virt_kvm_type(MachineState *ms, const char *type_str) 2172 { 2173 VirtMachineState *vms = VIRT_MACHINE(ms); 2174 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 2175 int requested_pa_size; 2176 2177 /* we freeze the memory map to compute the highest gpa */ 2178 virt_set_memmap(vms); 2179 2180 requested_pa_size = 64 - clz64(vms->highest_gpa); 2181 2182 if (requested_pa_size > max_vm_pa_size) { 2183 error_report("-m and ,maxmem option values " 2184 "require an IPA range (%d bits) larger than " 2185 "the one supported by the host (%d bits)", 2186 requested_pa_size, max_vm_pa_size); 2187 exit(1); 2188 } 2189 /* 2190 * By default we return 0 which corresponds to an implicit legacy 2191 * 40b IPA setting. Otherwise we return the actual requested PA 2192 * logsize 2193 */ 2194 return requested_pa_size > 40 ? requested_pa_size : 0; 2195 } 2196 2197 static void virt_machine_class_init(ObjectClass *oc, void *data) 2198 { 2199 MachineClass *mc = MACHINE_CLASS(oc); 2200 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2201 2202 mc->init = machvirt_init; 2203 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2204 * The value may be reduced later when we have more information about the 2205 * configuration of the particular instance. 2206 */ 2207 mc->max_cpus = 512; 2208 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2209 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2210 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2211 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2212 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2213 mc->block_default_type = IF_VIRTIO; 2214 mc->no_cdrom = 1; 2215 mc->pci_allow_0_address = true; 2216 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2217 mc->minimum_page_bits = 12; 2218 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2219 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2220 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2221 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2222 mc->kvm_type = virt_kvm_type; 2223 assert(!mc->get_hotplug_handler); 2224 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2225 hc->pre_plug = virt_machine_device_pre_plug_cb; 2226 hc->plug = virt_machine_device_plug_cb; 2227 hc->unplug_request = virt_machine_device_unplug_request_cb; 2228 mc->numa_mem_supported = true; 2229 mc->auto_enable_numa_with_memhp = true; 2230 mc->default_ram_id = "mach-virt.ram"; 2231 2232 object_class_property_add(oc, "acpi", "OnOffAuto", 2233 virt_get_acpi, virt_set_acpi, 2234 NULL, NULL, &error_abort); 2235 object_class_property_set_description(oc, "acpi", 2236 "Enable ACPI", &error_abort); 2237 } 2238 2239 static void virt_instance_init(Object *obj) 2240 { 2241 VirtMachineState *vms = VIRT_MACHINE(obj); 2242 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2243 2244 /* EL3 is disabled by default on virt: this makes us consistent 2245 * between KVM and TCG for this board, and it also allows us to 2246 * boot UEFI blobs which assume no TrustZone support. 2247 */ 2248 vms->secure = false; 2249 object_property_add_bool(obj, "secure", virt_get_secure, 2250 virt_set_secure, NULL); 2251 object_property_set_description(obj, "secure", 2252 "Set on/off to enable/disable the ARM " 2253 "Security Extensions (TrustZone)", 2254 NULL); 2255 2256 /* EL2 is also disabled by default, for similar reasons */ 2257 vms->virt = false; 2258 object_property_add_bool(obj, "virtualization", virt_get_virt, 2259 virt_set_virt, NULL); 2260 object_property_set_description(obj, "virtualization", 2261 "Set on/off to enable/disable emulating a " 2262 "guest CPU which implements the ARM " 2263 "Virtualization Extensions", 2264 NULL); 2265 2266 /* High memory is enabled by default */ 2267 vms->highmem = true; 2268 object_property_add_bool(obj, "highmem", virt_get_highmem, 2269 virt_set_highmem, NULL); 2270 object_property_set_description(obj, "highmem", 2271 "Set on/off to enable/disable using " 2272 "physical address space above 32 bits", 2273 NULL); 2274 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 2275 object_property_add_str(obj, "gic-version", virt_get_gic_version, 2276 virt_set_gic_version, NULL); 2277 object_property_set_description(obj, "gic-version", 2278 "Set GIC version. " 2279 "Valid values are 2, 3, host and max", 2280 NULL); 2281 2282 vms->highmem_ecam = !vmc->no_highmem_ecam; 2283 2284 if (vmc->no_its) { 2285 vms->its = false; 2286 } else { 2287 /* Default allows ITS instantiation */ 2288 vms->its = true; 2289 object_property_add_bool(obj, "its", virt_get_its, 2290 virt_set_its, NULL); 2291 object_property_set_description(obj, "its", 2292 "Set on/off to enable/disable " 2293 "ITS instantiation", 2294 NULL); 2295 } 2296 2297 /* Default disallows iommu instantiation */ 2298 vms->iommu = VIRT_IOMMU_NONE; 2299 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 2300 object_property_set_description(obj, "iommu", 2301 "Set the IOMMU type. " 2302 "Valid values are none and smmuv3", 2303 NULL); 2304 2305 vms->irqmap = a15irqmap; 2306 2307 virt_flash_create(vms); 2308 } 2309 2310 static const TypeInfo virt_machine_info = { 2311 .name = TYPE_VIRT_MACHINE, 2312 .parent = TYPE_MACHINE, 2313 .abstract = true, 2314 .instance_size = sizeof(VirtMachineState), 2315 .class_size = sizeof(VirtMachineClass), 2316 .class_init = virt_machine_class_init, 2317 .instance_init = virt_instance_init, 2318 .interfaces = (InterfaceInfo[]) { 2319 { TYPE_HOTPLUG_HANDLER }, 2320 { } 2321 }, 2322 }; 2323 2324 static void machvirt_machine_init(void) 2325 { 2326 type_register_static(&virt_machine_info); 2327 } 2328 type_init(machvirt_machine_init); 2329 2330 static void virt_machine_5_0_options(MachineClass *mc) 2331 { 2332 static GlobalProperty compat[] = { 2333 { TYPE_TPM_TIS_SYSBUS, "ppi", "false" }, 2334 }; 2335 2336 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 2337 } 2338 DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) 2339 2340 static void virt_machine_4_2_options(MachineClass *mc) 2341 { 2342 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2343 2344 virt_machine_5_0_options(mc); 2345 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 2346 vmc->kvm_no_adjvtime = true; 2347 } 2348 DEFINE_VIRT_MACHINE(4, 2) 2349 2350 static void virt_machine_4_1_options(MachineClass *mc) 2351 { 2352 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2353 2354 virt_machine_4_2_options(mc); 2355 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 2356 vmc->no_ged = true; 2357 mc->auto_enable_numa_with_memhp = false; 2358 } 2359 DEFINE_VIRT_MACHINE(4, 1) 2360 2361 static void virt_machine_4_0_options(MachineClass *mc) 2362 { 2363 virt_machine_4_1_options(mc); 2364 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2365 } 2366 DEFINE_VIRT_MACHINE(4, 0) 2367 2368 static void virt_machine_3_1_options(MachineClass *mc) 2369 { 2370 virt_machine_4_0_options(mc); 2371 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2372 } 2373 DEFINE_VIRT_MACHINE(3, 1) 2374 2375 static void virt_machine_3_0_options(MachineClass *mc) 2376 { 2377 virt_machine_3_1_options(mc); 2378 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2379 } 2380 DEFINE_VIRT_MACHINE(3, 0) 2381 2382 static void virt_machine_2_12_options(MachineClass *mc) 2383 { 2384 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2385 2386 virt_machine_3_0_options(mc); 2387 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2388 vmc->no_highmem_ecam = true; 2389 mc->max_cpus = 255; 2390 } 2391 DEFINE_VIRT_MACHINE(2, 12) 2392 2393 static void virt_machine_2_11_options(MachineClass *mc) 2394 { 2395 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2396 2397 virt_machine_2_12_options(mc); 2398 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2399 vmc->smbios_old_sys_ver = true; 2400 } 2401 DEFINE_VIRT_MACHINE(2, 11) 2402 2403 static void virt_machine_2_10_options(MachineClass *mc) 2404 { 2405 virt_machine_2_11_options(mc); 2406 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2407 /* before 2.11 we never faulted accesses to bad addresses */ 2408 mc->ignore_memory_transaction_failures = true; 2409 } 2410 DEFINE_VIRT_MACHINE(2, 10) 2411 2412 static void virt_machine_2_9_options(MachineClass *mc) 2413 { 2414 virt_machine_2_10_options(mc); 2415 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2416 } 2417 DEFINE_VIRT_MACHINE(2, 9) 2418 2419 static void virt_machine_2_8_options(MachineClass *mc) 2420 { 2421 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2422 2423 virt_machine_2_9_options(mc); 2424 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2425 /* For 2.8 and earlier we falsely claimed in the DT that 2426 * our timers were edge-triggered, not level-triggered. 2427 */ 2428 vmc->claim_edge_triggered_timers = true; 2429 } 2430 DEFINE_VIRT_MACHINE(2, 8) 2431 2432 static void virt_machine_2_7_options(MachineClass *mc) 2433 { 2434 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2435 2436 virt_machine_2_8_options(mc); 2437 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2438 /* ITS was introduced with 2.8 */ 2439 vmc->no_its = true; 2440 /* Stick with 1K pages for migration compatibility */ 2441 mc->minimum_page_bits = 0; 2442 } 2443 DEFINE_VIRT_MACHINE(2, 7) 2444 2445 static void virt_machine_2_6_options(MachineClass *mc) 2446 { 2447 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2448 2449 virt_machine_2_7_options(mc); 2450 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2451 vmc->disallow_affinity_adjustment = true; 2452 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2453 vmc->no_pmu = true; 2454 } 2455 DEFINE_VIRT_MACHINE(2, 6) 2456