1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/boards.h" 45 #include "hw/compat.h" 46 #include "hw/loader.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/bitops.h" 49 #include "qemu/error-report.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/arm/virt-acpi-build.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic_common.h" 56 #include "kvm_arm.h" 57 #include "hw/smbios/smbios.h" 58 #include "qapi/visitor.h" 59 #include "standard-headers/linux/input.h" 60 61 /* Number of external interrupt lines to configure the GIC with */ 62 #define NUM_IRQS 256 63 64 #define PLATFORM_BUS_NUM_IRQS 64 65 66 static ARMPlatformBusSystemParams platform_bus_params; 67 68 typedef struct VirtBoardInfo { 69 struct arm_boot_info bootinfo; 70 const char *cpu_model; 71 const MemMapEntry *memmap; 72 const int *irqmap; 73 int smp_cpus; 74 void *fdt; 75 int fdt_size; 76 uint32_t clock_phandle; 77 uint32_t gic_phandle; 78 uint32_t v2m_phandle; 79 bool using_psci; 80 } VirtBoardInfo; 81 82 typedef struct { 83 MachineClass parent; 84 VirtBoardInfo *daughterboard; 85 } VirtMachineClass; 86 87 typedef struct { 88 MachineState parent; 89 bool secure; 90 bool highmem; 91 int32_t gic_version; 92 } VirtMachineState; 93 94 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 95 #define VIRT_MACHINE(obj) \ 96 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) 97 #define VIRT_MACHINE_GET_CLASS(obj) \ 98 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) 99 #define VIRT_MACHINE_CLASS(klass) \ 100 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) 101 102 103 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 104 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 105 void *data) \ 106 { \ 107 MachineClass *mc = MACHINE_CLASS(oc); \ 108 virt_machine_##major##_##minor##_options(mc); \ 109 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 110 if (latest) { \ 111 mc->alias = "virt"; \ 112 } \ 113 } \ 114 static const TypeInfo machvirt_##major##_##minor##_info = { \ 115 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 116 .parent = TYPE_VIRT_MACHINE, \ 117 .instance_init = virt_##major##_##minor##_instance_init, \ 118 .class_init = virt_##major##_##minor##_class_init, \ 119 }; \ 120 static void machvirt_machine_##major##_##minor##_init(void) \ 121 { \ 122 type_register_static(&machvirt_##major##_##minor##_info); \ 123 } \ 124 type_init(machvirt_machine_##major##_##minor##_init); 125 126 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 127 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 128 #define DEFINE_VIRT_MACHINE(major, minor) \ 129 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 130 131 132 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 133 * RAM can go up to the 256GB mark, leaving 256GB of the physical 134 * address space unallocated and free for future use between 256G and 512G. 135 * If we need to provide more RAM to VMs in the future then we need to: 136 * * allocate a second bank of RAM starting at 2TB and working up 137 * * fix the DT and ACPI table generation code in QEMU to correctly 138 * report two split lumps of RAM to the guest 139 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 140 * (We don't want to fill all the way up to 512GB with RAM because 141 * we might want it for non-RAM purposes later. Conversely it seems 142 * reasonable to assume that anybody configuring a VM with a quarter 143 * of a terabyte of RAM will be doing it on a host with more than a 144 * terabyte of physical address space.) 145 */ 146 #define RAMLIMIT_GB 255 147 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 148 149 /* Addresses and sizes of our components. 150 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 151 * 128MB..256MB is used for miscellaneous device I/O. 152 * 256MB..1GB is reserved for possible future PCI support (ie where the 153 * PCI memory window will go if we add a PCI host controller). 154 * 1GB and up is RAM (which may happily spill over into the 155 * high memory region beyond 4GB). 156 * This represents a compromise between how much RAM can be given to 157 * a 32 bit VM and leaving space for expansion and in particular for PCI. 158 * Note that devices should generally be placed at multiples of 0x10000, 159 * to accommodate guests using 64K pages. 160 */ 161 static const MemMapEntry a15memmap[] = { 162 /* Space up to 0x8000000 is reserved for a boot ROM */ 163 [VIRT_FLASH] = { 0, 0x08000000 }, 164 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 165 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 166 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 167 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 168 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 169 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 170 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 171 /* This redistributor space allows up to 2*64kB*123 CPUs */ 172 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 173 [VIRT_UART] = { 0x09000000, 0x00001000 }, 174 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 175 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 176 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 177 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 178 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 179 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 180 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 181 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 182 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 183 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 184 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 185 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 186 /* Second PCIe window, 512GB wide at the 512GB boundary */ 187 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 188 }; 189 190 static const int a15irqmap[] = { 191 [VIRT_UART] = 1, 192 [VIRT_RTC] = 2, 193 [VIRT_PCIE] = 3, /* ... to 6 */ 194 [VIRT_GPIO] = 7, 195 [VIRT_SECURE_UART] = 8, 196 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 197 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 198 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 199 }; 200 201 static VirtBoardInfo machines[] = { 202 { 203 .cpu_model = "cortex-a15", 204 .memmap = a15memmap, 205 .irqmap = a15irqmap, 206 }, 207 { 208 .cpu_model = "cortex-a53", 209 .memmap = a15memmap, 210 .irqmap = a15irqmap, 211 }, 212 { 213 .cpu_model = "cortex-a57", 214 .memmap = a15memmap, 215 .irqmap = a15irqmap, 216 }, 217 { 218 .cpu_model = "host", 219 .memmap = a15memmap, 220 .irqmap = a15irqmap, 221 }, 222 }; 223 224 static VirtBoardInfo *find_machine_info(const char *cpu) 225 { 226 int i; 227 228 for (i = 0; i < ARRAY_SIZE(machines); i++) { 229 if (strcmp(cpu, machines[i].cpu_model) == 0) { 230 return &machines[i]; 231 } 232 } 233 return NULL; 234 } 235 236 static void create_fdt(VirtBoardInfo *vbi) 237 { 238 void *fdt = create_device_tree(&vbi->fdt_size); 239 240 if (!fdt) { 241 error_report("create_device_tree() failed"); 242 exit(1); 243 } 244 245 vbi->fdt = fdt; 246 247 /* Header */ 248 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 249 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 250 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 251 252 /* 253 * /chosen and /memory nodes must exist for load_dtb 254 * to fill in necessary properties later 255 */ 256 qemu_fdt_add_subnode(fdt, "/chosen"); 257 qemu_fdt_add_subnode(fdt, "/memory"); 258 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 259 260 /* Clock node, for the benefit of the UART. The kernel device tree 261 * binding documentation claims the PL011 node clock properties are 262 * optional but in practice if you omit them the kernel refuses to 263 * probe for the device. 264 */ 265 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 266 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 267 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 268 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 269 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 270 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 271 "clk24mhz"); 272 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 273 274 } 275 276 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 277 { 278 uint32_t cpu_suspend_fn; 279 uint32_t cpu_off_fn; 280 uint32_t cpu_on_fn; 281 uint32_t migrate_fn; 282 void *fdt = vbi->fdt; 283 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 284 285 if (!vbi->using_psci) { 286 return; 287 } 288 289 qemu_fdt_add_subnode(fdt, "/psci"); 290 if (armcpu->psci_version == 2) { 291 const char comp[] = "arm,psci-0.2\0arm,psci"; 292 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 293 294 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 295 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 296 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 297 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 298 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 299 } else { 300 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 301 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 302 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 303 } 304 } else { 305 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 306 307 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 308 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 309 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 310 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 311 } 312 313 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 314 * to the instruction that should be used to invoke PSCI functions. 315 * However, the device tree binding uses 'method' instead, so that is 316 * what we should use here. 317 */ 318 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 319 320 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 321 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 322 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 323 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 324 } 325 326 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype) 327 { 328 /* Note that on A15 h/w these interrupts are level-triggered, 329 * but for the GIC implementation provided by both QEMU and KVM 330 * they are edge-triggered. 331 */ 332 ARMCPU *armcpu; 333 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 334 335 if (gictype == 2) { 336 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 337 GIC_FDT_IRQ_PPI_CPU_WIDTH, 338 (1 << vbi->smp_cpus) - 1); 339 } 340 341 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 342 343 armcpu = ARM_CPU(qemu_get_cpu(0)); 344 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 345 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 346 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", 347 compat, sizeof(compat)); 348 } else { 349 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", 350 "arm,armv7-timer"); 351 } 352 qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0); 353 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 354 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 355 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 356 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 358 } 359 360 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 361 { 362 int cpu; 363 int addr_cells = 1; 364 unsigned int i; 365 366 /* 367 * From Documentation/devicetree/bindings/arm/cpus.txt 368 * On ARM v8 64-bit systems value should be set to 2, 369 * that corresponds to the MPIDR_EL1 register size. 370 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 371 * in the system, #address-cells can be set to 1, since 372 * MPIDR_EL1[63:32] bits are not used for CPUs 373 * identification. 374 * 375 * Here we actually don't know whether our system is 32- or 64-bit one. 376 * The simplest way to go is to examine affinity IDs of all our CPUs. If 377 * at least one of them has Aff3 populated, we set #address-cells to 2. 378 */ 379 for (cpu = 0; cpu < vbi->smp_cpus; cpu++) { 380 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 381 382 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 383 addr_cells = 2; 384 break; 385 } 386 } 387 388 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 389 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells); 390 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 391 392 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 393 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 394 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 395 396 qemu_fdt_add_subnode(vbi->fdt, nodename); 397 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 398 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 399 armcpu->dtb_compatible); 400 401 if (vbi->using_psci && vbi->smp_cpus > 1) { 402 qemu_fdt_setprop_string(vbi->fdt, nodename, 403 "enable-method", "psci"); 404 } 405 406 if (addr_cells == 2) { 407 qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", 408 armcpu->mp_affinity); 409 } else { 410 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", 411 armcpu->mp_affinity); 412 } 413 414 for (i = 0; i < nb_numa_nodes; i++) { 415 if (test_bit(cpu, numa_info[i].node_cpu)) { 416 qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i); 417 } 418 } 419 420 g_free(nodename); 421 } 422 } 423 424 static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) 425 { 426 vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 427 qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); 428 qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", 429 "arm,gic-v2m-frame"); 430 qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); 431 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", 432 2, vbi->memmap[VIRT_GIC_V2M].base, 433 2, vbi->memmap[VIRT_GIC_V2M].size); 434 qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle); 435 } 436 437 static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) 438 { 439 vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 440 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); 441 442 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 443 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 444 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 445 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); 446 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); 447 qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); 448 if (type == 3) { 449 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 450 "arm,gic-v3"); 451 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 452 2, vbi->memmap[VIRT_GIC_DIST].base, 453 2, vbi->memmap[VIRT_GIC_DIST].size, 454 2, vbi->memmap[VIRT_GIC_REDIST].base, 455 2, vbi->memmap[VIRT_GIC_REDIST].size); 456 } else { 457 /* 'cortex-a15-gic' means 'GIC v2' */ 458 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 459 "arm,cortex-a15-gic"); 460 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 461 2, vbi->memmap[VIRT_GIC_DIST].base, 462 2, vbi->memmap[VIRT_GIC_DIST].size, 463 2, vbi->memmap[VIRT_GIC_CPU].base, 464 2, vbi->memmap[VIRT_GIC_CPU].size); 465 } 466 467 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); 468 } 469 470 static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype) 471 { 472 CPUState *cpu; 473 ARMCPU *armcpu; 474 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 475 476 CPU_FOREACH(cpu) { 477 armcpu = ARM_CPU(cpu); 478 if (!armcpu->has_pmu || 479 !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { 480 return; 481 } 482 } 483 484 if (gictype == 2) { 485 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 486 GIC_FDT_IRQ_PPI_CPU_WIDTH, 487 (1 << vbi->smp_cpus) - 1); 488 } 489 490 armcpu = ARM_CPU(qemu_get_cpu(0)); 491 qemu_fdt_add_subnode(vbi->fdt, "/pmu"); 492 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 493 const char compat[] = "arm,armv8-pmuv3"; 494 qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", 495 compat, sizeof(compat)); 496 qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", 497 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 498 } 499 } 500 501 static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) 502 { 503 int i; 504 int irq = vbi->irqmap[VIRT_GIC_V2M]; 505 DeviceState *dev; 506 507 dev = qdev_create(NULL, "arm-gicv2m"); 508 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); 509 qdev_prop_set_uint32(dev, "base-spi", irq); 510 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 511 qdev_init_nofail(dev); 512 513 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 514 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 515 } 516 517 fdt_add_v2m_gic_node(vbi); 518 } 519 520 static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure) 521 { 522 /* We create a standalone GIC */ 523 DeviceState *gicdev; 524 SysBusDevice *gicbusdev; 525 const char *gictype; 526 int i; 527 528 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 529 530 gicdev = qdev_create(NULL, gictype); 531 qdev_prop_set_uint32(gicdev, "revision", type); 532 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 533 /* Note that the num-irq property counts both internal and external 534 * interrupts; there are always 32 of the former (mandated by GIC spec). 535 */ 536 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 537 if (!kvm_irqchip_in_kernel()) { 538 qdev_prop_set_bit(gicdev, "has-security-extensions", secure); 539 } 540 qdev_init_nofail(gicdev); 541 gicbusdev = SYS_BUS_DEVICE(gicdev); 542 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 543 if (type == 3) { 544 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); 545 } else { 546 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 547 } 548 549 /* Wire the outputs from each CPU's generic timer to the 550 * appropriate GIC PPI inputs, and the GIC's IRQ output to 551 * the CPU's IRQ input. 552 */ 553 for (i = 0; i < smp_cpus; i++) { 554 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 555 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 556 int irq; 557 /* Mapping from the output timer irq lines from the CPU to the 558 * GIC PPI inputs we use for the virt board. 559 */ 560 const int timer_irq[] = { 561 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 562 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 563 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 564 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 565 }; 566 567 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 568 qdev_connect_gpio_out(cpudev, irq, 569 qdev_get_gpio_in(gicdev, 570 ppibase + timer_irq[irq])); 571 } 572 573 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 574 sysbus_connect_irq(gicbusdev, i + smp_cpus, 575 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 576 } 577 578 for (i = 0; i < NUM_IRQS; i++) { 579 pic[i] = qdev_get_gpio_in(gicdev, i); 580 } 581 582 fdt_add_gic_node(vbi, type); 583 584 if (type == 2) { 585 create_v2m(vbi, pic); 586 } 587 } 588 589 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart, 590 MemoryRegion *mem, CharDriverState *chr) 591 { 592 char *nodename; 593 hwaddr base = vbi->memmap[uart].base; 594 hwaddr size = vbi->memmap[uart].size; 595 int irq = vbi->irqmap[uart]; 596 const char compat[] = "arm,pl011\0arm,primecell"; 597 const char clocknames[] = "uartclk\0apb_pclk"; 598 DeviceState *dev = qdev_create(NULL, "pl011"); 599 SysBusDevice *s = SYS_BUS_DEVICE(dev); 600 601 qdev_prop_set_chr(dev, "chardev", chr); 602 qdev_init_nofail(dev); 603 memory_region_add_subregion(mem, base, 604 sysbus_mmio_get_region(s, 0)); 605 sysbus_connect_irq(s, 0, pic[irq]); 606 607 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 608 qemu_fdt_add_subnode(vbi->fdt, nodename); 609 /* Note that we can't use setprop_string because of the embedded NUL */ 610 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 611 compat, sizeof(compat)); 612 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 613 2, base, 2, size); 614 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 615 GIC_FDT_IRQ_TYPE_SPI, irq, 616 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 617 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 618 vbi->clock_phandle, vbi->clock_phandle); 619 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 620 clocknames, sizeof(clocknames)); 621 622 if (uart == VIRT_UART) { 623 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); 624 } else { 625 /* Mark as not usable by the normal world */ 626 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 627 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 628 } 629 630 g_free(nodename); 631 } 632 633 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 634 { 635 char *nodename; 636 hwaddr base = vbi->memmap[VIRT_RTC].base; 637 hwaddr size = vbi->memmap[VIRT_RTC].size; 638 int irq = vbi->irqmap[VIRT_RTC]; 639 const char compat[] = "arm,pl031\0arm,primecell"; 640 641 sysbus_create_simple("pl031", base, pic[irq]); 642 643 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 644 qemu_fdt_add_subnode(vbi->fdt, nodename); 645 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 646 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 647 2, base, 2, size); 648 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 649 GIC_FDT_IRQ_TYPE_SPI, irq, 650 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 651 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 652 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 653 g_free(nodename); 654 } 655 656 static DeviceState *gpio_key_dev; 657 static void virt_powerdown_req(Notifier *n, void *opaque) 658 { 659 /* use gpio Pin 3 for power button event */ 660 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 661 } 662 663 static Notifier virt_system_powerdown_notifier = { 664 .notify = virt_powerdown_req 665 }; 666 667 static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic) 668 { 669 char *nodename; 670 DeviceState *pl061_dev; 671 hwaddr base = vbi->memmap[VIRT_GPIO].base; 672 hwaddr size = vbi->memmap[VIRT_GPIO].size; 673 int irq = vbi->irqmap[VIRT_GPIO]; 674 const char compat[] = "arm,pl061\0arm,primecell"; 675 676 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 677 678 uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt); 679 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 680 qemu_fdt_add_subnode(vbi->fdt, nodename); 681 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 682 2, base, 2, size); 683 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 684 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2); 685 qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0); 686 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 687 GIC_FDT_IRQ_TYPE_SPI, irq, 688 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 689 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 690 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 691 qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle); 692 693 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 694 qdev_get_gpio_in(pl061_dev, 3)); 695 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys"); 696 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys"); 697 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0); 698 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1); 699 700 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff"); 701 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff", 702 "label", "GPIO Key Poweroff"); 703 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", 704 KEY_POWER); 705 qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff", 706 "gpios", phandle, 3, 0); 707 708 /* connect powerdown request */ 709 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 710 711 g_free(nodename); 712 } 713 714 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 715 { 716 int i; 717 hwaddr size = vbi->memmap[VIRT_MMIO].size; 718 719 /* We create the transports in forwards order. Since qbus_realize() 720 * prepends (not appends) new child buses, the incrementing loop below will 721 * create a list of virtio-mmio buses with decreasing base addresses. 722 * 723 * When a -device option is processed from the command line, 724 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 725 * order. The upshot is that -device options in increasing command line 726 * order are mapped to virtio-mmio buses with decreasing base addresses. 727 * 728 * When this code was originally written, that arrangement ensured that the 729 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 730 * the first -device on the command line. (The end-to-end order is a 731 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 732 * guest kernel's name-to-address assignment strategy.) 733 * 734 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 735 * the message, if not necessarily the code, of commit 70161ff336. 736 * Therefore the loop now establishes the inverse of the original intent. 737 * 738 * Unfortunately, we can't counteract the kernel change by reversing the 739 * loop; it would break existing command lines. 740 * 741 * In any case, the kernel makes no guarantee about the stability of 742 * enumeration order of virtio devices (as demonstrated by it changing 743 * between kernel versions). For reliable and stable identification 744 * of disks users must use UUIDs or similar mechanisms. 745 */ 746 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 747 int irq = vbi->irqmap[VIRT_MMIO] + i; 748 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 749 750 sysbus_create_simple("virtio-mmio", base, pic[irq]); 751 } 752 753 /* We add dtb nodes in reverse order so that they appear in the finished 754 * device tree lowest address first. 755 * 756 * Note that this mapping is independent of the loop above. The previous 757 * loop influences virtio device to virtio transport assignment, whereas 758 * this loop controls how virtio transports are laid out in the dtb. 759 */ 760 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 761 char *nodename; 762 int irq = vbi->irqmap[VIRT_MMIO] + i; 763 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 764 765 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 766 qemu_fdt_add_subnode(vbi->fdt, nodename); 767 qemu_fdt_setprop_string(vbi->fdt, nodename, 768 "compatible", "virtio,mmio"); 769 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 770 2, base, 2, size); 771 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 772 GIC_FDT_IRQ_TYPE_SPI, irq, 773 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 774 g_free(nodename); 775 } 776 } 777 778 static void create_one_flash(const char *name, hwaddr flashbase, 779 hwaddr flashsize, const char *file, 780 MemoryRegion *sysmem) 781 { 782 /* Create and map a single flash device. We use the same 783 * parameters as the flash devices on the Versatile Express board. 784 */ 785 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 786 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 787 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 788 const uint64_t sectorlength = 256 * 1024; 789 790 if (dinfo) { 791 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 792 &error_abort); 793 } 794 795 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 796 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 797 qdev_prop_set_uint8(dev, "width", 4); 798 qdev_prop_set_uint8(dev, "device-width", 2); 799 qdev_prop_set_bit(dev, "big-endian", false); 800 qdev_prop_set_uint16(dev, "id0", 0x89); 801 qdev_prop_set_uint16(dev, "id1", 0x18); 802 qdev_prop_set_uint16(dev, "id2", 0x00); 803 qdev_prop_set_uint16(dev, "id3", 0x00); 804 qdev_prop_set_string(dev, "name", name); 805 qdev_init_nofail(dev); 806 807 memory_region_add_subregion(sysmem, flashbase, 808 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 809 810 if (file) { 811 char *fn; 812 int image_size; 813 814 if (drive_get(IF_PFLASH, 0, 0)) { 815 error_report("The contents of the first flash device may be " 816 "specified with -bios or with -drive if=pflash... " 817 "but you cannot use both options at once"); 818 exit(1); 819 } 820 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 821 if (!fn) { 822 error_report("Could not find ROM image '%s'", file); 823 exit(1); 824 } 825 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 826 g_free(fn); 827 if (image_size < 0) { 828 error_report("Could not load ROM image '%s'", file); 829 exit(1); 830 } 831 } 832 } 833 834 static void create_flash(const VirtBoardInfo *vbi, 835 MemoryRegion *sysmem, 836 MemoryRegion *secure_sysmem) 837 { 838 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 839 * Any file passed via -bios goes in the first of these. 840 * sysmem is the system memory space. secure_sysmem is the secure view 841 * of the system, and the first flash device should be made visible only 842 * there. The second flash device is visible to both secure and nonsecure. 843 * If sysmem == secure_sysmem this means there is no separate Secure 844 * address space and both flash devices are generally visible. 845 */ 846 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; 847 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; 848 char *nodename; 849 850 create_one_flash("virt.flash0", flashbase, flashsize, 851 bios_name, secure_sysmem); 852 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 853 NULL, sysmem); 854 855 if (sysmem == secure_sysmem) { 856 /* Report both flash devices as a single node in the DT */ 857 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 858 qemu_fdt_add_subnode(vbi->fdt, nodename); 859 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 860 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 861 2, flashbase, 2, flashsize, 862 2, flashbase + flashsize, 2, flashsize); 863 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 864 g_free(nodename); 865 } else { 866 /* Report the devices as separate nodes so we can mark one as 867 * only visible to the secure world. 868 */ 869 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 870 qemu_fdt_add_subnode(vbi->fdt, nodename); 871 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 872 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 873 2, flashbase, 2, flashsize); 874 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 875 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 876 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 877 g_free(nodename); 878 879 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 880 qemu_fdt_add_subnode(vbi->fdt, nodename); 881 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 882 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 883 2, flashbase + flashsize, 2, flashsize); 884 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 885 g_free(nodename); 886 } 887 } 888 889 static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as) 890 { 891 hwaddr base = vbi->memmap[VIRT_FW_CFG].base; 892 hwaddr size = vbi->memmap[VIRT_FW_CFG].size; 893 char *nodename; 894 895 fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 896 897 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 898 qemu_fdt_add_subnode(vbi->fdt, nodename); 899 qemu_fdt_setprop_string(vbi->fdt, nodename, 900 "compatible", "qemu,fw-cfg-mmio"); 901 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 902 2, base, 2, size); 903 g_free(nodename); 904 } 905 906 static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, 907 int first_irq, const char *nodename) 908 { 909 int devfn, pin; 910 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 911 uint32_t *irq_map = full_irq_map; 912 913 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 914 for (pin = 0; pin < 4; pin++) { 915 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 916 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 917 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 918 int i; 919 920 uint32_t map[] = { 921 devfn << 8, 0, 0, /* devfn */ 922 pin + 1, /* PCI pin */ 923 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 924 925 /* Convert map to big endian */ 926 for (i = 0; i < 10; i++) { 927 irq_map[i] = cpu_to_be32(map[i]); 928 } 929 irq_map += 10; 930 } 931 } 932 933 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", 934 full_irq_map, sizeof(full_irq_map)); 935 936 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", 937 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 938 0x7 /* PCI irq */); 939 } 940 941 static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, 942 bool use_highmem) 943 { 944 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; 945 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; 946 hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; 947 hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; 948 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; 949 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; 950 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; 951 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; 952 hwaddr base = base_mmio; 953 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 954 int irq = vbi->irqmap[VIRT_PCIE]; 955 MemoryRegion *mmio_alias; 956 MemoryRegion *mmio_reg; 957 MemoryRegion *ecam_alias; 958 MemoryRegion *ecam_reg; 959 DeviceState *dev; 960 char *nodename; 961 int i; 962 PCIHostState *pci; 963 964 dev = qdev_create(NULL, TYPE_GPEX_HOST); 965 qdev_init_nofail(dev); 966 967 /* Map only the first size_ecam bytes of ECAM space */ 968 ecam_alias = g_new0(MemoryRegion, 1); 969 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 970 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 971 ecam_reg, 0, size_ecam); 972 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 973 974 /* Map the MMIO window into system address space so as to expose 975 * the section of PCI MMIO space which starts at the same base address 976 * (ie 1:1 mapping for that part of PCI MMIO space visible through 977 * the window). 978 */ 979 mmio_alias = g_new0(MemoryRegion, 1); 980 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 981 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 982 mmio_reg, base_mmio, size_mmio); 983 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 984 985 if (use_highmem) { 986 /* Map high MMIO space */ 987 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 988 989 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 990 mmio_reg, base_mmio_high, size_mmio_high); 991 memory_region_add_subregion(get_system_memory(), base_mmio_high, 992 high_mmio_alias); 993 } 994 995 /* Map IO port space */ 996 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 997 998 for (i = 0; i < GPEX_NUM_IRQS; i++) { 999 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1000 } 1001 1002 pci = PCI_HOST_BRIDGE(dev); 1003 if (pci->bus) { 1004 for (i = 0; i < nb_nics; i++) { 1005 NICInfo *nd = &nd_table[i]; 1006 1007 if (!nd->model) { 1008 nd->model = g_strdup("virtio"); 1009 } 1010 1011 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1012 } 1013 } 1014 1015 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1016 qemu_fdt_add_subnode(vbi->fdt, nodename); 1017 qemu_fdt_setprop_string(vbi->fdt, nodename, 1018 "compatible", "pci-host-ecam-generic"); 1019 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); 1020 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); 1021 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); 1022 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, 1023 nr_pcie_buses - 1); 1024 1025 if (vbi->v2m_phandle) { 1026 qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", 1027 vbi->v2m_phandle); 1028 } 1029 1030 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 1031 2, base_ecam, 2, size_ecam); 1032 1033 if (use_highmem) { 1034 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1035 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1036 2, base_pio, 2, size_pio, 1037 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1038 2, base_mmio, 2, size_mmio, 1039 1, FDT_PCI_RANGE_MMIO_64BIT, 1040 2, base_mmio_high, 1041 2, base_mmio_high, 2, size_mmio_high); 1042 } else { 1043 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1044 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1045 2, base_pio, 2, size_pio, 1046 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1047 2, base_mmio, 2, size_mmio); 1048 } 1049 1050 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); 1051 create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); 1052 1053 g_free(nodename); 1054 } 1055 1056 static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic) 1057 { 1058 DeviceState *dev; 1059 SysBusDevice *s; 1060 int i; 1061 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1062 MemoryRegion *sysmem = get_system_memory(); 1063 1064 platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; 1065 platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; 1066 platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; 1067 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1068 1069 fdt_params->system_params = &platform_bus_params; 1070 fdt_params->binfo = &vbi->bootinfo; 1071 fdt_params->intc = "/intc"; 1072 /* 1073 * register a machine init done notifier that creates the device tree 1074 * nodes of the platform bus and its children dynamic sysbus devices 1075 */ 1076 arm_register_platform_bus_fdt_creator(fdt_params); 1077 1078 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1079 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1080 qdev_prop_set_uint32(dev, "num_irqs", 1081 platform_bus_params.platform_bus_num_irqs); 1082 qdev_prop_set_uint32(dev, "mmio_size", 1083 platform_bus_params.platform_bus_size); 1084 qdev_init_nofail(dev); 1085 s = SYS_BUS_DEVICE(dev); 1086 1087 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1088 int irqn = platform_bus_params.platform_bus_first_irq + i; 1089 sysbus_connect_irq(s, i, pic[irqn]); 1090 } 1091 1092 memory_region_add_subregion(sysmem, 1093 platform_bus_params.platform_bus_base, 1094 sysbus_mmio_get_region(s, 0)); 1095 } 1096 1097 static void create_secure_ram(VirtBoardInfo *vbi, MemoryRegion *secure_sysmem) 1098 { 1099 MemoryRegion *secram = g_new(MemoryRegion, 1); 1100 char *nodename; 1101 hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base; 1102 hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size; 1103 1104 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1105 vmstate_register_ram_global(secram); 1106 memory_region_add_subregion(secure_sysmem, base, secram); 1107 1108 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1109 qemu_fdt_add_subnode(vbi->fdt, nodename); 1110 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory"); 1111 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size); 1112 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 1113 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 1114 1115 g_free(nodename); 1116 } 1117 1118 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1119 { 1120 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 1121 1122 *fdt_size = board->fdt_size; 1123 return board->fdt; 1124 } 1125 1126 static void virt_build_smbios(VirtGuestInfo *guest_info) 1127 { 1128 FWCfgState *fw_cfg = guest_info->fw_cfg; 1129 uint8_t *smbios_tables, *smbios_anchor; 1130 size_t smbios_tables_len, smbios_anchor_len; 1131 const char *product = "QEMU Virtual Machine"; 1132 1133 if (!fw_cfg) { 1134 return; 1135 } 1136 1137 if (kvm_enabled()) { 1138 product = "KVM Virtual Machine"; 1139 } 1140 1141 smbios_set_defaults("QEMU", product, 1142 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1143 1144 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1145 &smbios_anchor, &smbios_anchor_len); 1146 1147 if (smbios_anchor) { 1148 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 1149 smbios_tables, smbios_tables_len); 1150 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 1151 smbios_anchor, smbios_anchor_len); 1152 } 1153 } 1154 1155 static 1156 void virt_guest_info_machine_done(Notifier *notifier, void *data) 1157 { 1158 VirtGuestInfoState *guest_info_state = container_of(notifier, 1159 VirtGuestInfoState, machine_done); 1160 virt_acpi_setup(&guest_info_state->info); 1161 virt_build_smbios(&guest_info_state->info); 1162 } 1163 1164 static void machvirt_init(MachineState *machine) 1165 { 1166 VirtMachineState *vms = VIRT_MACHINE(machine); 1167 qemu_irq pic[NUM_IRQS]; 1168 MemoryRegion *sysmem = get_system_memory(); 1169 MemoryRegion *secure_sysmem = NULL; 1170 int gic_version = vms->gic_version; 1171 int n, virt_max_cpus; 1172 MemoryRegion *ram = g_new(MemoryRegion, 1); 1173 const char *cpu_model = machine->cpu_model; 1174 VirtBoardInfo *vbi; 1175 VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1176 VirtGuestInfo *guest_info = &guest_info_state->info; 1177 char **cpustr; 1178 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1179 1180 if (!cpu_model) { 1181 cpu_model = "cortex-a15"; 1182 } 1183 1184 /* We can probe only here because during property set 1185 * KVM is not available yet 1186 */ 1187 if (!gic_version) { 1188 if (!kvm_enabled()) { 1189 error_report("gic-version=host requires KVM"); 1190 exit(1); 1191 } 1192 1193 gic_version = kvm_arm_vgic_probe(); 1194 if (!gic_version) { 1195 error_report("Unable to determine GIC version supported by host"); 1196 exit(1); 1197 } 1198 } 1199 1200 /* Separate the actual CPU model name from any appended features */ 1201 cpustr = g_strsplit(cpu_model, ",", 2); 1202 1203 vbi = find_machine_info(cpustr[0]); 1204 1205 if (!vbi) { 1206 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1207 exit(1); 1208 } 1209 1210 /* If we have an EL3 boot ROM then the assumption is that it will 1211 * implement PSCI itself, so disable QEMU's internal implementation 1212 * so it doesn't get in the way. Instead of starting secondary 1213 * CPUs in PSCI powerdown state we will start them all running and 1214 * let the boot ROM sort them out. 1215 * The usual case is that we do use QEMU's PSCI implementation. 1216 */ 1217 vbi->using_psci = !(vms->secure && firmware_loaded); 1218 1219 /* The maximum number of CPUs depends on the GIC version, or on how 1220 * many redistributors we can fit into the memory map. 1221 */ 1222 if (gic_version == 3) { 1223 virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000; 1224 } else { 1225 virt_max_cpus = GIC_NCPU; 1226 } 1227 1228 if (max_cpus > virt_max_cpus) { 1229 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1230 "supported by machine 'mach-virt' (%d)", 1231 max_cpus, virt_max_cpus); 1232 exit(1); 1233 } 1234 1235 vbi->smp_cpus = smp_cpus; 1236 1237 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 1238 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1239 exit(1); 1240 } 1241 1242 if (vms->secure) { 1243 if (kvm_enabled()) { 1244 error_report("mach-virt: KVM does not support Security extensions"); 1245 exit(1); 1246 } 1247 1248 /* The Secure view of the world is the same as the NonSecure, 1249 * but with a few extra devices. Create it as a container region 1250 * containing the system memory at low priority; any secure-only 1251 * devices go in at higher priority and take precedence. 1252 */ 1253 secure_sysmem = g_new(MemoryRegion, 1); 1254 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1255 UINT64_MAX); 1256 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1257 } 1258 1259 create_fdt(vbi); 1260 1261 for (n = 0; n < smp_cpus; n++) { 1262 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1263 CPUClass *cc = CPU_CLASS(oc); 1264 Object *cpuobj; 1265 Error *err = NULL; 1266 char *cpuopts = g_strdup(cpustr[1]); 1267 1268 if (!oc) { 1269 error_report("Unable to find CPU definition"); 1270 exit(1); 1271 } 1272 cpuobj = object_new(object_class_get_name(oc)); 1273 1274 /* Handle any CPU options specified by the user */ 1275 cc->parse_features(CPU(cpuobj), cpuopts, &err); 1276 g_free(cpuopts); 1277 if (err) { 1278 error_report_err(err); 1279 exit(1); 1280 } 1281 1282 if (!vms->secure) { 1283 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1284 } 1285 1286 if (vbi->using_psci) { 1287 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, 1288 "psci-conduit", NULL); 1289 1290 /* Secondary CPUs start in PSCI powered-down state */ 1291 if (n > 0) { 1292 object_property_set_bool(cpuobj, true, 1293 "start-powered-off", NULL); 1294 } 1295 } 1296 1297 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1298 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 1299 "reset-cbar", &error_abort); 1300 } 1301 1302 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1303 &error_abort); 1304 if (vms->secure) { 1305 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1306 "secure-memory", &error_abort); 1307 } 1308 1309 object_property_set_bool(cpuobj, true, "realized", NULL); 1310 } 1311 g_strfreev(cpustr); 1312 fdt_add_timer_nodes(vbi, gic_version); 1313 fdt_add_cpu_nodes(vbi); 1314 fdt_add_psci_node(vbi); 1315 1316 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1317 machine->ram_size); 1318 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 1319 1320 create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1321 1322 create_gic(vbi, pic, gic_version, vms->secure); 1323 1324 fdt_add_pmu_nodes(vbi, gic_version); 1325 1326 create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]); 1327 1328 if (vms->secure) { 1329 create_secure_ram(vbi, secure_sysmem); 1330 create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1331 } 1332 1333 create_rtc(vbi, pic); 1334 1335 create_pcie(vbi, pic, vms->highmem); 1336 1337 create_gpio(vbi, pic); 1338 1339 /* Create mmio transports, so the user can create virtio backends 1340 * (which will be automatically plugged in to the transports). If 1341 * no backend is created the transport will just sit harmlessly idle. 1342 */ 1343 create_virtio_devices(vbi, pic); 1344 1345 create_fw_cfg(vbi, &address_space_memory); 1346 rom_set_fw(fw_cfg_find()); 1347 1348 guest_info->smp_cpus = smp_cpus; 1349 guest_info->fw_cfg = fw_cfg_find(); 1350 guest_info->memmap = vbi->memmap; 1351 guest_info->irqmap = vbi->irqmap; 1352 guest_info->use_highmem = vms->highmem; 1353 guest_info->gic_version = gic_version; 1354 guest_info_state->machine_done.notify = virt_guest_info_machine_done; 1355 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1356 1357 vbi->bootinfo.ram_size = machine->ram_size; 1358 vbi->bootinfo.kernel_filename = machine->kernel_filename; 1359 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1360 vbi->bootinfo.initrd_filename = machine->initrd_filename; 1361 vbi->bootinfo.nb_cpus = smp_cpus; 1362 vbi->bootinfo.board_id = -1; 1363 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 1364 vbi->bootinfo.get_dtb = machvirt_dtb; 1365 vbi->bootinfo.firmware_loaded = firmware_loaded; 1366 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 1367 1368 /* 1369 * arm_load_kernel machine init done notifier registration must 1370 * happen before the platform_bus_create call. In this latter, 1371 * another notifier is registered which adds platform bus nodes. 1372 * Notifiers are executed in registration reverse order. 1373 */ 1374 create_platform_bus(vbi, pic); 1375 } 1376 1377 static bool virt_get_secure(Object *obj, Error **errp) 1378 { 1379 VirtMachineState *vms = VIRT_MACHINE(obj); 1380 1381 return vms->secure; 1382 } 1383 1384 static void virt_set_secure(Object *obj, bool value, Error **errp) 1385 { 1386 VirtMachineState *vms = VIRT_MACHINE(obj); 1387 1388 vms->secure = value; 1389 } 1390 1391 static bool virt_get_highmem(Object *obj, Error **errp) 1392 { 1393 VirtMachineState *vms = VIRT_MACHINE(obj); 1394 1395 return vms->highmem; 1396 } 1397 1398 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1399 { 1400 VirtMachineState *vms = VIRT_MACHINE(obj); 1401 1402 vms->highmem = value; 1403 } 1404 1405 static char *virt_get_gic_version(Object *obj, Error **errp) 1406 { 1407 VirtMachineState *vms = VIRT_MACHINE(obj); 1408 const char *val = vms->gic_version == 3 ? "3" : "2"; 1409 1410 return g_strdup(val); 1411 } 1412 1413 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1414 { 1415 VirtMachineState *vms = VIRT_MACHINE(obj); 1416 1417 if (!strcmp(value, "3")) { 1418 vms->gic_version = 3; 1419 } else if (!strcmp(value, "2")) { 1420 vms->gic_version = 2; 1421 } else if (!strcmp(value, "host")) { 1422 vms->gic_version = 0; /* Will probe later */ 1423 } else { 1424 error_setg(errp, "Invalid gic-version value"); 1425 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1426 } 1427 } 1428 1429 static void virt_machine_class_init(ObjectClass *oc, void *data) 1430 { 1431 MachineClass *mc = MACHINE_CLASS(oc); 1432 1433 mc->init = machvirt_init; 1434 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1435 * it later in machvirt_init, where we have more information about the 1436 * configuration of the particular instance. 1437 */ 1438 mc->max_cpus = MAX_CPUMASK_BITS; 1439 mc->has_dynamic_sysbus = true; 1440 mc->block_default_type = IF_VIRTIO; 1441 mc->no_cdrom = 1; 1442 mc->pci_allow_0_address = true; 1443 } 1444 1445 static const TypeInfo virt_machine_info = { 1446 .name = TYPE_VIRT_MACHINE, 1447 .parent = TYPE_MACHINE, 1448 .abstract = true, 1449 .instance_size = sizeof(VirtMachineState), 1450 .class_size = sizeof(VirtMachineClass), 1451 .class_init = virt_machine_class_init, 1452 }; 1453 1454 static void machvirt_machine_init(void) 1455 { 1456 type_register_static(&virt_machine_info); 1457 } 1458 type_init(machvirt_machine_init); 1459 1460 static void virt_2_7_instance_init(Object *obj) 1461 { 1462 VirtMachineState *vms = VIRT_MACHINE(obj); 1463 1464 /* EL3 is disabled by default on virt: this makes us consistent 1465 * between KVM and TCG for this board, and it also allows us to 1466 * boot UEFI blobs which assume no TrustZone support. 1467 */ 1468 vms->secure = false; 1469 object_property_add_bool(obj, "secure", virt_get_secure, 1470 virt_set_secure, NULL); 1471 object_property_set_description(obj, "secure", 1472 "Set on/off to enable/disable the ARM " 1473 "Security Extensions (TrustZone)", 1474 NULL); 1475 1476 /* High memory is enabled by default */ 1477 vms->highmem = true; 1478 object_property_add_bool(obj, "highmem", virt_get_highmem, 1479 virt_set_highmem, NULL); 1480 object_property_set_description(obj, "highmem", 1481 "Set on/off to enable/disable using " 1482 "physical address space above 32 bits", 1483 NULL); 1484 /* Default GIC type is v2 */ 1485 vms->gic_version = 2; 1486 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1487 virt_set_gic_version, NULL); 1488 object_property_set_description(obj, "gic-version", 1489 "Set GIC version. " 1490 "Valid values are 2, 3 and host", NULL); 1491 } 1492 1493 static void virt_machine_2_7_options(MachineClass *mc) 1494 { 1495 } 1496 DEFINE_VIRT_MACHINE_AS_LATEST(2, 7) 1497 1498 #define VIRT_COMPAT_2_6 \ 1499 HW_COMPAT_2_6 1500 1501 static void virt_2_6_instance_init(Object *obj) 1502 { 1503 virt_2_7_instance_init(obj); 1504 } 1505 1506 static void virt_machine_2_6_options(MachineClass *mc) 1507 { 1508 virt_machine_2_7_options(mc); 1509 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1510 } 1511 DEFINE_VIRT_MACHINE(2, 6) 1512