xref: /openbmc/qemu/hw/arm/virt.c (revision d5938f29fea29581725426f203a74da746ca03e7)
1 /*
2  * ARM mach-virt emulation
3  *
4  * Copyright (c) 2013 Linaro Limited
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * Emulate a virtual board which works by passing Linux all the information
19  * it needs about what devices are present via the device tree.
20  * There are some restrictions about what we can do here:
21  *  + we can only present devices whose Linux drivers will work based
22  *    purely on the device tree with no platform data at all
23  *  + we want to present a very stripped-down minimalist platform,
24  *    both because this reduces the security attack surface from the guest
25  *    and also because it reduces our exposure to being broken when
26  *    the kernel updates its device tree bindings and requires further
27  *    information in a device binding that we aren't providing.
28  * This is essentially the same approach kvmtool uses.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "qapi/error.h"
36 #include "hw/sysbus.h"
37 #include "hw/boards.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/primecell.h"
40 #include "hw/arm/virt.h"
41 #include "hw/block/flash.h"
42 #include "hw/vfio/vfio-calxeda-xgmac.h"
43 #include "hw/vfio/vfio-amd-xgbe.h"
44 #include "hw/display/ramfb.h"
45 #include "net/net.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/sysemu.h"
49 #include "sysemu/kvm.h"
50 #include "hw/loader.h"
51 #include "exec/address-spaces.h"
52 #include "qemu/bitops.h"
53 #include "qemu/error-report.h"
54 #include "qemu/module.h"
55 #include "hw/pci-host/gpex.h"
56 #include "hw/arm/sysbus-fdt.h"
57 #include "hw/platform-bus.h"
58 #include "hw/qdev-properties.h"
59 #include "hw/arm/fdt.h"
60 #include "hw/intc/arm_gic.h"
61 #include "hw/intc/arm_gicv3_common.h"
62 #include "hw/irq.h"
63 #include "kvm_arm.h"
64 #include "hw/firmware/smbios.h"
65 #include "qapi/visitor.h"
66 #include "standard-headers/linux/input.h"
67 #include "hw/arm/smmuv3.h"
68 #include "hw/acpi/acpi.h"
69 #include "target/arm/internals.h"
70 
71 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
72     static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
73                                                     void *data) \
74     { \
75         MachineClass *mc = MACHINE_CLASS(oc); \
76         virt_machine_##major##_##minor##_options(mc); \
77         mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
78         if (latest) { \
79             mc->alias = "virt"; \
80         } \
81     } \
82     static const TypeInfo machvirt_##major##_##minor##_info = { \
83         .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
84         .parent = TYPE_VIRT_MACHINE, \
85         .class_init = virt_##major##_##minor##_class_init, \
86     }; \
87     static void machvirt_machine_##major##_##minor##_init(void) \
88     { \
89         type_register_static(&machvirt_##major##_##minor##_info); \
90     } \
91     type_init(machvirt_machine_##major##_##minor##_init);
92 
93 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
94     DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
95 #define DEFINE_VIRT_MACHINE(major, minor) \
96     DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
97 
98 
99 /* Number of external interrupt lines to configure the GIC with */
100 #define NUM_IRQS 256
101 
102 #define PLATFORM_BUS_NUM_IRQS 64
103 
104 /* Legacy RAM limit in GB (< version 4.0) */
105 #define LEGACY_RAMLIMIT_GB 255
106 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
107 
108 /* Addresses and sizes of our components.
109  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
110  * 128MB..256MB is used for miscellaneous device I/O.
111  * 256MB..1GB is reserved for possible future PCI support (ie where the
112  * PCI memory window will go if we add a PCI host controller).
113  * 1GB and up is RAM (which may happily spill over into the
114  * high memory region beyond 4GB).
115  * This represents a compromise between how much RAM can be given to
116  * a 32 bit VM and leaving space for expansion and in particular for PCI.
117  * Note that devices should generally be placed at multiples of 0x10000,
118  * to accommodate guests using 64K pages.
119  */
120 static const MemMapEntry base_memmap[] = {
121     /* Space up to 0x8000000 is reserved for a boot ROM */
122     [VIRT_FLASH] =              {          0, 0x08000000 },
123     [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
124     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
125     [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
126     [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
127     [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
128     [VIRT_GIC_HYP] =            { 0x08030000, 0x00010000 },
129     [VIRT_GIC_VCPU] =           { 0x08040000, 0x00010000 },
130     /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
131     [VIRT_GIC_ITS] =            { 0x08080000, 0x00020000 },
132     /* This redistributor space allows up to 2*64kB*123 CPUs */
133     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
134     [VIRT_UART] =               { 0x09000000, 0x00001000 },
135     [VIRT_RTC] =                { 0x09010000, 0x00001000 },
136     [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
137     [VIRT_GPIO] =               { 0x09030000, 0x00001000 },
138     [VIRT_SECURE_UART] =        { 0x09040000, 0x00001000 },
139     [VIRT_SMMU] =               { 0x09050000, 0x00020000 },
140     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
141     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
142     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
143     [VIRT_SECURE_MEM] =         { 0x0e000000, 0x01000000 },
144     [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
145     [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
146     [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
147     /* Actual RAM size depends on initial RAM and device memory settings */
148     [VIRT_MEM] =                { GiB, LEGACY_RAMLIMIT_BYTES },
149 };
150 
151 /*
152  * Highmem IO Regions: This memory map is floating, located after the RAM.
153  * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
154  * top of the RAM, so that its base get the same alignment as the size,
155  * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
156  * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
157  * Note the extended_memmap is sized so that it eventually also includes the
158  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
159  * index of base_memmap).
160  */
161 static MemMapEntry extended_memmap[] = {
162     /* Additional 64 MB redist region (can contain up to 512 redistributors) */
163     [VIRT_HIGH_GIC_REDIST2] =   { 0x0, 64 * MiB },
164     [VIRT_HIGH_PCIE_ECAM] =     { 0x0, 256 * MiB },
165     /* Second PCIe window */
166     [VIRT_HIGH_PCIE_MMIO] =     { 0x0, 512 * GiB },
167 };
168 
169 static const int a15irqmap[] = {
170     [VIRT_UART] = 1,
171     [VIRT_RTC] = 2,
172     [VIRT_PCIE] = 3, /* ... to 6 */
173     [VIRT_GPIO] = 7,
174     [VIRT_SECURE_UART] = 8,
175     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
176     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
177     [VIRT_SMMU] = 74,    /* ...to 74 + NUM_SMMU_IRQS - 1 */
178     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
179 };
180 
181 static const char *valid_cpus[] = {
182     ARM_CPU_TYPE_NAME("cortex-a7"),
183     ARM_CPU_TYPE_NAME("cortex-a15"),
184     ARM_CPU_TYPE_NAME("cortex-a53"),
185     ARM_CPU_TYPE_NAME("cortex-a57"),
186     ARM_CPU_TYPE_NAME("cortex-a72"),
187     ARM_CPU_TYPE_NAME("host"),
188     ARM_CPU_TYPE_NAME("max"),
189 };
190 
191 static bool cpu_type_valid(const char *cpu)
192 {
193     int i;
194 
195     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
196         if (strcmp(cpu, valid_cpus[i]) == 0) {
197             return true;
198         }
199     }
200     return false;
201 }
202 
203 static void create_fdt(VirtMachineState *vms)
204 {
205     void *fdt = create_device_tree(&vms->fdt_size);
206 
207     if (!fdt) {
208         error_report("create_device_tree() failed");
209         exit(1);
210     }
211 
212     vms->fdt = fdt;
213 
214     /* Header */
215     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
216     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
217     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
218 
219     /* /chosen must exist for load_dtb to fill in necessary properties later */
220     qemu_fdt_add_subnode(fdt, "/chosen");
221 
222     /* Clock node, for the benefit of the UART. The kernel device tree
223      * binding documentation claims the PL011 node clock properties are
224      * optional but in practice if you omit them the kernel refuses to
225      * probe for the device.
226      */
227     vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
228     qemu_fdt_add_subnode(fdt, "/apb-pclk");
229     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
230     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
231     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
232     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
233                                 "clk24mhz");
234     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
235 
236     if (have_numa_distance) {
237         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
238         uint32_t *matrix = g_malloc0(size);
239         int idx, i, j;
240 
241         for (i = 0; i < nb_numa_nodes; i++) {
242             for (j = 0; j < nb_numa_nodes; j++) {
243                 idx = (i * nb_numa_nodes + j) * 3;
244                 matrix[idx + 0] = cpu_to_be32(i);
245                 matrix[idx + 1] = cpu_to_be32(j);
246                 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
247             }
248         }
249 
250         qemu_fdt_add_subnode(fdt, "/distance-map");
251         qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
252                                 "numa-distance-map-v1");
253         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
254                          matrix, size);
255         g_free(matrix);
256     }
257 }
258 
259 static void fdt_add_timer_nodes(const VirtMachineState *vms)
260 {
261     /* On real hardware these interrupts are level-triggered.
262      * On KVM they were edge-triggered before host kernel version 4.4,
263      * and level-triggered afterwards.
264      * On emulated QEMU they are level-triggered.
265      *
266      * Getting the DTB info about them wrong is awkward for some
267      * guest kernels:
268      *  pre-4.8 ignore the DT and leave the interrupt configured
269      *   with whatever the GIC reset value (or the bootloader) left it at
270      *  4.8 before rc6 honour the incorrect data by programming it back
271      *   into the GIC, causing problems
272      *  4.8rc6 and later ignore the DT and always write "level triggered"
273      *   into the GIC
274      *
275      * For backwards-compatibility, virt-2.8 and earlier will continue
276      * to say these are edge-triggered, but later machines will report
277      * the correct information.
278      */
279     ARMCPU *armcpu;
280     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
281     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
282 
283     if (vmc->claim_edge_triggered_timers) {
284         irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
285     }
286 
287     if (vms->gic_version == 2) {
288         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
289                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
290                              (1 << vms->smp_cpus) - 1);
291     }
292 
293     qemu_fdt_add_subnode(vms->fdt, "/timer");
294 
295     armcpu = ARM_CPU(qemu_get_cpu(0));
296     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
297         const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
298         qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
299                          compat, sizeof(compat));
300     } else {
301         qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
302                                 "arm,armv7-timer");
303     }
304     qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
305     qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
306                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
307                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
308                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
309                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
310 }
311 
312 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
313 {
314     int cpu;
315     int addr_cells = 1;
316     const MachineState *ms = MACHINE(vms);
317 
318     /*
319      * From Documentation/devicetree/bindings/arm/cpus.txt
320      *  On ARM v8 64-bit systems value should be set to 2,
321      *  that corresponds to the MPIDR_EL1 register size.
322      *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
323      *  in the system, #address-cells can be set to 1, since
324      *  MPIDR_EL1[63:32] bits are not used for CPUs
325      *  identification.
326      *
327      *  Here we actually don't know whether our system is 32- or 64-bit one.
328      *  The simplest way to go is to examine affinity IDs of all our CPUs. If
329      *  at least one of them has Aff3 populated, we set #address-cells to 2.
330      */
331     for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
332         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
333 
334         if (armcpu->mp_affinity & ARM_AFF3_MASK) {
335             addr_cells = 2;
336             break;
337         }
338     }
339 
340     qemu_fdt_add_subnode(vms->fdt, "/cpus");
341     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
342     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
343 
344     for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
345         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
346         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
347         CPUState *cs = CPU(armcpu);
348 
349         qemu_fdt_add_subnode(vms->fdt, nodename);
350         qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
351         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
352                                     armcpu->dtb_compatible);
353 
354         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
355             && vms->smp_cpus > 1) {
356             qemu_fdt_setprop_string(vms->fdt, nodename,
357                                         "enable-method", "psci");
358         }
359 
360         if (addr_cells == 2) {
361             qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
362                                  armcpu->mp_affinity);
363         } else {
364             qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
365                                   armcpu->mp_affinity);
366         }
367 
368         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
369             qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
370                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
371         }
372 
373         g_free(nodename);
374     }
375 }
376 
377 static void fdt_add_its_gic_node(VirtMachineState *vms)
378 {
379     char *nodename;
380 
381     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
382     nodename = g_strdup_printf("/intc/its@%" PRIx64,
383                                vms->memmap[VIRT_GIC_ITS].base);
384     qemu_fdt_add_subnode(vms->fdt, nodename);
385     qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
386                             "arm,gic-v3-its");
387     qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
388     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
389                                  2, vms->memmap[VIRT_GIC_ITS].base,
390                                  2, vms->memmap[VIRT_GIC_ITS].size);
391     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
392     g_free(nodename);
393 }
394 
395 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
396 {
397     char *nodename;
398 
399     nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
400                                vms->memmap[VIRT_GIC_V2M].base);
401     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
402     qemu_fdt_add_subnode(vms->fdt, nodename);
403     qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
404                             "arm,gic-v2m-frame");
405     qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
406     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
407                                  2, vms->memmap[VIRT_GIC_V2M].base,
408                                  2, vms->memmap[VIRT_GIC_V2M].size);
409     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
410     g_free(nodename);
411 }
412 
413 static void fdt_add_gic_node(VirtMachineState *vms)
414 {
415     char *nodename;
416 
417     vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
418     qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
419 
420     nodename = g_strdup_printf("/intc@%" PRIx64,
421                                vms->memmap[VIRT_GIC_DIST].base);
422     qemu_fdt_add_subnode(vms->fdt, nodename);
423     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
424     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
425     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
426     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
427     qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
428     if (vms->gic_version == 3) {
429         int nb_redist_regions = virt_gicv3_redist_region_count(vms);
430 
431         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
432                                 "arm,gic-v3");
433 
434         qemu_fdt_setprop_cell(vms->fdt, nodename,
435                               "#redistributor-regions", nb_redist_regions);
436 
437         if (nb_redist_regions == 1) {
438             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
439                                          2, vms->memmap[VIRT_GIC_DIST].base,
440                                          2, vms->memmap[VIRT_GIC_DIST].size,
441                                          2, vms->memmap[VIRT_GIC_REDIST].base,
442                                          2, vms->memmap[VIRT_GIC_REDIST].size);
443         } else {
444             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
445                                  2, vms->memmap[VIRT_GIC_DIST].base,
446                                  2, vms->memmap[VIRT_GIC_DIST].size,
447                                  2, vms->memmap[VIRT_GIC_REDIST].base,
448                                  2, vms->memmap[VIRT_GIC_REDIST].size,
449                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
450                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
451         }
452 
453         if (vms->virt) {
454             qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
455                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
456                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
457         }
458     } else {
459         /* 'cortex-a15-gic' means 'GIC v2' */
460         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
461                                 "arm,cortex-a15-gic");
462         if (!vms->virt) {
463             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
464                                          2, vms->memmap[VIRT_GIC_DIST].base,
465                                          2, vms->memmap[VIRT_GIC_DIST].size,
466                                          2, vms->memmap[VIRT_GIC_CPU].base,
467                                          2, vms->memmap[VIRT_GIC_CPU].size);
468         } else {
469             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
470                                          2, vms->memmap[VIRT_GIC_DIST].base,
471                                          2, vms->memmap[VIRT_GIC_DIST].size,
472                                          2, vms->memmap[VIRT_GIC_CPU].base,
473                                          2, vms->memmap[VIRT_GIC_CPU].size,
474                                          2, vms->memmap[VIRT_GIC_HYP].base,
475                                          2, vms->memmap[VIRT_GIC_HYP].size,
476                                          2, vms->memmap[VIRT_GIC_VCPU].base,
477                                          2, vms->memmap[VIRT_GIC_VCPU].size);
478             qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
479                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
480                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
481         }
482     }
483 
484     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
485     g_free(nodename);
486 }
487 
488 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
489 {
490     CPUState *cpu;
491     ARMCPU *armcpu;
492     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
493 
494     CPU_FOREACH(cpu) {
495         armcpu = ARM_CPU(cpu);
496         if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
497             return;
498         }
499         if (kvm_enabled()) {
500             if (kvm_irqchip_in_kernel()) {
501                 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
502             }
503             kvm_arm_pmu_init(cpu);
504         }
505     }
506 
507     if (vms->gic_version == 2) {
508         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
509                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
510                              (1 << vms->smp_cpus) - 1);
511     }
512 
513     armcpu = ARM_CPU(qemu_get_cpu(0));
514     qemu_fdt_add_subnode(vms->fdt, "/pmu");
515     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
516         const char compat[] = "arm,armv8-pmuv3";
517         qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
518                          compat, sizeof(compat));
519         qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
520                                GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
521     }
522 }
523 
524 static void create_its(VirtMachineState *vms, DeviceState *gicdev)
525 {
526     const char *itsclass = its_class_name();
527     DeviceState *dev;
528 
529     if (!itsclass) {
530         /* Do nothing if not supported */
531         return;
532     }
533 
534     dev = qdev_create(NULL, itsclass);
535 
536     object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
537                              &error_abort);
538     qdev_init_nofail(dev);
539     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
540 
541     fdt_add_its_gic_node(vms);
542 }
543 
544 static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
545 {
546     int i;
547     int irq = vms->irqmap[VIRT_GIC_V2M];
548     DeviceState *dev;
549 
550     dev = qdev_create(NULL, "arm-gicv2m");
551     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
552     qdev_prop_set_uint32(dev, "base-spi", irq);
553     qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
554     qdev_init_nofail(dev);
555 
556     for (i = 0; i < NUM_GICV2M_SPIS; i++) {
557         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
558     }
559 
560     fdt_add_v2m_gic_node(vms);
561 }
562 
563 static void create_gic(VirtMachineState *vms, qemu_irq *pic)
564 {
565     MachineState *ms = MACHINE(vms);
566     /* We create a standalone GIC */
567     DeviceState *gicdev;
568     SysBusDevice *gicbusdev;
569     const char *gictype;
570     int type = vms->gic_version, i;
571     unsigned int smp_cpus = ms->smp.cpus;
572     uint32_t nb_redist_regions = 0;
573 
574     gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
575 
576     gicdev = qdev_create(NULL, gictype);
577     qdev_prop_set_uint32(gicdev, "revision", type);
578     qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
579     /* Note that the num-irq property counts both internal and external
580      * interrupts; there are always 32 of the former (mandated by GIC spec).
581      */
582     qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
583     if (!kvm_irqchip_in_kernel()) {
584         qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
585     }
586 
587     if (type == 3) {
588         uint32_t redist0_capacity =
589                     vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
590         uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
591 
592         nb_redist_regions = virt_gicv3_redist_region_count(vms);
593 
594         qdev_prop_set_uint32(gicdev, "len-redist-region-count",
595                              nb_redist_regions);
596         qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
597 
598         if (nb_redist_regions == 2) {
599             uint32_t redist1_capacity =
600                     vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
601 
602             qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
603                 MIN(smp_cpus - redist0_count, redist1_capacity));
604         }
605     } else {
606         if (!kvm_irqchip_in_kernel()) {
607             qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
608                               vms->virt);
609         }
610     }
611     qdev_init_nofail(gicdev);
612     gicbusdev = SYS_BUS_DEVICE(gicdev);
613     sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
614     if (type == 3) {
615         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
616         if (nb_redist_regions == 2) {
617             sysbus_mmio_map(gicbusdev, 2,
618                             vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
619         }
620     } else {
621         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
622         if (vms->virt) {
623             sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
624             sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
625         }
626     }
627 
628     /* Wire the outputs from each CPU's generic timer and the GICv3
629      * maintenance interrupt signal to the appropriate GIC PPI inputs,
630      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
631      */
632     for (i = 0; i < smp_cpus; i++) {
633         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
634         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
635         int irq;
636         /* Mapping from the output timer irq lines from the CPU to the
637          * GIC PPI inputs we use for the virt board.
638          */
639         const int timer_irq[] = {
640             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
641             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
642             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
643             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
644         };
645 
646         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
647             qdev_connect_gpio_out(cpudev, irq,
648                                   qdev_get_gpio_in(gicdev,
649                                                    ppibase + timer_irq[irq]));
650         }
651 
652         if (type == 3) {
653             qemu_irq irq = qdev_get_gpio_in(gicdev,
654                                             ppibase + ARCH_GIC_MAINT_IRQ);
655             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
656                                         0, irq);
657         } else if (vms->virt) {
658             qemu_irq irq = qdev_get_gpio_in(gicdev,
659                                             ppibase + ARCH_GIC_MAINT_IRQ);
660             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
661         }
662 
663         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
664                                     qdev_get_gpio_in(gicdev, ppibase
665                                                      + VIRTUAL_PMU_IRQ));
666 
667         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
668         sysbus_connect_irq(gicbusdev, i + smp_cpus,
669                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
670         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
671                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
672         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
673                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
674     }
675 
676     for (i = 0; i < NUM_IRQS; i++) {
677         pic[i] = qdev_get_gpio_in(gicdev, i);
678     }
679 
680     fdt_add_gic_node(vms);
681 
682     if (type == 3 && vms->its) {
683         create_its(vms, gicdev);
684     } else if (type == 2) {
685         create_v2m(vms, pic);
686     }
687 }
688 
689 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
690                         MemoryRegion *mem, Chardev *chr)
691 {
692     char *nodename;
693     hwaddr base = vms->memmap[uart].base;
694     hwaddr size = vms->memmap[uart].size;
695     int irq = vms->irqmap[uart];
696     const char compat[] = "arm,pl011\0arm,primecell";
697     const char clocknames[] = "uartclk\0apb_pclk";
698     DeviceState *dev = qdev_create(NULL, "pl011");
699     SysBusDevice *s = SYS_BUS_DEVICE(dev);
700 
701     qdev_prop_set_chr(dev, "chardev", chr);
702     qdev_init_nofail(dev);
703     memory_region_add_subregion(mem, base,
704                                 sysbus_mmio_get_region(s, 0));
705     sysbus_connect_irq(s, 0, pic[irq]);
706 
707     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
708     qemu_fdt_add_subnode(vms->fdt, nodename);
709     /* Note that we can't use setprop_string because of the embedded NUL */
710     qemu_fdt_setprop(vms->fdt, nodename, "compatible",
711                          compat, sizeof(compat));
712     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
713                                      2, base, 2, size);
714     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
715                                GIC_FDT_IRQ_TYPE_SPI, irq,
716                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
717     qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
718                                vms->clock_phandle, vms->clock_phandle);
719     qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
720                          clocknames, sizeof(clocknames));
721 
722     if (uart == VIRT_UART) {
723         qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
724     } else {
725         /* Mark as not usable by the normal world */
726         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
727         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
728 
729         qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
730         qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
731                                 nodename);
732     }
733 
734     g_free(nodename);
735 }
736 
737 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
738 {
739     char *nodename;
740     hwaddr base = vms->memmap[VIRT_RTC].base;
741     hwaddr size = vms->memmap[VIRT_RTC].size;
742     int irq = vms->irqmap[VIRT_RTC];
743     const char compat[] = "arm,pl031\0arm,primecell";
744 
745     sysbus_create_simple("pl031", base, pic[irq]);
746 
747     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
748     qemu_fdt_add_subnode(vms->fdt, nodename);
749     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
750     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
751                                  2, base, 2, size);
752     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
753                            GIC_FDT_IRQ_TYPE_SPI, irq,
754                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
755     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
756     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
757     g_free(nodename);
758 }
759 
760 static DeviceState *gpio_key_dev;
761 static void virt_powerdown_req(Notifier *n, void *opaque)
762 {
763     /* use gpio Pin 3 for power button event */
764     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
765 }
766 
767 static Notifier virt_system_powerdown_notifier = {
768     .notify = virt_powerdown_req
769 };
770 
771 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
772 {
773     char *nodename;
774     DeviceState *pl061_dev;
775     hwaddr base = vms->memmap[VIRT_GPIO].base;
776     hwaddr size = vms->memmap[VIRT_GPIO].size;
777     int irq = vms->irqmap[VIRT_GPIO];
778     const char compat[] = "arm,pl061\0arm,primecell";
779 
780     pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
781 
782     uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
783     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
784     qemu_fdt_add_subnode(vms->fdt, nodename);
785     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
786                                  2, base, 2, size);
787     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
788     qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
789     qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
790     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
791                            GIC_FDT_IRQ_TYPE_SPI, irq,
792                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
793     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
794     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
795     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
796 
797     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
798                                         qdev_get_gpio_in(pl061_dev, 3));
799     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
800     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
801     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
802     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
803 
804     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
805     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
806                             "label", "GPIO Key Poweroff");
807     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
808                           KEY_POWER);
809     qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
810                            "gpios", phandle, 3, 0);
811 
812     /* connect powerdown request */
813     qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
814 
815     g_free(nodename);
816 }
817 
818 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
819 {
820     int i;
821     hwaddr size = vms->memmap[VIRT_MMIO].size;
822 
823     /* We create the transports in forwards order. Since qbus_realize()
824      * prepends (not appends) new child buses, the incrementing loop below will
825      * create a list of virtio-mmio buses with decreasing base addresses.
826      *
827      * When a -device option is processed from the command line,
828      * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
829      * order. The upshot is that -device options in increasing command line
830      * order are mapped to virtio-mmio buses with decreasing base addresses.
831      *
832      * When this code was originally written, that arrangement ensured that the
833      * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
834      * the first -device on the command line. (The end-to-end order is a
835      * function of this loop, qbus_realize(), qbus_find_recursive(), and the
836      * guest kernel's name-to-address assignment strategy.)
837      *
838      * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
839      * the message, if not necessarily the code, of commit 70161ff336.
840      * Therefore the loop now establishes the inverse of the original intent.
841      *
842      * Unfortunately, we can't counteract the kernel change by reversing the
843      * loop; it would break existing command lines.
844      *
845      * In any case, the kernel makes no guarantee about the stability of
846      * enumeration order of virtio devices (as demonstrated by it changing
847      * between kernel versions). For reliable and stable identification
848      * of disks users must use UUIDs or similar mechanisms.
849      */
850     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
851         int irq = vms->irqmap[VIRT_MMIO] + i;
852         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
853 
854         sysbus_create_simple("virtio-mmio", base, pic[irq]);
855     }
856 
857     /* We add dtb nodes in reverse order so that they appear in the finished
858      * device tree lowest address first.
859      *
860      * Note that this mapping is independent of the loop above. The previous
861      * loop influences virtio device to virtio transport assignment, whereas
862      * this loop controls how virtio transports are laid out in the dtb.
863      */
864     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
865         char *nodename;
866         int irq = vms->irqmap[VIRT_MMIO] + i;
867         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
868 
869         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
870         qemu_fdt_add_subnode(vms->fdt, nodename);
871         qemu_fdt_setprop_string(vms->fdt, nodename,
872                                 "compatible", "virtio,mmio");
873         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
874                                      2, base, 2, size);
875         qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
876                                GIC_FDT_IRQ_TYPE_SPI, irq,
877                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
878         qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
879         g_free(nodename);
880     }
881 }
882 
883 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
884 
885 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
886                                         const char *name,
887                                         const char *alias_prop_name)
888 {
889     /*
890      * Create a single flash device.  We use the same parameters as
891      * the flash devices on the Versatile Express board.
892      */
893     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
894 
895     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
896     qdev_prop_set_uint8(dev, "width", 4);
897     qdev_prop_set_uint8(dev, "device-width", 2);
898     qdev_prop_set_bit(dev, "big-endian", false);
899     qdev_prop_set_uint16(dev, "id0", 0x89);
900     qdev_prop_set_uint16(dev, "id1", 0x18);
901     qdev_prop_set_uint16(dev, "id2", 0x00);
902     qdev_prop_set_uint16(dev, "id3", 0x00);
903     qdev_prop_set_string(dev, "name", name);
904     object_property_add_child(OBJECT(vms), name, OBJECT(dev),
905                               &error_abort);
906     object_property_add_alias(OBJECT(vms), alias_prop_name,
907                               OBJECT(dev), "drive", &error_abort);
908     return PFLASH_CFI01(dev);
909 }
910 
911 static void virt_flash_create(VirtMachineState *vms)
912 {
913     vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
914     vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
915 }
916 
917 static void virt_flash_map1(PFlashCFI01 *flash,
918                             hwaddr base, hwaddr size,
919                             MemoryRegion *sysmem)
920 {
921     DeviceState *dev = DEVICE(flash);
922 
923     assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
924     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
925     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
926     qdev_init_nofail(dev);
927 
928     memory_region_add_subregion(sysmem, base,
929                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
930                                                        0));
931 }
932 
933 static void virt_flash_map(VirtMachineState *vms,
934                            MemoryRegion *sysmem,
935                            MemoryRegion *secure_sysmem)
936 {
937     /*
938      * Map two flash devices to fill the VIRT_FLASH space in the memmap.
939      * sysmem is the system memory space. secure_sysmem is the secure view
940      * of the system, and the first flash device should be made visible only
941      * there. The second flash device is visible to both secure and nonsecure.
942      * If sysmem == secure_sysmem this means there is no separate Secure
943      * address space and both flash devices are generally visible.
944      */
945     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
946     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
947 
948     virt_flash_map1(vms->flash[0], flashbase, flashsize,
949                     secure_sysmem);
950     virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
951                     sysmem);
952 }
953 
954 static void virt_flash_fdt(VirtMachineState *vms,
955                            MemoryRegion *sysmem,
956                            MemoryRegion *secure_sysmem)
957 {
958     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
959     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
960     char *nodename;
961 
962     if (sysmem == secure_sysmem) {
963         /* Report both flash devices as a single node in the DT */
964         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
965         qemu_fdt_add_subnode(vms->fdt, nodename);
966         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
967         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
968                                      2, flashbase, 2, flashsize,
969                                      2, flashbase + flashsize, 2, flashsize);
970         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
971         g_free(nodename);
972     } else {
973         /*
974          * Report the devices as separate nodes so we can mark one as
975          * only visible to the secure world.
976          */
977         nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
978         qemu_fdt_add_subnode(vms->fdt, nodename);
979         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
980         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
981                                      2, flashbase, 2, flashsize);
982         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
983         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
984         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
985         g_free(nodename);
986 
987         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
988         qemu_fdt_add_subnode(vms->fdt, nodename);
989         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
990         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
991                                      2, flashbase + flashsize, 2, flashsize);
992         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
993         g_free(nodename);
994     }
995 }
996 
997 static bool virt_firmware_init(VirtMachineState *vms,
998                                MemoryRegion *sysmem,
999                                MemoryRegion *secure_sysmem)
1000 {
1001     int i;
1002     BlockBackend *pflash_blk0;
1003 
1004     /* Map legacy -drive if=pflash to machine properties */
1005     for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1006         pflash_cfi01_legacy_drive(vms->flash[i],
1007                                   drive_get(IF_PFLASH, 0, i));
1008     }
1009 
1010     virt_flash_map(vms, sysmem, secure_sysmem);
1011 
1012     pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1013 
1014     if (bios_name) {
1015         char *fname;
1016         MemoryRegion *mr;
1017         int image_size;
1018 
1019         if (pflash_blk0) {
1020             error_report("The contents of the first flash device may be "
1021                          "specified with -bios or with -drive if=pflash... "
1022                          "but you cannot use both options at once");
1023             exit(1);
1024         }
1025 
1026         /* Fall back to -bios */
1027 
1028         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1029         if (!fname) {
1030             error_report("Could not find ROM image '%s'", bios_name);
1031             exit(1);
1032         }
1033         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1034         image_size = load_image_mr(fname, mr);
1035         g_free(fname);
1036         if (image_size < 0) {
1037             error_report("Could not load ROM image '%s'", bios_name);
1038             exit(1);
1039         }
1040     }
1041 
1042     return pflash_blk0 || bios_name;
1043 }
1044 
1045 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1046 {
1047     MachineState *ms = MACHINE(vms);
1048     hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1049     hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1050     FWCfgState *fw_cfg;
1051     char *nodename;
1052 
1053     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1054     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1055 
1056     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1057     qemu_fdt_add_subnode(vms->fdt, nodename);
1058     qemu_fdt_setprop_string(vms->fdt, nodename,
1059                             "compatible", "qemu,fw-cfg-mmio");
1060     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1061                                  2, base, 2, size);
1062     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1063     g_free(nodename);
1064     return fw_cfg;
1065 }
1066 
1067 static void create_pcie_irq_map(const VirtMachineState *vms,
1068                                 uint32_t gic_phandle,
1069                                 int first_irq, const char *nodename)
1070 {
1071     int devfn, pin;
1072     uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1073     uint32_t *irq_map = full_irq_map;
1074 
1075     for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1076         for (pin = 0; pin < 4; pin++) {
1077             int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1078             int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1079             int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1080             int i;
1081 
1082             uint32_t map[] = {
1083                 devfn << 8, 0, 0,                           /* devfn */
1084                 pin + 1,                                    /* PCI pin */
1085                 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1086 
1087             /* Convert map to big endian */
1088             for (i = 0; i < 10; i++) {
1089                 irq_map[i] = cpu_to_be32(map[i]);
1090             }
1091             irq_map += 10;
1092         }
1093     }
1094 
1095     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1096                      full_irq_map, sizeof(full_irq_map));
1097 
1098     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1099                            0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1100                            0x7           /* PCI irq */);
1101 }
1102 
1103 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1104                         PCIBus *bus)
1105 {
1106     char *node;
1107     const char compat[] = "arm,smmu-v3";
1108     int irq =  vms->irqmap[VIRT_SMMU];
1109     int i;
1110     hwaddr base = vms->memmap[VIRT_SMMU].base;
1111     hwaddr size = vms->memmap[VIRT_SMMU].size;
1112     const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1113     DeviceState *dev;
1114 
1115     if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1116         return;
1117     }
1118 
1119     dev = qdev_create(NULL, "arm-smmuv3");
1120 
1121     object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1122                              &error_abort);
1123     qdev_init_nofail(dev);
1124     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1125     for (i = 0; i < NUM_SMMU_IRQS; i++) {
1126         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1127     }
1128 
1129     node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1130     qemu_fdt_add_subnode(vms->fdt, node);
1131     qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1132     qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1133 
1134     qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1135             GIC_FDT_IRQ_TYPE_SPI, irq    , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1136             GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1137             GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1138             GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1139 
1140     qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1141                      sizeof(irq_names));
1142 
1143     qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1144     qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1145     qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1146 
1147     qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1148 
1149     qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1150     g_free(node);
1151 }
1152 
1153 static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1154 {
1155     hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1156     hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1157     hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1158     hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1159     hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1160     hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1161     hwaddr base_ecam, size_ecam;
1162     hwaddr base = base_mmio;
1163     int nr_pcie_buses;
1164     int irq = vms->irqmap[VIRT_PCIE];
1165     MemoryRegion *mmio_alias;
1166     MemoryRegion *mmio_reg;
1167     MemoryRegion *ecam_alias;
1168     MemoryRegion *ecam_reg;
1169     DeviceState *dev;
1170     char *nodename;
1171     int i, ecam_id;
1172     PCIHostState *pci;
1173 
1174     dev = qdev_create(NULL, TYPE_GPEX_HOST);
1175     qdev_init_nofail(dev);
1176 
1177     ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1178     base_ecam = vms->memmap[ecam_id].base;
1179     size_ecam = vms->memmap[ecam_id].size;
1180     nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1181     /* Map only the first size_ecam bytes of ECAM space */
1182     ecam_alias = g_new0(MemoryRegion, 1);
1183     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1184     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1185                              ecam_reg, 0, size_ecam);
1186     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1187 
1188     /* Map the MMIO window into system address space so as to expose
1189      * the section of PCI MMIO space which starts at the same base address
1190      * (ie 1:1 mapping for that part of PCI MMIO space visible through
1191      * the window).
1192      */
1193     mmio_alias = g_new0(MemoryRegion, 1);
1194     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1195     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1196                              mmio_reg, base_mmio, size_mmio);
1197     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1198 
1199     if (vms->highmem) {
1200         /* Map high MMIO space */
1201         MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1202 
1203         memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1204                                  mmio_reg, base_mmio_high, size_mmio_high);
1205         memory_region_add_subregion(get_system_memory(), base_mmio_high,
1206                                     high_mmio_alias);
1207     }
1208 
1209     /* Map IO port space */
1210     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1211 
1212     for (i = 0; i < GPEX_NUM_IRQS; i++) {
1213         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1214         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1215     }
1216 
1217     pci = PCI_HOST_BRIDGE(dev);
1218     if (pci->bus) {
1219         for (i = 0; i < nb_nics; i++) {
1220             NICInfo *nd = &nd_table[i];
1221 
1222             if (!nd->model) {
1223                 nd->model = g_strdup("virtio");
1224             }
1225 
1226             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1227         }
1228     }
1229 
1230     nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1231     qemu_fdt_add_subnode(vms->fdt, nodename);
1232     qemu_fdt_setprop_string(vms->fdt, nodename,
1233                             "compatible", "pci-host-ecam-generic");
1234     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1235     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1236     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1237     qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1238     qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1239                            nr_pcie_buses - 1);
1240     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1241 
1242     if (vms->msi_phandle) {
1243         qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1244                                vms->msi_phandle);
1245     }
1246 
1247     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1248                                  2, base_ecam, 2, size_ecam);
1249 
1250     if (vms->highmem) {
1251         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1252                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1253                                      2, base_pio, 2, size_pio,
1254                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1255                                      2, base_mmio, 2, size_mmio,
1256                                      1, FDT_PCI_RANGE_MMIO_64BIT,
1257                                      2, base_mmio_high,
1258                                      2, base_mmio_high, 2, size_mmio_high);
1259     } else {
1260         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1261                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1262                                      2, base_pio, 2, size_pio,
1263                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1264                                      2, base_mmio, 2, size_mmio);
1265     }
1266 
1267     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1268     create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1269 
1270     if (vms->iommu) {
1271         vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1272 
1273         create_smmu(vms, pic, pci->bus);
1274 
1275         qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1276                                0x0, vms->iommu_phandle, 0x0, 0x10000);
1277     }
1278 
1279     g_free(nodename);
1280 }
1281 
1282 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1283 {
1284     DeviceState *dev;
1285     SysBusDevice *s;
1286     int i;
1287     MemoryRegion *sysmem = get_system_memory();
1288 
1289     dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1290     dev->id = TYPE_PLATFORM_BUS_DEVICE;
1291     qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1292     qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1293     qdev_init_nofail(dev);
1294     vms->platform_bus_dev = dev;
1295 
1296     s = SYS_BUS_DEVICE(dev);
1297     for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1298         int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1299         sysbus_connect_irq(s, i, pic[irqn]);
1300     }
1301 
1302     memory_region_add_subregion(sysmem,
1303                                 vms->memmap[VIRT_PLATFORM_BUS].base,
1304                                 sysbus_mmio_get_region(s, 0));
1305 }
1306 
1307 static void create_secure_ram(VirtMachineState *vms,
1308                               MemoryRegion *secure_sysmem)
1309 {
1310     MemoryRegion *secram = g_new(MemoryRegion, 1);
1311     char *nodename;
1312     hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1313     hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1314 
1315     memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1316                            &error_fatal);
1317     memory_region_add_subregion(secure_sysmem, base, secram);
1318 
1319     nodename = g_strdup_printf("/secram@%" PRIx64, base);
1320     qemu_fdt_add_subnode(vms->fdt, nodename);
1321     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1322     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1323     qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1324     qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1325 
1326     g_free(nodename);
1327 }
1328 
1329 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1330 {
1331     const VirtMachineState *board = container_of(binfo, VirtMachineState,
1332                                                  bootinfo);
1333 
1334     *fdt_size = board->fdt_size;
1335     return board->fdt;
1336 }
1337 
1338 static void virt_build_smbios(VirtMachineState *vms)
1339 {
1340     MachineClass *mc = MACHINE_GET_CLASS(vms);
1341     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1342     uint8_t *smbios_tables, *smbios_anchor;
1343     size_t smbios_tables_len, smbios_anchor_len;
1344     const char *product = "QEMU Virtual Machine";
1345 
1346     if (kvm_enabled()) {
1347         product = "KVM Virtual Machine";
1348     }
1349 
1350     smbios_set_defaults("QEMU", product,
1351                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1352                         true, SMBIOS_ENTRY_POINT_30);
1353 
1354     smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
1355                       &smbios_anchor, &smbios_anchor_len);
1356 
1357     if (smbios_anchor) {
1358         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1359                         smbios_tables, smbios_tables_len);
1360         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1361                         smbios_anchor, smbios_anchor_len);
1362     }
1363 }
1364 
1365 static
1366 void virt_machine_done(Notifier *notifier, void *data)
1367 {
1368     VirtMachineState *vms = container_of(notifier, VirtMachineState,
1369                                          machine_done);
1370     ARMCPU *cpu = ARM_CPU(first_cpu);
1371     struct arm_boot_info *info = &vms->bootinfo;
1372     AddressSpace *as = arm_boot_address_space(cpu, info);
1373 
1374     /*
1375      * If the user provided a dtb, we assume the dynamic sysbus nodes
1376      * already are integrated there. This corresponds to a use case where
1377      * the dynamic sysbus nodes are complex and their generation is not yet
1378      * supported. In that case the user can take charge of the guest dt
1379      * while qemu takes charge of the qom stuff.
1380      */
1381     if (info->dtb_filename == NULL) {
1382         platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1383                                        vms->memmap[VIRT_PLATFORM_BUS].base,
1384                                        vms->memmap[VIRT_PLATFORM_BUS].size,
1385                                        vms->irqmap[VIRT_PLATFORM_BUS]);
1386     }
1387     if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1388         exit(1);
1389     }
1390 
1391     virt_acpi_setup(vms);
1392     virt_build_smbios(vms);
1393 }
1394 
1395 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1396 {
1397     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1398     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1399 
1400     if (!vmc->disallow_affinity_adjustment) {
1401         /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1402          * GIC's target-list limitations. 32-bit KVM hosts currently
1403          * always create clusters of 4 CPUs, but that is expected to
1404          * change when they gain support for gicv3. When KVM is enabled
1405          * it will override the changes we make here, therefore our
1406          * purposes are to make TCG consistent (with 64-bit KVM hosts)
1407          * and to improve SGI efficiency.
1408          */
1409         if (vms->gic_version == 3) {
1410             clustersz = GICV3_TARGETLIST_BITS;
1411         } else {
1412             clustersz = GIC_TARGETLIST_BITS;
1413         }
1414     }
1415     return arm_cpu_mp_affinity(idx, clustersz);
1416 }
1417 
1418 static void virt_set_memmap(VirtMachineState *vms)
1419 {
1420     MachineState *ms = MACHINE(vms);
1421     hwaddr base, device_memory_base, device_memory_size;
1422     int i;
1423 
1424     vms->memmap = extended_memmap;
1425 
1426     for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1427         vms->memmap[i] = base_memmap[i];
1428     }
1429 
1430     if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1431         error_report("unsupported number of memory slots: %"PRIu64,
1432                      ms->ram_slots);
1433         exit(EXIT_FAILURE);
1434     }
1435 
1436     /*
1437      * We compute the base of the high IO region depending on the
1438      * amount of initial and device memory. The device memory start/size
1439      * is aligned on 1GiB. We never put the high IO region below 256GiB
1440      * so that if maxram_size is < 255GiB we keep the legacy memory map.
1441      * The device region size assumes 1GiB page max alignment per slot.
1442      */
1443     device_memory_base =
1444         ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1445     device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1446 
1447     /* Base address of the high IO region */
1448     base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1449     if (base < device_memory_base) {
1450         error_report("maxmem/slots too huge");
1451         exit(EXIT_FAILURE);
1452     }
1453     if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1454         base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1455     }
1456 
1457     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1458         hwaddr size = extended_memmap[i].size;
1459 
1460         base = ROUND_UP(base, size);
1461         vms->memmap[i].base = base;
1462         vms->memmap[i].size = size;
1463         base += size;
1464     }
1465     vms->highest_gpa = base - 1;
1466     if (device_memory_size > 0) {
1467         ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1468         ms->device_memory->base = device_memory_base;
1469         memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1470                            "device-memory", device_memory_size);
1471     }
1472 }
1473 
1474 static void machvirt_init(MachineState *machine)
1475 {
1476     VirtMachineState *vms = VIRT_MACHINE(machine);
1477     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1478     MachineClass *mc = MACHINE_GET_CLASS(machine);
1479     const CPUArchIdList *possible_cpus;
1480     qemu_irq pic[NUM_IRQS];
1481     MemoryRegion *sysmem = get_system_memory();
1482     MemoryRegion *secure_sysmem = NULL;
1483     int n, virt_max_cpus;
1484     MemoryRegion *ram = g_new(MemoryRegion, 1);
1485     bool firmware_loaded;
1486     bool aarch64 = true;
1487     unsigned int smp_cpus = machine->smp.cpus;
1488     unsigned int max_cpus = machine->smp.max_cpus;
1489 
1490     /*
1491      * In accelerated mode, the memory map is computed earlier in kvm_type()
1492      * to create a VM with the right number of IPA bits.
1493      */
1494     if (!vms->memmap) {
1495         virt_set_memmap(vms);
1496     }
1497 
1498     /* We can probe only here because during property set
1499      * KVM is not available yet
1500      */
1501     if (vms->gic_version <= 0) {
1502         /* "host" or "max" */
1503         if (!kvm_enabled()) {
1504             if (vms->gic_version == 0) {
1505                 error_report("gic-version=host requires KVM");
1506                 exit(1);
1507             } else {
1508                 /* "max": currently means 3 for TCG */
1509                 vms->gic_version = 3;
1510             }
1511         } else {
1512             vms->gic_version = kvm_arm_vgic_probe();
1513             if (!vms->gic_version) {
1514                 error_report(
1515                     "Unable to determine GIC version supported by host");
1516                 exit(1);
1517             }
1518         }
1519     }
1520 
1521     if (!cpu_type_valid(machine->cpu_type)) {
1522         error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1523         exit(1);
1524     }
1525 
1526     if (vms->secure) {
1527         if (kvm_enabled()) {
1528             error_report("mach-virt: KVM does not support Security extensions");
1529             exit(1);
1530         }
1531 
1532         /*
1533          * The Secure view of the world is the same as the NonSecure,
1534          * but with a few extra devices. Create it as a container region
1535          * containing the system memory at low priority; any secure-only
1536          * devices go in at higher priority and take precedence.
1537          */
1538         secure_sysmem = g_new(MemoryRegion, 1);
1539         memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1540                            UINT64_MAX);
1541         memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1542     }
1543 
1544     firmware_loaded = virt_firmware_init(vms, sysmem,
1545                                          secure_sysmem ?: sysmem);
1546 
1547     /* If we have an EL3 boot ROM then the assumption is that it will
1548      * implement PSCI itself, so disable QEMU's internal implementation
1549      * so it doesn't get in the way. Instead of starting secondary
1550      * CPUs in PSCI powerdown state we will start them all running and
1551      * let the boot ROM sort them out.
1552      * The usual case is that we do use QEMU's PSCI implementation;
1553      * if the guest has EL2 then we will use SMC as the conduit,
1554      * and otherwise we will use HVC (for backwards compatibility and
1555      * because if we're using KVM then we must use HVC).
1556      */
1557     if (vms->secure && firmware_loaded) {
1558         vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1559     } else if (vms->virt) {
1560         vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1561     } else {
1562         vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1563     }
1564 
1565     /* The maximum number of CPUs depends on the GIC version, or on how
1566      * many redistributors we can fit into the memory map.
1567      */
1568     if (vms->gic_version == 3) {
1569         virt_max_cpus =
1570             vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1571         virt_max_cpus +=
1572             vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1573     } else {
1574         virt_max_cpus = GIC_NCPU;
1575     }
1576 
1577     if (max_cpus > virt_max_cpus) {
1578         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1579                      "supported by machine 'mach-virt' (%d)",
1580                      max_cpus, virt_max_cpus);
1581         exit(1);
1582     }
1583 
1584     vms->smp_cpus = smp_cpus;
1585 
1586     if (vms->virt && kvm_enabled()) {
1587         error_report("mach-virt: KVM does not support providing "
1588                      "Virtualization extensions to the guest CPU");
1589         exit(1);
1590     }
1591 
1592     create_fdt(vms);
1593 
1594     possible_cpus = mc->possible_cpu_arch_ids(machine);
1595     for (n = 0; n < possible_cpus->len; n++) {
1596         Object *cpuobj;
1597         CPUState *cs;
1598 
1599         if (n >= smp_cpus) {
1600             break;
1601         }
1602 
1603         cpuobj = object_new(possible_cpus->cpus[n].type);
1604         object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1605                                 "mp-affinity", NULL);
1606 
1607         cs = CPU(cpuobj);
1608         cs->cpu_index = n;
1609 
1610         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1611                           &error_fatal);
1612 
1613         aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1614 
1615         if (!vms->secure) {
1616             object_property_set_bool(cpuobj, false, "has_el3", NULL);
1617         }
1618 
1619         if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1620             object_property_set_bool(cpuobj, false, "has_el2", NULL);
1621         }
1622 
1623         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1624             object_property_set_int(cpuobj, vms->psci_conduit,
1625                                     "psci-conduit", NULL);
1626 
1627             /* Secondary CPUs start in PSCI powered-down state */
1628             if (n > 0) {
1629                 object_property_set_bool(cpuobj, true,
1630                                          "start-powered-off", NULL);
1631             }
1632         }
1633 
1634         if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1635             object_property_set_bool(cpuobj, false, "pmu", NULL);
1636         }
1637 
1638         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1639             object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1640                                     "reset-cbar", &error_abort);
1641         }
1642 
1643         object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1644                                  &error_abort);
1645         if (vms->secure) {
1646             object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1647                                      "secure-memory", &error_abort);
1648         }
1649 
1650         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1651         object_unref(cpuobj);
1652     }
1653     fdt_add_timer_nodes(vms);
1654     fdt_add_cpu_nodes(vms);
1655 
1656    if (!kvm_enabled()) {
1657         ARMCPU *cpu = ARM_CPU(first_cpu);
1658         bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1659 
1660         if (aarch64 && vms->highmem) {
1661             int requested_pa_size, pamax = arm_pamax(cpu);
1662 
1663             requested_pa_size = 64 - clz64(vms->highest_gpa);
1664             if (pamax < requested_pa_size) {
1665                 error_report("VCPU supports less PA bits (%d) than requested "
1666                             "by the memory map (%d)", pamax, requested_pa_size);
1667                 exit(1);
1668             }
1669         }
1670     }
1671 
1672     memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1673                                          machine->ram_size);
1674     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1675     if (machine->device_memory) {
1676         memory_region_add_subregion(sysmem, machine->device_memory->base,
1677                                     &machine->device_memory->mr);
1678     }
1679 
1680     virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
1681 
1682     create_gic(vms, pic);
1683 
1684     fdt_add_pmu_nodes(vms);
1685 
1686     create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1687 
1688     if (vms->secure) {
1689         create_secure_ram(vms, secure_sysmem);
1690         create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1691     }
1692 
1693     vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1694 
1695     create_rtc(vms, pic);
1696 
1697     create_pcie(vms, pic);
1698 
1699     create_gpio(vms, pic);
1700 
1701     /* Create mmio transports, so the user can create virtio backends
1702      * (which will be automatically plugged in to the transports). If
1703      * no backend is created the transport will just sit harmlessly idle.
1704      */
1705     create_virtio_devices(vms, pic);
1706 
1707     vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1708     rom_set_fw(vms->fw_cfg);
1709 
1710     create_platform_bus(vms, pic);
1711 
1712     vms->bootinfo.ram_size = machine->ram_size;
1713     vms->bootinfo.kernel_filename = machine->kernel_filename;
1714     vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1715     vms->bootinfo.initrd_filename = machine->initrd_filename;
1716     vms->bootinfo.nb_cpus = smp_cpus;
1717     vms->bootinfo.board_id = -1;
1718     vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1719     vms->bootinfo.get_dtb = machvirt_dtb;
1720     vms->bootinfo.skip_dtb_autoload = true;
1721     vms->bootinfo.firmware_loaded = firmware_loaded;
1722     arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1723 
1724     vms->machine_done.notify = virt_machine_done;
1725     qemu_add_machine_init_done_notifier(&vms->machine_done);
1726 }
1727 
1728 static bool virt_get_secure(Object *obj, Error **errp)
1729 {
1730     VirtMachineState *vms = VIRT_MACHINE(obj);
1731 
1732     return vms->secure;
1733 }
1734 
1735 static void virt_set_secure(Object *obj, bool value, Error **errp)
1736 {
1737     VirtMachineState *vms = VIRT_MACHINE(obj);
1738 
1739     vms->secure = value;
1740 }
1741 
1742 static bool virt_get_virt(Object *obj, Error **errp)
1743 {
1744     VirtMachineState *vms = VIRT_MACHINE(obj);
1745 
1746     return vms->virt;
1747 }
1748 
1749 static void virt_set_virt(Object *obj, bool value, Error **errp)
1750 {
1751     VirtMachineState *vms = VIRT_MACHINE(obj);
1752 
1753     vms->virt = value;
1754 }
1755 
1756 static bool virt_get_highmem(Object *obj, Error **errp)
1757 {
1758     VirtMachineState *vms = VIRT_MACHINE(obj);
1759 
1760     return vms->highmem;
1761 }
1762 
1763 static void virt_set_highmem(Object *obj, bool value, Error **errp)
1764 {
1765     VirtMachineState *vms = VIRT_MACHINE(obj);
1766 
1767     vms->highmem = value;
1768 }
1769 
1770 static bool virt_get_its(Object *obj, Error **errp)
1771 {
1772     VirtMachineState *vms = VIRT_MACHINE(obj);
1773 
1774     return vms->its;
1775 }
1776 
1777 static void virt_set_its(Object *obj, bool value, Error **errp)
1778 {
1779     VirtMachineState *vms = VIRT_MACHINE(obj);
1780 
1781     vms->its = value;
1782 }
1783 
1784 static char *virt_get_gic_version(Object *obj, Error **errp)
1785 {
1786     VirtMachineState *vms = VIRT_MACHINE(obj);
1787     const char *val = vms->gic_version == 3 ? "3" : "2";
1788 
1789     return g_strdup(val);
1790 }
1791 
1792 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1793 {
1794     VirtMachineState *vms = VIRT_MACHINE(obj);
1795 
1796     if (!strcmp(value, "3")) {
1797         vms->gic_version = 3;
1798     } else if (!strcmp(value, "2")) {
1799         vms->gic_version = 2;
1800     } else if (!strcmp(value, "host")) {
1801         vms->gic_version = 0; /* Will probe later */
1802     } else if (!strcmp(value, "max")) {
1803         vms->gic_version = -1; /* Will probe later */
1804     } else {
1805         error_setg(errp, "Invalid gic-version value");
1806         error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1807     }
1808 }
1809 
1810 static char *virt_get_iommu(Object *obj, Error **errp)
1811 {
1812     VirtMachineState *vms = VIRT_MACHINE(obj);
1813 
1814     switch (vms->iommu) {
1815     case VIRT_IOMMU_NONE:
1816         return g_strdup("none");
1817     case VIRT_IOMMU_SMMUV3:
1818         return g_strdup("smmuv3");
1819     default:
1820         g_assert_not_reached();
1821     }
1822 }
1823 
1824 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1825 {
1826     VirtMachineState *vms = VIRT_MACHINE(obj);
1827 
1828     if (!strcmp(value, "smmuv3")) {
1829         vms->iommu = VIRT_IOMMU_SMMUV3;
1830     } else if (!strcmp(value, "none")) {
1831         vms->iommu = VIRT_IOMMU_NONE;
1832     } else {
1833         error_setg(errp, "Invalid iommu value");
1834         error_append_hint(errp, "Valid values are none, smmuv3.\n");
1835     }
1836 }
1837 
1838 static CpuInstanceProperties
1839 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1840 {
1841     MachineClass *mc = MACHINE_GET_CLASS(ms);
1842     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1843 
1844     assert(cpu_index < possible_cpus->len);
1845     return possible_cpus->cpus[cpu_index].props;
1846 }
1847 
1848 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1849 {
1850     return idx % nb_numa_nodes;
1851 }
1852 
1853 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1854 {
1855     int n;
1856     unsigned int max_cpus = ms->smp.max_cpus;
1857     VirtMachineState *vms = VIRT_MACHINE(ms);
1858 
1859     if (ms->possible_cpus) {
1860         assert(ms->possible_cpus->len == max_cpus);
1861         return ms->possible_cpus;
1862     }
1863 
1864     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1865                                   sizeof(CPUArchId) * max_cpus);
1866     ms->possible_cpus->len = max_cpus;
1867     for (n = 0; n < ms->possible_cpus->len; n++) {
1868         ms->possible_cpus->cpus[n].type = ms->cpu_type;
1869         ms->possible_cpus->cpus[n].arch_id =
1870             virt_cpu_mp_affinity(vms, n);
1871         ms->possible_cpus->cpus[n].props.has_thread_id = true;
1872         ms->possible_cpus->cpus[n].props.thread_id = n;
1873     }
1874     return ms->possible_cpus;
1875 }
1876 
1877 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1878                                         DeviceState *dev, Error **errp)
1879 {
1880     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1881 
1882     if (vms->platform_bus_dev) {
1883         if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1884             platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1885                                      SYS_BUS_DEVICE(dev));
1886         }
1887     }
1888 }
1889 
1890 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1891                                                         DeviceState *dev)
1892 {
1893     if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1894         return HOTPLUG_HANDLER(machine);
1895     }
1896 
1897     return NULL;
1898 }
1899 
1900 /*
1901  * for arm64 kvm_type [7-0] encodes the requested number of bits
1902  * in the IPA address space
1903  */
1904 static int virt_kvm_type(MachineState *ms, const char *type_str)
1905 {
1906     VirtMachineState *vms = VIRT_MACHINE(ms);
1907     int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
1908     int requested_pa_size;
1909 
1910     /* we freeze the memory map to compute the highest gpa */
1911     virt_set_memmap(vms);
1912 
1913     requested_pa_size = 64 - clz64(vms->highest_gpa);
1914 
1915     if (requested_pa_size > max_vm_pa_size) {
1916         error_report("-m and ,maxmem option values "
1917                      "require an IPA range (%d bits) larger than "
1918                      "the one supported by the host (%d bits)",
1919                      requested_pa_size, max_vm_pa_size);
1920        exit(1);
1921     }
1922     /*
1923      * By default we return 0 which corresponds to an implicit legacy
1924      * 40b IPA setting. Otherwise we return the actual requested PA
1925      * logsize
1926      */
1927     return requested_pa_size > 40 ? requested_pa_size : 0;
1928 }
1929 
1930 static void virt_machine_class_init(ObjectClass *oc, void *data)
1931 {
1932     MachineClass *mc = MACHINE_CLASS(oc);
1933     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1934 
1935     mc->init = machvirt_init;
1936     /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1937      * The value may be reduced later when we have more information about the
1938      * configuration of the particular instance.
1939      */
1940     mc->max_cpus = 512;
1941     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1942     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1943     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1944     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
1945     mc->block_default_type = IF_VIRTIO;
1946     mc->no_cdrom = 1;
1947     mc->pci_allow_0_address = true;
1948     /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1949     mc->minimum_page_bits = 12;
1950     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1951     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1952     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1953     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1954     mc->kvm_type = virt_kvm_type;
1955     assert(!mc->get_hotplug_handler);
1956     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1957     hc->plug = virt_machine_device_plug_cb;
1958     mc->numa_mem_supported = true;
1959 }
1960 
1961 static void virt_instance_init(Object *obj)
1962 {
1963     VirtMachineState *vms = VIRT_MACHINE(obj);
1964     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1965 
1966     /* EL3 is disabled by default on virt: this makes us consistent
1967      * between KVM and TCG for this board, and it also allows us to
1968      * boot UEFI blobs which assume no TrustZone support.
1969      */
1970     vms->secure = false;
1971     object_property_add_bool(obj, "secure", virt_get_secure,
1972                              virt_set_secure, NULL);
1973     object_property_set_description(obj, "secure",
1974                                     "Set on/off to enable/disable the ARM "
1975                                     "Security Extensions (TrustZone)",
1976                                     NULL);
1977 
1978     /* EL2 is also disabled by default, for similar reasons */
1979     vms->virt = false;
1980     object_property_add_bool(obj, "virtualization", virt_get_virt,
1981                              virt_set_virt, NULL);
1982     object_property_set_description(obj, "virtualization",
1983                                     "Set on/off to enable/disable emulating a "
1984                                     "guest CPU which implements the ARM "
1985                                     "Virtualization Extensions",
1986                                     NULL);
1987 
1988     /* High memory is enabled by default */
1989     vms->highmem = true;
1990     object_property_add_bool(obj, "highmem", virt_get_highmem,
1991                              virt_set_highmem, NULL);
1992     object_property_set_description(obj, "highmem",
1993                                     "Set on/off to enable/disable using "
1994                                     "physical address space above 32 bits",
1995                                     NULL);
1996     /* Default GIC type is v2 */
1997     vms->gic_version = 2;
1998     object_property_add_str(obj, "gic-version", virt_get_gic_version,
1999                         virt_set_gic_version, NULL);
2000     object_property_set_description(obj, "gic-version",
2001                                     "Set GIC version. "
2002                                     "Valid values are 2, 3 and host", NULL);
2003 
2004     vms->highmem_ecam = !vmc->no_highmem_ecam;
2005 
2006     if (vmc->no_its) {
2007         vms->its = false;
2008     } else {
2009         /* Default allows ITS instantiation */
2010         vms->its = true;
2011         object_property_add_bool(obj, "its", virt_get_its,
2012                                  virt_set_its, NULL);
2013         object_property_set_description(obj, "its",
2014                                         "Set on/off to enable/disable "
2015                                         "ITS instantiation",
2016                                         NULL);
2017     }
2018 
2019     /* Default disallows iommu instantiation */
2020     vms->iommu = VIRT_IOMMU_NONE;
2021     object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
2022     object_property_set_description(obj, "iommu",
2023                                     "Set the IOMMU type. "
2024                                     "Valid values are none and smmuv3",
2025                                     NULL);
2026 
2027     vms->irqmap = a15irqmap;
2028 
2029     virt_flash_create(vms);
2030 }
2031 
2032 static const TypeInfo virt_machine_info = {
2033     .name          = TYPE_VIRT_MACHINE,
2034     .parent        = TYPE_MACHINE,
2035     .abstract      = true,
2036     .instance_size = sizeof(VirtMachineState),
2037     .class_size    = sizeof(VirtMachineClass),
2038     .class_init    = virt_machine_class_init,
2039     .instance_init = virt_instance_init,
2040     .interfaces = (InterfaceInfo[]) {
2041          { TYPE_HOTPLUG_HANDLER },
2042          { }
2043     },
2044 };
2045 
2046 static void machvirt_machine_init(void)
2047 {
2048     type_register_static(&virt_machine_info);
2049 }
2050 type_init(machvirt_machine_init);
2051 
2052 static void virt_machine_4_1_options(MachineClass *mc)
2053 {
2054 }
2055 DEFINE_VIRT_MACHINE_AS_LATEST(4, 1)
2056 
2057 static void virt_machine_4_0_options(MachineClass *mc)
2058 {
2059     virt_machine_4_1_options(mc);
2060     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2061 }
2062 DEFINE_VIRT_MACHINE(4, 0)
2063 
2064 static void virt_machine_3_1_options(MachineClass *mc)
2065 {
2066     virt_machine_4_0_options(mc);
2067     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2068 }
2069 DEFINE_VIRT_MACHINE(3, 1)
2070 
2071 static void virt_machine_3_0_options(MachineClass *mc)
2072 {
2073     virt_machine_3_1_options(mc);
2074     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2075 }
2076 DEFINE_VIRT_MACHINE(3, 0)
2077 
2078 static void virt_machine_2_12_options(MachineClass *mc)
2079 {
2080     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2081 
2082     virt_machine_3_0_options(mc);
2083     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2084     vmc->no_highmem_ecam = true;
2085     mc->max_cpus = 255;
2086 }
2087 DEFINE_VIRT_MACHINE(2, 12)
2088 
2089 static void virt_machine_2_11_options(MachineClass *mc)
2090 {
2091     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2092 
2093     virt_machine_2_12_options(mc);
2094     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2095     vmc->smbios_old_sys_ver = true;
2096 }
2097 DEFINE_VIRT_MACHINE(2, 11)
2098 
2099 static void virt_machine_2_10_options(MachineClass *mc)
2100 {
2101     virt_machine_2_11_options(mc);
2102     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2103     /* before 2.11 we never faulted accesses to bad addresses */
2104     mc->ignore_memory_transaction_failures = true;
2105 }
2106 DEFINE_VIRT_MACHINE(2, 10)
2107 
2108 static void virt_machine_2_9_options(MachineClass *mc)
2109 {
2110     virt_machine_2_10_options(mc);
2111     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2112 }
2113 DEFINE_VIRT_MACHINE(2, 9)
2114 
2115 static void virt_machine_2_8_options(MachineClass *mc)
2116 {
2117     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2118 
2119     virt_machine_2_9_options(mc);
2120     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2121     /* For 2.8 and earlier we falsely claimed in the DT that
2122      * our timers were edge-triggered, not level-triggered.
2123      */
2124     vmc->claim_edge_triggered_timers = true;
2125 }
2126 DEFINE_VIRT_MACHINE(2, 8)
2127 
2128 static void virt_machine_2_7_options(MachineClass *mc)
2129 {
2130     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2131 
2132     virt_machine_2_8_options(mc);
2133     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2134     /* ITS was introduced with 2.8 */
2135     vmc->no_its = true;
2136     /* Stick with 1K pages for migration compatibility */
2137     mc->minimum_page_bits = 0;
2138 }
2139 DEFINE_VIRT_MACHINE(2, 7)
2140 
2141 static void virt_machine_2_6_options(MachineClass *mc)
2142 {
2143     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2144 
2145     virt_machine_2_7_options(mc);
2146     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2147     vmc->disallow_affinity_adjustment = true;
2148     /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2149     vmc->no_pmu = true;
2150 }
2151 DEFINE_VIRT_MACHINE(2, 6)
2152