1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/vfio/vfio-calxeda-xgmac.h" 38 #include "hw/vfio/vfio-amd-xgbe.h" 39 #include "hw/display/ramfb.h" 40 #include "hw/devices.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/numa.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "hw/compat.h" 47 #include "hw/loader.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/bitops.h" 50 #include "qemu/error-report.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 #include "hw/arm/smmuv3.h" 62 63 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 64 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 65 void *data) \ 66 { \ 67 MachineClass *mc = MACHINE_CLASS(oc); \ 68 virt_machine_##major##_##minor##_options(mc); \ 69 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 70 if (latest) { \ 71 mc->alias = "virt"; \ 72 } \ 73 } \ 74 static const TypeInfo machvirt_##major##_##minor##_info = { \ 75 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 76 .parent = TYPE_VIRT_MACHINE, \ 77 .instance_init = virt_##major##_##minor##_instance_init, \ 78 .class_init = virt_##major##_##minor##_class_init, \ 79 }; \ 80 static void machvirt_machine_##major##_##minor##_init(void) \ 81 { \ 82 type_register_static(&machvirt_##major##_##minor##_info); \ 83 } \ 84 type_init(machvirt_machine_##major##_##minor##_init); 85 86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 87 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 88 #define DEFINE_VIRT_MACHINE(major, minor) \ 89 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 90 91 92 /* Number of external interrupt lines to configure the GIC with */ 93 #define NUM_IRQS 256 94 95 #define PLATFORM_BUS_NUM_IRQS 64 96 97 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 98 * RAM can go up to the 256GB mark, leaving 256GB of the physical 99 * address space unallocated and free for future use between 256G and 512G. 100 * If we need to provide more RAM to VMs in the future then we need to: 101 * * allocate a second bank of RAM starting at 2TB and working up 102 * * fix the DT and ACPI table generation code in QEMU to correctly 103 * report two split lumps of RAM to the guest 104 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 105 * (We don't want to fill all the way up to 512GB with RAM because 106 * we might want it for non-RAM purposes later. Conversely it seems 107 * reasonable to assume that anybody configuring a VM with a quarter 108 * of a terabyte of RAM will be doing it on a host with more than a 109 * terabyte of physical address space.) 110 */ 111 #define RAMLIMIT_GB 255 112 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 113 114 /* Addresses and sizes of our components. 115 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 116 * 128MB..256MB is used for miscellaneous device I/O. 117 * 256MB..1GB is reserved for possible future PCI support (ie where the 118 * PCI memory window will go if we add a PCI host controller). 119 * 1GB and up is RAM (which may happily spill over into the 120 * high memory region beyond 4GB). 121 * This represents a compromise between how much RAM can be given to 122 * a 32 bit VM and leaving space for expansion and in particular for PCI. 123 * Note that devices should generally be placed at multiples of 0x10000, 124 * to accommodate guests using 64K pages. 125 */ 126 static const MemMapEntry a15memmap[] = { 127 /* Space up to 0x8000000 is reserved for a boot ROM */ 128 [VIRT_FLASH] = { 0, 0x08000000 }, 129 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 130 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 131 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 132 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 133 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 134 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 135 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 136 /* This redistributor space allows up to 2*64kB*123 CPUs */ 137 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 138 [VIRT_UART] = { 0x09000000, 0x00001000 }, 139 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 140 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 141 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 142 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 143 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 144 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 146 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 147 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 148 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 149 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 150 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 151 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 152 /* Second PCIe window, 512GB wide at the 512GB boundary */ 153 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 154 }; 155 156 static const int a15irqmap[] = { 157 [VIRT_UART] = 1, 158 [VIRT_RTC] = 2, 159 [VIRT_PCIE] = 3, /* ... to 6 */ 160 [VIRT_GPIO] = 7, 161 [VIRT_SECURE_UART] = 8, 162 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 163 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 164 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 165 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 166 }; 167 168 static const char *valid_cpus[] = { 169 ARM_CPU_TYPE_NAME("cortex-a15"), 170 ARM_CPU_TYPE_NAME("cortex-a53"), 171 ARM_CPU_TYPE_NAME("cortex-a57"), 172 ARM_CPU_TYPE_NAME("host"), 173 ARM_CPU_TYPE_NAME("max"), 174 }; 175 176 static bool cpu_type_valid(const char *cpu) 177 { 178 int i; 179 180 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 181 if (strcmp(cpu, valid_cpus[i]) == 0) { 182 return true; 183 } 184 } 185 return false; 186 } 187 188 static void create_fdt(VirtMachineState *vms) 189 { 190 void *fdt = create_device_tree(&vms->fdt_size); 191 192 if (!fdt) { 193 error_report("create_device_tree() failed"); 194 exit(1); 195 } 196 197 vms->fdt = fdt; 198 199 /* Header */ 200 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 201 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 202 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 203 204 /* 205 * /chosen and /memory nodes must exist for load_dtb 206 * to fill in necessary properties later 207 */ 208 qemu_fdt_add_subnode(fdt, "/chosen"); 209 qemu_fdt_add_subnode(fdt, "/memory"); 210 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 211 212 /* Clock node, for the benefit of the UART. The kernel device tree 213 * binding documentation claims the PL011 node clock properties are 214 * optional but in practice if you omit them the kernel refuses to 215 * probe for the device. 216 */ 217 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 218 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 219 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 221 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 222 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 223 "clk24mhz"); 224 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 225 226 if (have_numa_distance) { 227 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 228 uint32_t *matrix = g_malloc0(size); 229 int idx, i, j; 230 231 for (i = 0; i < nb_numa_nodes; i++) { 232 for (j = 0; j < nb_numa_nodes; j++) { 233 idx = (i * nb_numa_nodes + j) * 3; 234 matrix[idx + 0] = cpu_to_be32(i); 235 matrix[idx + 1] = cpu_to_be32(j); 236 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 237 } 238 } 239 240 qemu_fdt_add_subnode(fdt, "/distance-map"); 241 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 242 "numa-distance-map-v1"); 243 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 244 matrix, size); 245 g_free(matrix); 246 } 247 } 248 249 static void fdt_add_timer_nodes(const VirtMachineState *vms) 250 { 251 /* On real hardware these interrupts are level-triggered. 252 * On KVM they were edge-triggered before host kernel version 4.4, 253 * and level-triggered afterwards. 254 * On emulated QEMU they are level-triggered. 255 * 256 * Getting the DTB info about them wrong is awkward for some 257 * guest kernels: 258 * pre-4.8 ignore the DT and leave the interrupt configured 259 * with whatever the GIC reset value (or the bootloader) left it at 260 * 4.8 before rc6 honour the incorrect data by programming it back 261 * into the GIC, causing problems 262 * 4.8rc6 and later ignore the DT and always write "level triggered" 263 * into the GIC 264 * 265 * For backwards-compatibility, virt-2.8 and earlier will continue 266 * to say these are edge-triggered, but later machines will report 267 * the correct information. 268 */ 269 ARMCPU *armcpu; 270 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 271 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 272 273 if (vmc->claim_edge_triggered_timers) { 274 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 275 } 276 277 if (vms->gic_version == 2) { 278 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 279 GIC_FDT_IRQ_PPI_CPU_WIDTH, 280 (1 << vms->smp_cpus) - 1); 281 } 282 283 qemu_fdt_add_subnode(vms->fdt, "/timer"); 284 285 armcpu = ARM_CPU(qemu_get_cpu(0)); 286 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 287 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 288 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 289 compat, sizeof(compat)); 290 } else { 291 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 292 "arm,armv7-timer"); 293 } 294 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 295 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 296 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 298 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 299 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 300 } 301 302 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 303 { 304 int cpu; 305 int addr_cells = 1; 306 const MachineState *ms = MACHINE(vms); 307 308 /* 309 * From Documentation/devicetree/bindings/arm/cpus.txt 310 * On ARM v8 64-bit systems value should be set to 2, 311 * that corresponds to the MPIDR_EL1 register size. 312 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 313 * in the system, #address-cells can be set to 1, since 314 * MPIDR_EL1[63:32] bits are not used for CPUs 315 * identification. 316 * 317 * Here we actually don't know whether our system is 32- or 64-bit one. 318 * The simplest way to go is to examine affinity IDs of all our CPUs. If 319 * at least one of them has Aff3 populated, we set #address-cells to 2. 320 */ 321 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 322 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 323 324 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 325 addr_cells = 2; 326 break; 327 } 328 } 329 330 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 331 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 332 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 333 334 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 335 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 336 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 337 CPUState *cs = CPU(armcpu); 338 339 qemu_fdt_add_subnode(vms->fdt, nodename); 340 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 341 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 342 armcpu->dtb_compatible); 343 344 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 345 && vms->smp_cpus > 1) { 346 qemu_fdt_setprop_string(vms->fdt, nodename, 347 "enable-method", "psci"); 348 } 349 350 if (addr_cells == 2) { 351 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 352 armcpu->mp_affinity); 353 } else { 354 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 355 armcpu->mp_affinity); 356 } 357 358 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 359 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 360 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 361 } 362 363 g_free(nodename); 364 } 365 } 366 367 static void fdt_add_its_gic_node(VirtMachineState *vms) 368 { 369 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 370 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 371 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 372 "arm,gic-v3-its"); 373 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 374 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 375 2, vms->memmap[VIRT_GIC_ITS].base, 376 2, vms->memmap[VIRT_GIC_ITS].size); 377 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 378 } 379 380 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 381 { 382 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 383 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 384 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 385 "arm,gic-v2m-frame"); 386 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 387 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 388 2, vms->memmap[VIRT_GIC_V2M].base, 389 2, vms->memmap[VIRT_GIC_V2M].size); 390 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 391 } 392 393 static void fdt_add_gic_node(VirtMachineState *vms) 394 { 395 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 396 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 397 398 qemu_fdt_add_subnode(vms->fdt, "/intc"); 399 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 400 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 401 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 402 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 403 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 404 if (vms->gic_version == 3) { 405 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 406 "arm,gic-v3"); 407 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 408 2, vms->memmap[VIRT_GIC_DIST].base, 409 2, vms->memmap[VIRT_GIC_DIST].size, 410 2, vms->memmap[VIRT_GIC_REDIST].base, 411 2, vms->memmap[VIRT_GIC_REDIST].size); 412 if (vms->virt) { 413 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 414 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 415 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 416 } 417 } else { 418 /* 'cortex-a15-gic' means 'GIC v2' */ 419 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 420 "arm,cortex-a15-gic"); 421 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 422 2, vms->memmap[VIRT_GIC_DIST].base, 423 2, vms->memmap[VIRT_GIC_DIST].size, 424 2, vms->memmap[VIRT_GIC_CPU].base, 425 2, vms->memmap[VIRT_GIC_CPU].size); 426 } 427 428 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 429 } 430 431 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 432 { 433 CPUState *cpu; 434 ARMCPU *armcpu; 435 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 436 437 CPU_FOREACH(cpu) { 438 armcpu = ARM_CPU(cpu); 439 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 440 return; 441 } 442 if (kvm_enabled()) { 443 if (kvm_irqchip_in_kernel()) { 444 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 445 } 446 kvm_arm_pmu_init(cpu); 447 } 448 } 449 450 if (vms->gic_version == 2) { 451 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 452 GIC_FDT_IRQ_PPI_CPU_WIDTH, 453 (1 << vms->smp_cpus) - 1); 454 } 455 456 armcpu = ARM_CPU(qemu_get_cpu(0)); 457 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 458 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 459 const char compat[] = "arm,armv8-pmuv3"; 460 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 461 compat, sizeof(compat)); 462 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 463 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 464 } 465 } 466 467 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 468 { 469 const char *itsclass = its_class_name(); 470 DeviceState *dev; 471 472 if (!itsclass) { 473 /* Do nothing if not supported */ 474 return; 475 } 476 477 dev = qdev_create(NULL, itsclass); 478 479 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 480 &error_abort); 481 qdev_init_nofail(dev); 482 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 483 484 fdt_add_its_gic_node(vms); 485 } 486 487 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 488 { 489 int i; 490 int irq = vms->irqmap[VIRT_GIC_V2M]; 491 DeviceState *dev; 492 493 dev = qdev_create(NULL, "arm-gicv2m"); 494 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 495 qdev_prop_set_uint32(dev, "base-spi", irq); 496 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 497 qdev_init_nofail(dev); 498 499 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 500 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 501 } 502 503 fdt_add_v2m_gic_node(vms); 504 } 505 506 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 507 { 508 /* We create a standalone GIC */ 509 DeviceState *gicdev; 510 SysBusDevice *gicbusdev; 511 const char *gictype; 512 int type = vms->gic_version, i; 513 514 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 515 516 gicdev = qdev_create(NULL, gictype); 517 qdev_prop_set_uint32(gicdev, "revision", type); 518 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 519 /* Note that the num-irq property counts both internal and external 520 * interrupts; there are always 32 of the former (mandated by GIC spec). 521 */ 522 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 523 if (!kvm_irqchip_in_kernel()) { 524 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 525 } 526 qdev_init_nofail(gicdev); 527 gicbusdev = SYS_BUS_DEVICE(gicdev); 528 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 529 if (type == 3) { 530 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 531 } else { 532 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 533 } 534 535 /* Wire the outputs from each CPU's generic timer and the GICv3 536 * maintenance interrupt signal to the appropriate GIC PPI inputs, 537 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 538 */ 539 for (i = 0; i < smp_cpus; i++) { 540 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 541 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 542 int irq; 543 /* Mapping from the output timer irq lines from the CPU to the 544 * GIC PPI inputs we use for the virt board. 545 */ 546 const int timer_irq[] = { 547 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 548 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 549 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 550 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 551 }; 552 553 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 554 qdev_connect_gpio_out(cpudev, irq, 555 qdev_get_gpio_in(gicdev, 556 ppibase + timer_irq[irq])); 557 } 558 559 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 560 qdev_get_gpio_in(gicdev, ppibase 561 + ARCH_GICV3_MAINT_IRQ)); 562 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 563 qdev_get_gpio_in(gicdev, ppibase 564 + VIRTUAL_PMU_IRQ)); 565 566 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 567 sysbus_connect_irq(gicbusdev, i + smp_cpus, 568 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 569 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 570 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 571 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 572 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 573 } 574 575 for (i = 0; i < NUM_IRQS; i++) { 576 pic[i] = qdev_get_gpio_in(gicdev, i); 577 } 578 579 fdt_add_gic_node(vms); 580 581 if (type == 3 && vms->its) { 582 create_its(vms, gicdev); 583 } else if (type == 2) { 584 create_v2m(vms, pic); 585 } 586 } 587 588 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 589 MemoryRegion *mem, Chardev *chr) 590 { 591 char *nodename; 592 hwaddr base = vms->memmap[uart].base; 593 hwaddr size = vms->memmap[uart].size; 594 int irq = vms->irqmap[uart]; 595 const char compat[] = "arm,pl011\0arm,primecell"; 596 const char clocknames[] = "uartclk\0apb_pclk"; 597 DeviceState *dev = qdev_create(NULL, "pl011"); 598 SysBusDevice *s = SYS_BUS_DEVICE(dev); 599 600 qdev_prop_set_chr(dev, "chardev", chr); 601 qdev_init_nofail(dev); 602 memory_region_add_subregion(mem, base, 603 sysbus_mmio_get_region(s, 0)); 604 sysbus_connect_irq(s, 0, pic[irq]); 605 606 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 607 qemu_fdt_add_subnode(vms->fdt, nodename); 608 /* Note that we can't use setprop_string because of the embedded NUL */ 609 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 610 compat, sizeof(compat)); 611 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 612 2, base, 2, size); 613 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 614 GIC_FDT_IRQ_TYPE_SPI, irq, 615 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 616 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 617 vms->clock_phandle, vms->clock_phandle); 618 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 619 clocknames, sizeof(clocknames)); 620 621 if (uart == VIRT_UART) { 622 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 623 } else { 624 /* Mark as not usable by the normal world */ 625 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 626 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 627 } 628 629 g_free(nodename); 630 } 631 632 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 633 { 634 char *nodename; 635 hwaddr base = vms->memmap[VIRT_RTC].base; 636 hwaddr size = vms->memmap[VIRT_RTC].size; 637 int irq = vms->irqmap[VIRT_RTC]; 638 const char compat[] = "arm,pl031\0arm,primecell"; 639 640 sysbus_create_simple("pl031", base, pic[irq]); 641 642 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 643 qemu_fdt_add_subnode(vms->fdt, nodename); 644 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 645 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 646 2, base, 2, size); 647 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 648 GIC_FDT_IRQ_TYPE_SPI, irq, 649 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 650 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 651 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 652 g_free(nodename); 653 } 654 655 static DeviceState *gpio_key_dev; 656 static void virt_powerdown_req(Notifier *n, void *opaque) 657 { 658 /* use gpio Pin 3 for power button event */ 659 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 660 } 661 662 static Notifier virt_system_powerdown_notifier = { 663 .notify = virt_powerdown_req 664 }; 665 666 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 667 { 668 char *nodename; 669 DeviceState *pl061_dev; 670 hwaddr base = vms->memmap[VIRT_GPIO].base; 671 hwaddr size = vms->memmap[VIRT_GPIO].size; 672 int irq = vms->irqmap[VIRT_GPIO]; 673 const char compat[] = "arm,pl061\0arm,primecell"; 674 675 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 676 677 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 678 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 679 qemu_fdt_add_subnode(vms->fdt, nodename); 680 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 681 2, base, 2, size); 682 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 683 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 684 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 685 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 686 GIC_FDT_IRQ_TYPE_SPI, irq, 687 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 688 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 689 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 690 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 691 692 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 693 qdev_get_gpio_in(pl061_dev, 3)); 694 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 695 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 696 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 697 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 698 699 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 700 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 701 "label", "GPIO Key Poweroff"); 702 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 703 KEY_POWER); 704 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 705 "gpios", phandle, 3, 0); 706 707 /* connect powerdown request */ 708 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 709 710 g_free(nodename); 711 } 712 713 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 714 { 715 int i; 716 hwaddr size = vms->memmap[VIRT_MMIO].size; 717 718 /* We create the transports in forwards order. Since qbus_realize() 719 * prepends (not appends) new child buses, the incrementing loop below will 720 * create a list of virtio-mmio buses with decreasing base addresses. 721 * 722 * When a -device option is processed from the command line, 723 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 724 * order. The upshot is that -device options in increasing command line 725 * order are mapped to virtio-mmio buses with decreasing base addresses. 726 * 727 * When this code was originally written, that arrangement ensured that the 728 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 729 * the first -device on the command line. (The end-to-end order is a 730 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 731 * guest kernel's name-to-address assignment strategy.) 732 * 733 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 734 * the message, if not necessarily the code, of commit 70161ff336. 735 * Therefore the loop now establishes the inverse of the original intent. 736 * 737 * Unfortunately, we can't counteract the kernel change by reversing the 738 * loop; it would break existing command lines. 739 * 740 * In any case, the kernel makes no guarantee about the stability of 741 * enumeration order of virtio devices (as demonstrated by it changing 742 * between kernel versions). For reliable and stable identification 743 * of disks users must use UUIDs or similar mechanisms. 744 */ 745 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 746 int irq = vms->irqmap[VIRT_MMIO] + i; 747 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 748 749 sysbus_create_simple("virtio-mmio", base, pic[irq]); 750 } 751 752 /* We add dtb nodes in reverse order so that they appear in the finished 753 * device tree lowest address first. 754 * 755 * Note that this mapping is independent of the loop above. The previous 756 * loop influences virtio device to virtio transport assignment, whereas 757 * this loop controls how virtio transports are laid out in the dtb. 758 */ 759 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 760 char *nodename; 761 int irq = vms->irqmap[VIRT_MMIO] + i; 762 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 763 764 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 765 qemu_fdt_add_subnode(vms->fdt, nodename); 766 qemu_fdt_setprop_string(vms->fdt, nodename, 767 "compatible", "virtio,mmio"); 768 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 769 2, base, 2, size); 770 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 771 GIC_FDT_IRQ_TYPE_SPI, irq, 772 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 773 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 774 g_free(nodename); 775 } 776 } 777 778 static void create_one_flash(const char *name, hwaddr flashbase, 779 hwaddr flashsize, const char *file, 780 MemoryRegion *sysmem) 781 { 782 /* Create and map a single flash device. We use the same 783 * parameters as the flash devices on the Versatile Express board. 784 */ 785 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 786 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 787 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 788 const uint64_t sectorlength = 256 * 1024; 789 790 if (dinfo) { 791 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 792 &error_abort); 793 } 794 795 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 796 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 797 qdev_prop_set_uint8(dev, "width", 4); 798 qdev_prop_set_uint8(dev, "device-width", 2); 799 qdev_prop_set_bit(dev, "big-endian", false); 800 qdev_prop_set_uint16(dev, "id0", 0x89); 801 qdev_prop_set_uint16(dev, "id1", 0x18); 802 qdev_prop_set_uint16(dev, "id2", 0x00); 803 qdev_prop_set_uint16(dev, "id3", 0x00); 804 qdev_prop_set_string(dev, "name", name); 805 qdev_init_nofail(dev); 806 807 memory_region_add_subregion(sysmem, flashbase, 808 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 809 810 if (file) { 811 char *fn; 812 int image_size; 813 814 if (drive_get(IF_PFLASH, 0, 0)) { 815 error_report("The contents of the first flash device may be " 816 "specified with -bios or with -drive if=pflash... " 817 "but you cannot use both options at once"); 818 exit(1); 819 } 820 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 821 if (!fn) { 822 error_report("Could not find ROM image '%s'", file); 823 exit(1); 824 } 825 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 826 g_free(fn); 827 if (image_size < 0) { 828 error_report("Could not load ROM image '%s'", file); 829 exit(1); 830 } 831 } 832 } 833 834 static void create_flash(const VirtMachineState *vms, 835 MemoryRegion *sysmem, 836 MemoryRegion *secure_sysmem) 837 { 838 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 839 * Any file passed via -bios goes in the first of these. 840 * sysmem is the system memory space. secure_sysmem is the secure view 841 * of the system, and the first flash device should be made visible only 842 * there. The second flash device is visible to both secure and nonsecure. 843 * If sysmem == secure_sysmem this means there is no separate Secure 844 * address space and both flash devices are generally visible. 845 */ 846 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 847 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 848 char *nodename; 849 850 create_one_flash("virt.flash0", flashbase, flashsize, 851 bios_name, secure_sysmem); 852 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 853 NULL, sysmem); 854 855 if (sysmem == secure_sysmem) { 856 /* Report both flash devices as a single node in the DT */ 857 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 858 qemu_fdt_add_subnode(vms->fdt, nodename); 859 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 860 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 861 2, flashbase, 2, flashsize, 862 2, flashbase + flashsize, 2, flashsize); 863 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 864 g_free(nodename); 865 } else { 866 /* Report the devices as separate nodes so we can mark one as 867 * only visible to the secure world. 868 */ 869 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 870 qemu_fdt_add_subnode(vms->fdt, nodename); 871 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 872 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 873 2, flashbase, 2, flashsize); 874 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 875 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 876 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 877 g_free(nodename); 878 879 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 880 qemu_fdt_add_subnode(vms->fdt, nodename); 881 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 882 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 883 2, flashbase + flashsize, 2, flashsize); 884 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 885 g_free(nodename); 886 } 887 } 888 889 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 890 { 891 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 892 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 893 FWCfgState *fw_cfg; 894 char *nodename; 895 896 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 897 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 898 899 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 900 qemu_fdt_add_subnode(vms->fdt, nodename); 901 qemu_fdt_setprop_string(vms->fdt, nodename, 902 "compatible", "qemu,fw-cfg-mmio"); 903 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 904 2, base, 2, size); 905 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 906 g_free(nodename); 907 return fw_cfg; 908 } 909 910 static void create_pcie_irq_map(const VirtMachineState *vms, 911 uint32_t gic_phandle, 912 int first_irq, const char *nodename) 913 { 914 int devfn, pin; 915 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 916 uint32_t *irq_map = full_irq_map; 917 918 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 919 for (pin = 0; pin < 4; pin++) { 920 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 921 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 922 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 923 int i; 924 925 uint32_t map[] = { 926 devfn << 8, 0, 0, /* devfn */ 927 pin + 1, /* PCI pin */ 928 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 929 930 /* Convert map to big endian */ 931 for (i = 0; i < 10; i++) { 932 irq_map[i] = cpu_to_be32(map[i]); 933 } 934 irq_map += 10; 935 } 936 } 937 938 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 939 full_irq_map, sizeof(full_irq_map)); 940 941 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 942 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 943 0x7 /* PCI irq */); 944 } 945 946 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, 947 PCIBus *bus) 948 { 949 char *node; 950 const char compat[] = "arm,smmu-v3"; 951 int irq = vms->irqmap[VIRT_SMMU]; 952 int i; 953 hwaddr base = vms->memmap[VIRT_SMMU].base; 954 hwaddr size = vms->memmap[VIRT_SMMU].size; 955 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 956 DeviceState *dev; 957 958 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 959 return; 960 } 961 962 dev = qdev_create(NULL, "arm-smmuv3"); 963 964 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 965 &error_abort); 966 qdev_init_nofail(dev); 967 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 968 for (i = 0; i < NUM_SMMU_IRQS; i++) { 969 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 970 } 971 972 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 973 qemu_fdt_add_subnode(vms->fdt, node); 974 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 975 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 976 977 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 978 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 979 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 980 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 981 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 982 983 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 984 sizeof(irq_names)); 985 986 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 987 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 988 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 989 990 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 991 992 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 993 g_free(node); 994 } 995 996 static void create_pcie(VirtMachineState *vms, qemu_irq *pic) 997 { 998 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 999 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1000 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 1001 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 1002 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1003 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1004 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 1005 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 1006 hwaddr base = base_mmio; 1007 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1008 int irq = vms->irqmap[VIRT_PCIE]; 1009 MemoryRegion *mmio_alias; 1010 MemoryRegion *mmio_reg; 1011 MemoryRegion *ecam_alias; 1012 MemoryRegion *ecam_reg; 1013 DeviceState *dev; 1014 char *nodename; 1015 int i; 1016 PCIHostState *pci; 1017 1018 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1019 qdev_init_nofail(dev); 1020 1021 /* Map only the first size_ecam bytes of ECAM space */ 1022 ecam_alias = g_new0(MemoryRegion, 1); 1023 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1024 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1025 ecam_reg, 0, size_ecam); 1026 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1027 1028 /* Map the MMIO window into system address space so as to expose 1029 * the section of PCI MMIO space which starts at the same base address 1030 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1031 * the window). 1032 */ 1033 mmio_alias = g_new0(MemoryRegion, 1); 1034 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1035 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1036 mmio_reg, base_mmio, size_mmio); 1037 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1038 1039 if (vms->highmem) { 1040 /* Map high MMIO space */ 1041 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1042 1043 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1044 mmio_reg, base_mmio_high, size_mmio_high); 1045 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1046 high_mmio_alias); 1047 } 1048 1049 /* Map IO port space */ 1050 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1051 1052 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1053 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1054 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1055 } 1056 1057 pci = PCI_HOST_BRIDGE(dev); 1058 if (pci->bus) { 1059 for (i = 0; i < nb_nics; i++) { 1060 NICInfo *nd = &nd_table[i]; 1061 1062 if (!nd->model) { 1063 nd->model = g_strdup("virtio"); 1064 } 1065 1066 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1067 } 1068 } 1069 1070 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1071 qemu_fdt_add_subnode(vms->fdt, nodename); 1072 qemu_fdt_setprop_string(vms->fdt, nodename, 1073 "compatible", "pci-host-ecam-generic"); 1074 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1075 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1076 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1077 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1078 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1079 nr_pcie_buses - 1); 1080 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1081 1082 if (vms->msi_phandle) { 1083 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1084 vms->msi_phandle); 1085 } 1086 1087 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1088 2, base_ecam, 2, size_ecam); 1089 1090 if (vms->highmem) { 1091 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1092 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1093 2, base_pio, 2, size_pio, 1094 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1095 2, base_mmio, 2, size_mmio, 1096 1, FDT_PCI_RANGE_MMIO_64BIT, 1097 2, base_mmio_high, 1098 2, base_mmio_high, 2, size_mmio_high); 1099 } else { 1100 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1101 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1102 2, base_pio, 2, size_pio, 1103 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1104 2, base_mmio, 2, size_mmio); 1105 } 1106 1107 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1108 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1109 1110 if (vms->iommu) { 1111 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1112 1113 create_smmu(vms, pic, pci->bus); 1114 1115 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1116 0x0, vms->iommu_phandle, 0x0, 0x10000); 1117 } 1118 1119 g_free(nodename); 1120 } 1121 1122 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1123 { 1124 DeviceState *dev; 1125 SysBusDevice *s; 1126 int i; 1127 MemoryRegion *sysmem = get_system_memory(); 1128 1129 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1130 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1131 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1132 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1133 qdev_init_nofail(dev); 1134 vms->platform_bus_dev = dev; 1135 1136 s = SYS_BUS_DEVICE(dev); 1137 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1138 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1139 sysbus_connect_irq(s, i, pic[irqn]); 1140 } 1141 1142 memory_region_add_subregion(sysmem, 1143 vms->memmap[VIRT_PLATFORM_BUS].base, 1144 sysbus_mmio_get_region(s, 0)); 1145 } 1146 1147 static void create_secure_ram(VirtMachineState *vms, 1148 MemoryRegion *secure_sysmem) 1149 { 1150 MemoryRegion *secram = g_new(MemoryRegion, 1); 1151 char *nodename; 1152 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1153 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1154 1155 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1156 &error_fatal); 1157 memory_region_add_subregion(secure_sysmem, base, secram); 1158 1159 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1160 qemu_fdt_add_subnode(vms->fdt, nodename); 1161 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1162 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1163 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1164 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1165 1166 g_free(nodename); 1167 } 1168 1169 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1170 { 1171 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1172 bootinfo); 1173 1174 *fdt_size = board->fdt_size; 1175 return board->fdt; 1176 } 1177 1178 static void virt_build_smbios(VirtMachineState *vms) 1179 { 1180 MachineClass *mc = MACHINE_GET_CLASS(vms); 1181 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1182 uint8_t *smbios_tables, *smbios_anchor; 1183 size_t smbios_tables_len, smbios_anchor_len; 1184 const char *product = "QEMU Virtual Machine"; 1185 1186 if (!vms->fw_cfg) { 1187 return; 1188 } 1189 1190 if (kvm_enabled()) { 1191 product = "KVM Virtual Machine"; 1192 } 1193 1194 smbios_set_defaults("QEMU", product, 1195 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1196 true, SMBIOS_ENTRY_POINT_30); 1197 1198 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1199 &smbios_anchor, &smbios_anchor_len); 1200 1201 if (smbios_anchor) { 1202 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1203 smbios_tables, smbios_tables_len); 1204 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1205 smbios_anchor, smbios_anchor_len); 1206 } 1207 } 1208 1209 static 1210 void virt_machine_done(Notifier *notifier, void *data) 1211 { 1212 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1213 machine_done); 1214 ARMCPU *cpu = ARM_CPU(first_cpu); 1215 struct arm_boot_info *info = &vms->bootinfo; 1216 AddressSpace *as = arm_boot_address_space(cpu, info); 1217 1218 /* 1219 * If the user provided a dtb, we assume the dynamic sysbus nodes 1220 * already are integrated there. This corresponds to a use case where 1221 * the dynamic sysbus nodes are complex and their generation is not yet 1222 * supported. In that case the user can take charge of the guest dt 1223 * while qemu takes charge of the qom stuff. 1224 */ 1225 if (info->dtb_filename == NULL) { 1226 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1227 vms->memmap[VIRT_PLATFORM_BUS].base, 1228 vms->memmap[VIRT_PLATFORM_BUS].size, 1229 vms->irqmap[VIRT_PLATFORM_BUS]); 1230 } 1231 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1232 exit(1); 1233 } 1234 1235 virt_acpi_setup(vms); 1236 virt_build_smbios(vms); 1237 } 1238 1239 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1240 { 1241 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1242 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1243 1244 if (!vmc->disallow_affinity_adjustment) { 1245 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1246 * GIC's target-list limitations. 32-bit KVM hosts currently 1247 * always create clusters of 4 CPUs, but that is expected to 1248 * change when they gain support for gicv3. When KVM is enabled 1249 * it will override the changes we make here, therefore our 1250 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1251 * and to improve SGI efficiency. 1252 */ 1253 if (vms->gic_version == 3) { 1254 clustersz = GICV3_TARGETLIST_BITS; 1255 } else { 1256 clustersz = GIC_TARGETLIST_BITS; 1257 } 1258 } 1259 return arm_cpu_mp_affinity(idx, clustersz); 1260 } 1261 1262 static void machvirt_init(MachineState *machine) 1263 { 1264 VirtMachineState *vms = VIRT_MACHINE(machine); 1265 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1266 MachineClass *mc = MACHINE_GET_CLASS(machine); 1267 const CPUArchIdList *possible_cpus; 1268 qemu_irq pic[NUM_IRQS]; 1269 MemoryRegion *sysmem = get_system_memory(); 1270 MemoryRegion *secure_sysmem = NULL; 1271 int n, virt_max_cpus; 1272 MemoryRegion *ram = g_new(MemoryRegion, 1); 1273 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1274 1275 /* We can probe only here because during property set 1276 * KVM is not available yet 1277 */ 1278 if (vms->gic_version <= 0) { 1279 /* "host" or "max" */ 1280 if (!kvm_enabled()) { 1281 if (vms->gic_version == 0) { 1282 error_report("gic-version=host requires KVM"); 1283 exit(1); 1284 } else { 1285 /* "max": currently means 3 for TCG */ 1286 vms->gic_version = 3; 1287 } 1288 } else { 1289 vms->gic_version = kvm_arm_vgic_probe(); 1290 if (!vms->gic_version) { 1291 error_report( 1292 "Unable to determine GIC version supported by host"); 1293 exit(1); 1294 } 1295 } 1296 } 1297 1298 if (!cpu_type_valid(machine->cpu_type)) { 1299 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1300 exit(1); 1301 } 1302 1303 /* If we have an EL3 boot ROM then the assumption is that it will 1304 * implement PSCI itself, so disable QEMU's internal implementation 1305 * so it doesn't get in the way. Instead of starting secondary 1306 * CPUs in PSCI powerdown state we will start them all running and 1307 * let the boot ROM sort them out. 1308 * The usual case is that we do use QEMU's PSCI implementation; 1309 * if the guest has EL2 then we will use SMC as the conduit, 1310 * and otherwise we will use HVC (for backwards compatibility and 1311 * because if we're using KVM then we must use HVC). 1312 */ 1313 if (vms->secure && firmware_loaded) { 1314 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1315 } else if (vms->virt) { 1316 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1317 } else { 1318 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1319 } 1320 1321 /* The maximum number of CPUs depends on the GIC version, or on how 1322 * many redistributors we can fit into the memory map. 1323 */ 1324 if (vms->gic_version == 3) { 1325 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1326 } else { 1327 virt_max_cpus = GIC_NCPU; 1328 } 1329 1330 if (max_cpus > virt_max_cpus) { 1331 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1332 "supported by machine 'mach-virt' (%d)", 1333 max_cpus, virt_max_cpus); 1334 exit(1); 1335 } 1336 1337 vms->smp_cpus = smp_cpus; 1338 1339 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1340 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1341 exit(1); 1342 } 1343 1344 if (vms->virt && kvm_enabled()) { 1345 error_report("mach-virt: KVM does not support providing " 1346 "Virtualization extensions to the guest CPU"); 1347 exit(1); 1348 } 1349 1350 if (vms->secure) { 1351 if (kvm_enabled()) { 1352 error_report("mach-virt: KVM does not support Security extensions"); 1353 exit(1); 1354 } 1355 1356 /* The Secure view of the world is the same as the NonSecure, 1357 * but with a few extra devices. Create it as a container region 1358 * containing the system memory at low priority; any secure-only 1359 * devices go in at higher priority and take precedence. 1360 */ 1361 secure_sysmem = g_new(MemoryRegion, 1); 1362 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1363 UINT64_MAX); 1364 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1365 } 1366 1367 create_fdt(vms); 1368 1369 possible_cpus = mc->possible_cpu_arch_ids(machine); 1370 for (n = 0; n < possible_cpus->len; n++) { 1371 Object *cpuobj; 1372 CPUState *cs; 1373 1374 if (n >= smp_cpus) { 1375 break; 1376 } 1377 1378 cpuobj = object_new(possible_cpus->cpus[n].type); 1379 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1380 "mp-affinity", NULL); 1381 1382 cs = CPU(cpuobj); 1383 cs->cpu_index = n; 1384 1385 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1386 &error_fatal); 1387 1388 if (!vms->secure) { 1389 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1390 } 1391 1392 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1393 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1394 } 1395 1396 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1397 object_property_set_int(cpuobj, vms->psci_conduit, 1398 "psci-conduit", NULL); 1399 1400 /* Secondary CPUs start in PSCI powered-down state */ 1401 if (n > 0) { 1402 object_property_set_bool(cpuobj, true, 1403 "start-powered-off", NULL); 1404 } 1405 } 1406 1407 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1408 object_property_set_bool(cpuobj, false, "pmu", NULL); 1409 } 1410 1411 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1412 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1413 "reset-cbar", &error_abort); 1414 } 1415 1416 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1417 &error_abort); 1418 if (vms->secure) { 1419 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1420 "secure-memory", &error_abort); 1421 } 1422 1423 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1424 object_unref(cpuobj); 1425 } 1426 fdt_add_timer_nodes(vms); 1427 fdt_add_cpu_nodes(vms); 1428 1429 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1430 machine->ram_size); 1431 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1432 1433 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1434 1435 create_gic(vms, pic); 1436 1437 fdt_add_pmu_nodes(vms); 1438 1439 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); 1440 1441 if (vms->secure) { 1442 create_secure_ram(vms, secure_sysmem); 1443 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1444 } 1445 1446 create_rtc(vms, pic); 1447 1448 create_pcie(vms, pic); 1449 1450 create_gpio(vms, pic); 1451 1452 /* Create mmio transports, so the user can create virtio backends 1453 * (which will be automatically plugged in to the transports). If 1454 * no backend is created the transport will just sit harmlessly idle. 1455 */ 1456 create_virtio_devices(vms, pic); 1457 1458 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1459 rom_set_fw(vms->fw_cfg); 1460 1461 create_platform_bus(vms, pic); 1462 1463 vms->bootinfo.ram_size = machine->ram_size; 1464 vms->bootinfo.kernel_filename = machine->kernel_filename; 1465 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1466 vms->bootinfo.initrd_filename = machine->initrd_filename; 1467 vms->bootinfo.nb_cpus = smp_cpus; 1468 vms->bootinfo.board_id = -1; 1469 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1470 vms->bootinfo.get_dtb = machvirt_dtb; 1471 vms->bootinfo.skip_dtb_autoload = true; 1472 vms->bootinfo.firmware_loaded = firmware_loaded; 1473 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1474 1475 vms->machine_done.notify = virt_machine_done; 1476 qemu_add_machine_init_done_notifier(&vms->machine_done); 1477 } 1478 1479 static bool virt_get_secure(Object *obj, Error **errp) 1480 { 1481 VirtMachineState *vms = VIRT_MACHINE(obj); 1482 1483 return vms->secure; 1484 } 1485 1486 static void virt_set_secure(Object *obj, bool value, Error **errp) 1487 { 1488 VirtMachineState *vms = VIRT_MACHINE(obj); 1489 1490 vms->secure = value; 1491 } 1492 1493 static bool virt_get_virt(Object *obj, Error **errp) 1494 { 1495 VirtMachineState *vms = VIRT_MACHINE(obj); 1496 1497 return vms->virt; 1498 } 1499 1500 static void virt_set_virt(Object *obj, bool value, Error **errp) 1501 { 1502 VirtMachineState *vms = VIRT_MACHINE(obj); 1503 1504 vms->virt = value; 1505 } 1506 1507 static bool virt_get_highmem(Object *obj, Error **errp) 1508 { 1509 VirtMachineState *vms = VIRT_MACHINE(obj); 1510 1511 return vms->highmem; 1512 } 1513 1514 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1515 { 1516 VirtMachineState *vms = VIRT_MACHINE(obj); 1517 1518 vms->highmem = value; 1519 } 1520 1521 static bool virt_get_its(Object *obj, Error **errp) 1522 { 1523 VirtMachineState *vms = VIRT_MACHINE(obj); 1524 1525 return vms->its; 1526 } 1527 1528 static void virt_set_its(Object *obj, bool value, Error **errp) 1529 { 1530 VirtMachineState *vms = VIRT_MACHINE(obj); 1531 1532 vms->its = value; 1533 } 1534 1535 static char *virt_get_gic_version(Object *obj, Error **errp) 1536 { 1537 VirtMachineState *vms = VIRT_MACHINE(obj); 1538 const char *val = vms->gic_version == 3 ? "3" : "2"; 1539 1540 return g_strdup(val); 1541 } 1542 1543 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1544 { 1545 VirtMachineState *vms = VIRT_MACHINE(obj); 1546 1547 if (!strcmp(value, "3")) { 1548 vms->gic_version = 3; 1549 } else if (!strcmp(value, "2")) { 1550 vms->gic_version = 2; 1551 } else if (!strcmp(value, "host")) { 1552 vms->gic_version = 0; /* Will probe later */ 1553 } else if (!strcmp(value, "max")) { 1554 vms->gic_version = -1; /* Will probe later */ 1555 } else { 1556 error_setg(errp, "Invalid gic-version value"); 1557 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1558 } 1559 } 1560 1561 static char *virt_get_iommu(Object *obj, Error **errp) 1562 { 1563 VirtMachineState *vms = VIRT_MACHINE(obj); 1564 1565 switch (vms->iommu) { 1566 case VIRT_IOMMU_NONE: 1567 return g_strdup("none"); 1568 case VIRT_IOMMU_SMMUV3: 1569 return g_strdup("smmuv3"); 1570 default: 1571 g_assert_not_reached(); 1572 } 1573 } 1574 1575 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1576 { 1577 VirtMachineState *vms = VIRT_MACHINE(obj); 1578 1579 if (!strcmp(value, "smmuv3")) { 1580 vms->iommu = VIRT_IOMMU_SMMUV3; 1581 } else if (!strcmp(value, "none")) { 1582 vms->iommu = VIRT_IOMMU_NONE; 1583 } else { 1584 error_setg(errp, "Invalid iommu value"); 1585 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1586 } 1587 } 1588 1589 static CpuInstanceProperties 1590 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1591 { 1592 MachineClass *mc = MACHINE_GET_CLASS(ms); 1593 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1594 1595 assert(cpu_index < possible_cpus->len); 1596 return possible_cpus->cpus[cpu_index].props; 1597 } 1598 1599 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1600 { 1601 return idx % nb_numa_nodes; 1602 } 1603 1604 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1605 { 1606 int n; 1607 VirtMachineState *vms = VIRT_MACHINE(ms); 1608 1609 if (ms->possible_cpus) { 1610 assert(ms->possible_cpus->len == max_cpus); 1611 return ms->possible_cpus; 1612 } 1613 1614 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1615 sizeof(CPUArchId) * max_cpus); 1616 ms->possible_cpus->len = max_cpus; 1617 for (n = 0; n < ms->possible_cpus->len; n++) { 1618 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1619 ms->possible_cpus->cpus[n].arch_id = 1620 virt_cpu_mp_affinity(vms, n); 1621 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1622 ms->possible_cpus->cpus[n].props.thread_id = n; 1623 } 1624 return ms->possible_cpus; 1625 } 1626 1627 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1628 DeviceState *dev, Error **errp) 1629 { 1630 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1631 1632 if (vms->platform_bus_dev) { 1633 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1634 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 1635 SYS_BUS_DEVICE(dev)); 1636 } 1637 } 1638 } 1639 1640 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1641 DeviceState *dev) 1642 { 1643 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1644 return HOTPLUG_HANDLER(machine); 1645 } 1646 1647 return NULL; 1648 } 1649 1650 static void virt_machine_class_init(ObjectClass *oc, void *data) 1651 { 1652 MachineClass *mc = MACHINE_CLASS(oc); 1653 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1654 1655 mc->init = machvirt_init; 1656 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1657 * it later in machvirt_init, where we have more information about the 1658 * configuration of the particular instance. 1659 */ 1660 mc->max_cpus = 255; 1661 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1662 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1663 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1664 mc->block_default_type = IF_VIRTIO; 1665 mc->no_cdrom = 1; 1666 mc->pci_allow_0_address = true; 1667 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1668 mc->minimum_page_bits = 12; 1669 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1670 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1671 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1672 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1673 assert(!mc->get_hotplug_handler); 1674 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1675 hc->plug = virt_machine_device_plug_cb; 1676 } 1677 1678 static const TypeInfo virt_machine_info = { 1679 .name = TYPE_VIRT_MACHINE, 1680 .parent = TYPE_MACHINE, 1681 .abstract = true, 1682 .instance_size = sizeof(VirtMachineState), 1683 .class_size = sizeof(VirtMachineClass), 1684 .class_init = virt_machine_class_init, 1685 .interfaces = (InterfaceInfo[]) { 1686 { TYPE_HOTPLUG_HANDLER }, 1687 { } 1688 }, 1689 }; 1690 1691 static void machvirt_machine_init(void) 1692 { 1693 type_register_static(&virt_machine_info); 1694 } 1695 type_init(machvirt_machine_init); 1696 1697 #define VIRT_COMPAT_2_12 \ 1698 HW_COMPAT_2_12 1699 1700 static void virt_2_12_instance_init(Object *obj) 1701 { 1702 VirtMachineState *vms = VIRT_MACHINE(obj); 1703 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1704 1705 /* EL3 is disabled by default on virt: this makes us consistent 1706 * between KVM and TCG for this board, and it also allows us to 1707 * boot UEFI blobs which assume no TrustZone support. 1708 */ 1709 vms->secure = false; 1710 object_property_add_bool(obj, "secure", virt_get_secure, 1711 virt_set_secure, NULL); 1712 object_property_set_description(obj, "secure", 1713 "Set on/off to enable/disable the ARM " 1714 "Security Extensions (TrustZone)", 1715 NULL); 1716 1717 /* EL2 is also disabled by default, for similar reasons */ 1718 vms->virt = false; 1719 object_property_add_bool(obj, "virtualization", virt_get_virt, 1720 virt_set_virt, NULL); 1721 object_property_set_description(obj, "virtualization", 1722 "Set on/off to enable/disable emulating a " 1723 "guest CPU which implements the ARM " 1724 "Virtualization Extensions", 1725 NULL); 1726 1727 /* High memory is enabled by default */ 1728 vms->highmem = true; 1729 object_property_add_bool(obj, "highmem", virt_get_highmem, 1730 virt_set_highmem, NULL); 1731 object_property_set_description(obj, "highmem", 1732 "Set on/off to enable/disable using " 1733 "physical address space above 32 bits", 1734 NULL); 1735 /* Default GIC type is v2 */ 1736 vms->gic_version = 2; 1737 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1738 virt_set_gic_version, NULL); 1739 object_property_set_description(obj, "gic-version", 1740 "Set GIC version. " 1741 "Valid values are 2, 3 and host", NULL); 1742 1743 if (vmc->no_its) { 1744 vms->its = false; 1745 } else { 1746 /* Default allows ITS instantiation */ 1747 vms->its = true; 1748 object_property_add_bool(obj, "its", virt_get_its, 1749 virt_set_its, NULL); 1750 object_property_set_description(obj, "its", 1751 "Set on/off to enable/disable " 1752 "ITS instantiation", 1753 NULL); 1754 } 1755 1756 /* Default disallows iommu instantiation */ 1757 vms->iommu = VIRT_IOMMU_NONE; 1758 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 1759 object_property_set_description(obj, "iommu", 1760 "Set the IOMMU type. " 1761 "Valid values are none and smmuv3", 1762 NULL); 1763 1764 vms->memmap = a15memmap; 1765 vms->irqmap = a15irqmap; 1766 } 1767 1768 static void virt_machine_2_12_options(MachineClass *mc) 1769 { 1770 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12); 1771 } 1772 DEFINE_VIRT_MACHINE_AS_LATEST(2, 12) 1773 1774 #define VIRT_COMPAT_2_11 \ 1775 HW_COMPAT_2_11 1776 1777 static void virt_2_11_instance_init(Object *obj) 1778 { 1779 virt_2_12_instance_init(obj); 1780 } 1781 1782 static void virt_machine_2_11_options(MachineClass *mc) 1783 { 1784 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1785 1786 virt_machine_2_12_options(mc); 1787 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); 1788 vmc->smbios_old_sys_ver = true; 1789 } 1790 DEFINE_VIRT_MACHINE(2, 11) 1791 1792 #define VIRT_COMPAT_2_10 \ 1793 HW_COMPAT_2_10 1794 1795 static void virt_2_10_instance_init(Object *obj) 1796 { 1797 virt_2_11_instance_init(obj); 1798 } 1799 1800 static void virt_machine_2_10_options(MachineClass *mc) 1801 { 1802 virt_machine_2_11_options(mc); 1803 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); 1804 } 1805 DEFINE_VIRT_MACHINE(2, 10) 1806 1807 #define VIRT_COMPAT_2_9 \ 1808 HW_COMPAT_2_9 1809 1810 static void virt_2_9_instance_init(Object *obj) 1811 { 1812 virt_2_10_instance_init(obj); 1813 } 1814 1815 static void virt_machine_2_9_options(MachineClass *mc) 1816 { 1817 virt_machine_2_10_options(mc); 1818 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1819 } 1820 DEFINE_VIRT_MACHINE(2, 9) 1821 1822 #define VIRT_COMPAT_2_8 \ 1823 HW_COMPAT_2_8 1824 1825 static void virt_2_8_instance_init(Object *obj) 1826 { 1827 virt_2_9_instance_init(obj); 1828 } 1829 1830 static void virt_machine_2_8_options(MachineClass *mc) 1831 { 1832 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1833 1834 virt_machine_2_9_options(mc); 1835 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1836 /* For 2.8 and earlier we falsely claimed in the DT that 1837 * our timers were edge-triggered, not level-triggered. 1838 */ 1839 vmc->claim_edge_triggered_timers = true; 1840 } 1841 DEFINE_VIRT_MACHINE(2, 8) 1842 1843 #define VIRT_COMPAT_2_7 \ 1844 HW_COMPAT_2_7 1845 1846 static void virt_2_7_instance_init(Object *obj) 1847 { 1848 virt_2_8_instance_init(obj); 1849 } 1850 1851 static void virt_machine_2_7_options(MachineClass *mc) 1852 { 1853 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1854 1855 virt_machine_2_8_options(mc); 1856 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1857 /* ITS was introduced with 2.8 */ 1858 vmc->no_its = true; 1859 /* Stick with 1K pages for migration compatibility */ 1860 mc->minimum_page_bits = 0; 1861 } 1862 DEFINE_VIRT_MACHINE(2, 7) 1863 1864 #define VIRT_COMPAT_2_6 \ 1865 HW_COMPAT_2_6 1866 1867 static void virt_2_6_instance_init(Object *obj) 1868 { 1869 virt_2_7_instance_init(obj); 1870 } 1871 1872 static void virt_machine_2_6_options(MachineClass *mc) 1873 { 1874 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1875 1876 virt_machine_2_7_options(mc); 1877 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1878 vmc->disallow_affinity_adjustment = true; 1879 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1880 vmc->no_pmu = true; 1881 } 1882 DEFINE_VIRT_MACHINE(2, 6) 1883