1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "system/device_tree.h" 46 #include "system/numa.h" 47 #include "system/runstate.h" 48 #include "system/tpm.h" 49 #include "system/tcg.h" 50 #include "system/kvm.h" 51 #include "system/hvf.h" 52 #include "system/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/cutils.h" 57 #include "qemu/error-report.h" 58 #include "qemu/module.h" 59 #include "hw/pci-host/gpex.h" 60 #include "hw/pci-bridge/pci_expander_bridge.h" 61 #include "hw/virtio/virtio-pci.h" 62 #include "hw/core/sysbus-fdt.h" 63 #include "hw/platform-bus.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/arm/fdt.h" 66 #include "hw/intc/arm_gic.h" 67 #include "hw/intc/arm_gicv3_common.h" 68 #include "hw/intc/arm_gicv3_its_common.h" 69 #include "hw/irq.h" 70 #include "kvm_arm.h" 71 #include "hvf_arm.h" 72 #include "hw/firmware/smbios.h" 73 #include "qapi/visitor.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qobject/qlist.h" 76 #include "standard-headers/linux/input.h" 77 #include "hw/arm/smmuv3.h" 78 #include "hw/acpi/acpi.h" 79 #include "hw/acpi/pcihp.h" 80 #include "target/arm/cpu-qom.h" 81 #include "target/arm/internals.h" 82 #include "target/arm/multiprocessing.h" 83 #include "target/arm/gtimer.h" 84 #include "hw/mem/pc-dimm.h" 85 #include "hw/mem/nvdimm.h" 86 #include "hw/acpi/generic_event_device.h" 87 #include "hw/uefi/var-service-api.h" 88 #include "hw/virtio/virtio-md-pci.h" 89 #include "hw/virtio/virtio-iommu.h" 90 #include "hw/char/pl011.h" 91 #include "hw/cxl/cxl.h" 92 #include "hw/cxl/cxl_host.h" 93 #include "qemu/guest-random.h" 94 95 static GlobalProperty arm_virt_compat[] = { 96 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, 97 }; 98 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat); 99 100 /* 101 * This cannot be called from the virt_machine_class_init() because 102 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() 103 * only is called on virt non abstract class init. 104 */ 105 static void arm_virt_compat_set(MachineClass *mc) 106 { 107 compat_props_add(mc->compat_props, arm_virt_compat, 108 arm_virt_compat_len); 109 } 110 111 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \ 112 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \ 113 ObjectClass *oc, \ 114 const void *data) \ 115 { \ 116 MachineClass *mc = MACHINE_CLASS(oc); \ 117 arm_virt_compat_set(mc); \ 118 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ 119 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \ 120 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 121 if (latest) { \ 122 mc->alias = "virt"; \ 123 } \ 124 } \ 125 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \ 126 { \ 127 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ 128 .parent = TYPE_VIRT_MACHINE, \ 129 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ 130 }; \ 131 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ 132 { \ 133 MACHINE_VER_DELETION(__VA_ARGS__); \ 134 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \ 135 } \ 136 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__)); 137 138 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 139 DEFINE_VIRT_MACHINE_IMPL(true, major, minor) 140 #define DEFINE_VIRT_MACHINE(major, minor) \ 141 DEFINE_VIRT_MACHINE_IMPL(false, major, minor) 142 143 144 /* Number of external interrupt lines to configure the GIC with */ 145 #define NUM_IRQS 256 146 147 #define PLATFORM_BUS_NUM_IRQS 64 148 149 /* Legacy RAM limit in GB (< version 4.0) */ 150 #define LEGACY_RAMLIMIT_GB 255 151 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 152 153 /* Addresses and sizes of our components. 154 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 155 * 128MB..256MB is used for miscellaneous device I/O. 156 * 256MB..1GB is reserved for possible future PCI support (ie where the 157 * PCI memory window will go if we add a PCI host controller). 158 * 1GB and up is RAM (which may happily spill over into the 159 * high memory region beyond 4GB). 160 * This represents a compromise between how much RAM can be given to 161 * a 32 bit VM and leaving space for expansion and in particular for PCI. 162 * Note that devices should generally be placed at multiples of 0x10000, 163 * to accommodate guests using 64K pages. 164 */ 165 static const MemMapEntry base_memmap[] = { 166 /* Space up to 0x8000000 is reserved for a boot ROM */ 167 [VIRT_FLASH] = { 0, 0x08000000 }, 168 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 169 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 170 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 171 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 172 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 173 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 174 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 175 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 176 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 177 /* This redistributor space allows up to 2*64kB*123 CPUs */ 178 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 179 [VIRT_UART0] = { 0x09000000, 0x00001000 }, 180 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 181 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 182 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 183 [VIRT_UART1] = { 0x09040000, 0x00001000 }, 184 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 185 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 186 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 187 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 188 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 189 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 190 [VIRT_ACPI_PCIHP] = { 0x090c0000, ACPI_PCIHP_SIZE }, 191 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 192 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 193 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 194 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 195 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 196 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 197 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 198 /* Actual RAM size depends on initial RAM and device memory settings */ 199 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 200 }; 201 202 /* Update the docs for highmem-mmio-size when changing this default */ 203 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512 204 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) 205 206 /* 207 * Highmem IO Regions: This memory map is floating, located after the RAM. 208 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 209 * top of the RAM, so that its base get the same alignment as the size, 210 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 211 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 212 * Note the extended_memmap is sized so that it eventually also includes the 213 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 214 * index of base_memmap). 215 * 216 * The memory map for these Highmem IO Regions can be in legacy or compact 217 * layout, depending on 'compact-highmem' property. With legacy layout, the 218 * PA space for one specific region is always reserved, even if the region 219 * has been disabled or doesn't fit into the PA space. However, the PA space 220 * for the region won't be reserved in these circumstances with compact layout. 221 * 222 * Note that the highmem-mmio-size property will update the high PCIE MMIO size 223 * field in this array. 224 */ 225 static MemMapEntry extended_memmap[] = { 226 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 227 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 228 [VIRT_CXL_HOST] = { 0x0, 64 * KiB * 16 }, /* 16 UID */ 229 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 230 /* Second PCIe window */ 231 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, 232 /* Any CXL Fixed memory windows come here */ 233 }; 234 235 static const int a15irqmap[] = { 236 [VIRT_UART0] = 1, 237 [VIRT_RTC] = 2, 238 [VIRT_PCIE] = 3, /* ... to 6 */ 239 [VIRT_GPIO] = 7, 240 [VIRT_UART1] = 8, 241 [VIRT_ACPI_GED] = 9, 242 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 243 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 244 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 245 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 246 }; 247 248 static void create_randomness(MachineState *ms, const char *node) 249 { 250 struct { 251 uint64_t kaslr; 252 uint8_t rng[32]; 253 } seed; 254 255 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 256 return; 257 } 258 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 259 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 260 } 261 262 /* 263 * The CPU object always exposes the NS EL2 virt timer IRQ line, 264 * but we don't want to advertise it to the guest in the dtb or ACPI 265 * table unless it's really going to do something. 266 */ 267 static bool ns_el2_virt_timer_present(void) 268 { 269 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 270 CPUARMState *env = &cpu->env; 271 272 return arm_feature(env, ARM_FEATURE_AARCH64) && 273 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); 274 } 275 276 static void create_fdt(VirtMachineState *vms) 277 { 278 MachineState *ms = MACHINE(vms); 279 int nb_numa_nodes = ms->numa_state->num_nodes; 280 void *fdt = create_device_tree(&vms->fdt_size); 281 282 if (!fdt) { 283 error_report("create_device_tree() failed"); 284 exit(1); 285 } 286 287 ms->fdt = fdt; 288 289 /* Header */ 290 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 291 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 292 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 293 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 294 295 /* 296 * For QEMU, all DMA is coherent. Advertising this in the root node 297 * has two benefits: 298 * 299 * - It avoids potential bugs where we forget to mark a DMA 300 * capable device as being dma-coherent 301 * - It avoids spurious warnings from the Linux kernel about 302 * devices which can't do DMA at all 303 */ 304 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0); 305 306 /* /chosen must exist for load_dtb to fill in necessary properties later */ 307 qemu_fdt_add_subnode(fdt, "/chosen"); 308 if (vms->dtb_randomness) { 309 create_randomness(ms, "/chosen"); 310 } 311 312 if (vms->secure) { 313 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 314 if (vms->dtb_randomness) { 315 create_randomness(ms, "/secure-chosen"); 316 } 317 } 318 319 qemu_fdt_add_subnode(fdt, "/aliases"); 320 321 /* Clock node, for the benefit of the UART. The kernel device tree 322 * binding documentation claims the PL011 node clock properties are 323 * optional but in practice if you omit them the kernel refuses to 324 * probe for the device. 325 */ 326 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 327 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 328 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 329 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 330 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 331 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 332 "clk24mhz"); 333 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 334 335 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 336 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 337 uint32_t *matrix = g_malloc0(size); 338 int idx, i, j; 339 340 for (i = 0; i < nb_numa_nodes; i++) { 341 for (j = 0; j < nb_numa_nodes; j++) { 342 idx = (i * nb_numa_nodes + j) * 3; 343 matrix[idx + 0] = cpu_to_be32(i); 344 matrix[idx + 1] = cpu_to_be32(j); 345 matrix[idx + 2] = 346 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 347 } 348 } 349 350 qemu_fdt_add_subnode(fdt, "/distance-map"); 351 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 352 "numa-distance-map-v1"); 353 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 354 matrix, size); 355 g_free(matrix); 356 } 357 } 358 359 static void fdt_add_timer_nodes(const VirtMachineState *vms) 360 { 361 /* On real hardware these interrupts are level-triggered. 362 * On KVM they were edge-triggered before host kernel version 4.4, 363 * and level-triggered afterwards. 364 * On emulated QEMU they are level-triggered. 365 * 366 * Getting the DTB info about them wrong is awkward for some 367 * guest kernels: 368 * pre-4.8 ignore the DT and leave the interrupt configured 369 * with whatever the GIC reset value (or the bootloader) left it at 370 * 4.8 before rc6 honour the incorrect data by programming it back 371 * into the GIC, causing problems 372 * 4.8rc6 and later ignore the DT and always write "level triggered" 373 * into the GIC 374 * 375 * For backwards-compatibility, virt-2.8 and earlier will continue 376 * to say these are edge-triggered, but later machines will report 377 * the correct information. 378 */ 379 ARMCPU *armcpu; 380 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 381 MachineState *ms = MACHINE(vms); 382 383 if (vms->gic_version == VIRT_GIC_VERSION_2) { 384 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 385 GIC_FDT_IRQ_PPI_CPU_WIDTH, 386 (1 << MACHINE(vms)->smp.cpus) - 1); 387 } 388 389 qemu_fdt_add_subnode(ms->fdt, "/timer"); 390 391 armcpu = ARM_CPU(qemu_get_cpu(0)); 392 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 393 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 394 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 395 compat, sizeof(compat)); 396 } else { 397 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 398 "arm,armv7-timer"); 399 } 400 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 401 if (vms->ns_el2_virt_timer_irq) { 402 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 403 GIC_FDT_IRQ_TYPE_PPI, 404 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 405 GIC_FDT_IRQ_TYPE_PPI, 406 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 407 GIC_FDT_IRQ_TYPE_PPI, 408 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 409 GIC_FDT_IRQ_TYPE_PPI, 410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, 411 GIC_FDT_IRQ_TYPE_PPI, 412 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); 413 } else { 414 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 415 GIC_FDT_IRQ_TYPE_PPI, 416 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 417 GIC_FDT_IRQ_TYPE_PPI, 418 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 419 GIC_FDT_IRQ_TYPE_PPI, 420 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 421 GIC_FDT_IRQ_TYPE_PPI, 422 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 423 } 424 } 425 426 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 427 { 428 int cpu; 429 int addr_cells = 1; 430 const MachineState *ms = MACHINE(vms); 431 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 432 int smp_cpus = ms->smp.cpus; 433 434 /* 435 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 436 * On ARM v8 64-bit systems value should be set to 2, 437 * that corresponds to the MPIDR_EL1 register size. 438 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 439 * in the system, #address-cells can be set to 1, since 440 * MPIDR_EL1[63:32] bits are not used for CPUs 441 * identification. 442 * 443 * Here we actually don't know whether our system is 32- or 64-bit one. 444 * The simplest way to go is to examine affinity IDs of all our CPUs. If 445 * at least one of them has Aff3 populated, we set #address-cells to 2. 446 */ 447 for (cpu = 0; cpu < smp_cpus; cpu++) { 448 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 449 450 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 451 addr_cells = 2; 452 break; 453 } 454 } 455 456 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 457 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 458 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 459 460 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 461 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 462 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 463 CPUState *cs = CPU(armcpu); 464 465 qemu_fdt_add_subnode(ms->fdt, nodename); 466 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 467 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 468 armcpu->dtb_compatible); 469 470 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 471 qemu_fdt_setprop_string(ms->fdt, nodename, 472 "enable-method", "psci"); 473 } 474 475 if (addr_cells == 2) { 476 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 477 arm_cpu_mp_affinity(armcpu)); 478 } else { 479 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 480 arm_cpu_mp_affinity(armcpu)); 481 } 482 483 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 484 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 485 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 486 } 487 488 if (!vmc->no_cpu_topology) { 489 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 490 qemu_fdt_alloc_phandle(ms->fdt)); 491 } 492 493 g_free(nodename); 494 } 495 496 if (!vmc->no_cpu_topology) { 497 /* 498 * Add vCPU topology description through fdt node cpu-map. 499 * 500 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 501 * In a SMP system, the hierarchy of CPUs can be defined through 502 * four entities that are used to describe the layout of CPUs in 503 * the system: socket/cluster/core/thread. 504 * 505 * A socket node represents the boundary of system physical package 506 * and its child nodes must be one or more cluster nodes. A system 507 * can contain several layers of clustering within a single physical 508 * package and cluster nodes can be contained in parent cluster nodes. 509 * 510 * Note: currently we only support one layer of clustering within 511 * each physical package. 512 */ 513 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 514 515 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 516 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 517 char *map_path; 518 519 if (ms->smp.threads > 1) { 520 map_path = g_strdup_printf( 521 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 522 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 523 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 524 (cpu / ms->smp.threads) % ms->smp.cores, 525 cpu % ms->smp.threads); 526 } else { 527 map_path = g_strdup_printf( 528 "/cpus/cpu-map/socket%d/cluster%d/core%d", 529 cpu / (ms->smp.clusters * ms->smp.cores), 530 (cpu / ms->smp.cores) % ms->smp.clusters, 531 cpu % ms->smp.cores); 532 } 533 qemu_fdt_add_path(ms->fdt, map_path); 534 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 535 536 g_free(map_path); 537 g_free(cpu_path); 538 } 539 } 540 } 541 542 static void fdt_add_its_gic_node(VirtMachineState *vms) 543 { 544 char *nodename; 545 MachineState *ms = MACHINE(vms); 546 547 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 548 nodename = g_strdup_printf("/intc/its@%" PRIx64, 549 vms->memmap[VIRT_GIC_ITS].base); 550 qemu_fdt_add_subnode(ms->fdt, nodename); 551 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 552 "arm,gic-v3-its"); 553 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 554 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 555 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 556 2, vms->memmap[VIRT_GIC_ITS].base, 557 2, vms->memmap[VIRT_GIC_ITS].size); 558 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 559 g_free(nodename); 560 } 561 562 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 563 { 564 MachineState *ms = MACHINE(vms); 565 char *nodename; 566 567 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 568 vms->memmap[VIRT_GIC_V2M].base); 569 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 570 qemu_fdt_add_subnode(ms->fdt, nodename); 571 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 572 "arm,gic-v2m-frame"); 573 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 574 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 575 2, vms->memmap[VIRT_GIC_V2M].base, 576 2, vms->memmap[VIRT_GIC_V2M].size); 577 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 578 g_free(nodename); 579 } 580 581 static void fdt_add_gic_node(VirtMachineState *vms) 582 { 583 MachineState *ms = MACHINE(vms); 584 char *nodename; 585 586 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 587 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 588 589 nodename = g_strdup_printf("/intc@%" PRIx64, 590 vms->memmap[VIRT_GIC_DIST].base); 591 qemu_fdt_add_subnode(ms->fdt, nodename); 592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 593 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 594 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 595 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 596 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 597 if (vms->gic_version != VIRT_GIC_VERSION_2) { 598 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 599 600 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 601 "arm,gic-v3"); 602 603 qemu_fdt_setprop_cell(ms->fdt, nodename, 604 "#redistributor-regions", nb_redist_regions); 605 606 if (nb_redist_regions == 1) { 607 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 608 2, vms->memmap[VIRT_GIC_DIST].base, 609 2, vms->memmap[VIRT_GIC_DIST].size, 610 2, vms->memmap[VIRT_GIC_REDIST].base, 611 2, vms->memmap[VIRT_GIC_REDIST].size); 612 } else { 613 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 614 2, vms->memmap[VIRT_GIC_DIST].base, 615 2, vms->memmap[VIRT_GIC_DIST].size, 616 2, vms->memmap[VIRT_GIC_REDIST].base, 617 2, vms->memmap[VIRT_GIC_REDIST].size, 618 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 619 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 620 } 621 622 if (vms->virt) { 623 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 624 GIC_FDT_IRQ_TYPE_PPI, 625 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 626 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 627 } 628 } else { 629 /* 'cortex-a15-gic' means 'GIC v2' */ 630 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 631 "arm,cortex-a15-gic"); 632 if (!vms->virt) { 633 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 634 2, vms->memmap[VIRT_GIC_DIST].base, 635 2, vms->memmap[VIRT_GIC_DIST].size, 636 2, vms->memmap[VIRT_GIC_CPU].base, 637 2, vms->memmap[VIRT_GIC_CPU].size); 638 } else { 639 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 640 2, vms->memmap[VIRT_GIC_DIST].base, 641 2, vms->memmap[VIRT_GIC_DIST].size, 642 2, vms->memmap[VIRT_GIC_CPU].base, 643 2, vms->memmap[VIRT_GIC_CPU].size, 644 2, vms->memmap[VIRT_GIC_HYP].base, 645 2, vms->memmap[VIRT_GIC_HYP].size, 646 2, vms->memmap[VIRT_GIC_VCPU].base, 647 2, vms->memmap[VIRT_GIC_VCPU].size); 648 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 649 GIC_FDT_IRQ_TYPE_PPI, 650 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 651 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 652 } 653 } 654 655 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 656 g_free(nodename); 657 } 658 659 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 660 { 661 ARMCPU *armcpu = ARM_CPU(first_cpu); 662 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 663 MachineState *ms = MACHINE(vms); 664 665 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 666 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 667 return; 668 } 669 670 if (vms->gic_version == VIRT_GIC_VERSION_2) { 671 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 672 GIC_FDT_IRQ_PPI_CPU_WIDTH, 673 (1 << MACHINE(vms)->smp.cpus) - 1); 674 } 675 676 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 677 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 678 const char compat[] = "arm,armv8-pmuv3"; 679 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 680 compat, sizeof(compat)); 681 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 682 GIC_FDT_IRQ_TYPE_PPI, 683 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 684 } 685 } 686 687 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 688 { 689 DeviceState *dev; 690 MachineState *ms = MACHINE(vms); 691 int irq = vms->irqmap[VIRT_ACPI_GED]; 692 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 693 694 if (ms->ram_slots) { 695 event |= ACPI_GED_MEM_HOTPLUG_EVT; 696 } 697 698 if (ms->nvdimms_state->is_enabled) { 699 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 700 } 701 702 dev = qdev_new(TYPE_ACPI_GED); 703 qdev_prop_set_uint32(dev, "ged-event", event); 704 object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_abort); 705 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 706 707 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 708 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 709 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 710 711 return dev; 712 } 713 714 static void create_its(VirtMachineState *vms) 715 { 716 DeviceState *dev; 717 718 assert(vms->its); 719 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { 720 /* 721 * Do nothing if ITS is neither supported by the host nor emulated by 722 * the machine. 723 */ 724 return; 725 } 726 727 dev = qdev_new(its_class_name()); 728 729 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 730 &error_abort); 731 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 732 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 733 734 fdt_add_its_gic_node(vms); 735 vms->msi_controller = VIRT_MSI_CTRL_ITS; 736 } 737 738 static void create_v2m(VirtMachineState *vms) 739 { 740 int i; 741 int irq = vms->irqmap[VIRT_GIC_V2M]; 742 DeviceState *dev; 743 744 dev = qdev_new("arm-gicv2m"); 745 qdev_prop_set_uint32(dev, "base-spi", irq); 746 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 747 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 748 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 749 750 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 751 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 752 qdev_get_gpio_in(vms->gic, irq + i)); 753 } 754 755 fdt_add_v2m_gic_node(vms); 756 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 757 } 758 759 /* 760 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. 761 * It's permitted to have a configuration with NMI in the CPU (and thus the 762 * GICv3 CPU interface) but not in the distributor/redistributors, but it's 763 * not very useful. 764 */ 765 static bool gicv3_nmi_present(VirtMachineState *vms) 766 { 767 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 768 769 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) && 770 (vms->gic_version != VIRT_GIC_VERSION_2); 771 } 772 773 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 774 { 775 MachineState *ms = MACHINE(vms); 776 /* We create a standalone GIC */ 777 SysBusDevice *gicbusdev; 778 const char *gictype; 779 int i; 780 unsigned int smp_cpus = ms->smp.cpus; 781 uint32_t nb_redist_regions = 0; 782 int revision; 783 784 if (vms->gic_version == VIRT_GIC_VERSION_2) { 785 gictype = gic_class_name(); 786 } else { 787 gictype = gicv3_class_name(); 788 } 789 790 switch (vms->gic_version) { 791 case VIRT_GIC_VERSION_2: 792 revision = 2; 793 break; 794 case VIRT_GIC_VERSION_3: 795 revision = 3; 796 break; 797 case VIRT_GIC_VERSION_4: 798 revision = 4; 799 break; 800 default: 801 g_assert_not_reached(); 802 } 803 804 if (kvm_enabled() && vms->virt && 805 (revision != 3 || !kvm_irqchip_in_kernel())) { 806 error_report("KVM EL2 is only supported with in-kernel GICv3"); 807 exit(1); 808 } 809 810 vms->gic = qdev_new(gictype); 811 qdev_prop_set_uint32(vms->gic, "revision", revision); 812 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 813 /* Note that the num-irq property counts both internal and external 814 * interrupts; there are always 32 of the former (mandated by GIC spec). 815 */ 816 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 817 if (!kvm_irqchip_in_kernel()) { 818 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 819 } 820 821 if (vms->gic_version != VIRT_GIC_VERSION_2) { 822 QList *redist_region_count; 823 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 824 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 825 826 nb_redist_regions = virt_gicv3_redist_region_count(vms); 827 828 redist_region_count = qlist_new(); 829 qlist_append_int(redist_region_count, redist0_count); 830 if (nb_redist_regions == 2) { 831 uint32_t redist1_capacity = 832 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 833 834 qlist_append_int(redist_region_count, 835 MIN(smp_cpus - redist0_count, redist1_capacity)); 836 } 837 qdev_prop_set_array(vms->gic, "redist-region-count", 838 redist_region_count); 839 840 if (!kvm_irqchip_in_kernel()) { 841 if (vms->tcg_its) { 842 object_property_set_link(OBJECT(vms->gic), "sysmem", 843 OBJECT(mem), &error_fatal); 844 qdev_prop_set_bit(vms->gic, "has-lpi", true); 845 } 846 } else if (vms->virt) { 847 qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", 848 ARCH_GIC_MAINT_IRQ); 849 } 850 } else { 851 if (!kvm_irqchip_in_kernel()) { 852 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 853 vms->virt); 854 } 855 } 856 857 if (gicv3_nmi_present(vms)) { 858 qdev_prop_set_bit(vms->gic, "has-nmi", true); 859 } 860 861 gicbusdev = SYS_BUS_DEVICE(vms->gic); 862 sysbus_realize_and_unref(gicbusdev, &error_fatal); 863 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 864 if (vms->gic_version != VIRT_GIC_VERSION_2) { 865 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 866 if (nb_redist_regions == 2) { 867 sysbus_mmio_map(gicbusdev, 2, 868 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 869 } 870 } else { 871 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 872 if (vms->virt) { 873 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 874 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 875 } 876 } 877 878 /* Wire the outputs from each CPU's generic timer and the GICv3 879 * maintenance interrupt signal to the appropriate GIC PPI inputs, 880 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the 881 * CPU's inputs. 882 */ 883 for (i = 0; i < smp_cpus; i++) { 884 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 885 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 886 /* Mapping from the output timer irq lines from the CPU to the 887 * GIC PPI inputs we use for the virt board. 888 */ 889 const int timer_irq[] = { 890 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 891 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 892 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 893 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 894 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 895 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, 896 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, 897 }; 898 899 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 900 qdev_connect_gpio_out(cpudev, irq, 901 qdev_get_gpio_in(vms->gic, 902 intidbase + timer_irq[irq])); 903 } 904 905 if (vms->gic_version != VIRT_GIC_VERSION_2) { 906 qemu_irq irq = qdev_get_gpio_in(vms->gic, 907 intidbase + ARCH_GIC_MAINT_IRQ); 908 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 909 0, irq); 910 } else if (vms->virt) { 911 qemu_irq irq = qdev_get_gpio_in(vms->gic, 912 intidbase + ARCH_GIC_MAINT_IRQ); 913 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 914 } 915 916 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 917 qdev_get_gpio_in(vms->gic, intidbase 918 + VIRTUAL_PMU_IRQ)); 919 920 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 921 sysbus_connect_irq(gicbusdev, i + smp_cpus, 922 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 923 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 924 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 925 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 926 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 927 928 if (vms->gic_version != VIRT_GIC_VERSION_2) { 929 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, 930 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 931 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, 932 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 933 } 934 } 935 936 fdt_add_gic_node(vms); 937 938 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 939 create_its(vms); 940 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 941 create_v2m(vms); 942 } 943 } 944 945 static void create_uart(const VirtMachineState *vms, int uart, 946 MemoryRegion *mem, Chardev *chr, bool secure) 947 { 948 char *nodename; 949 hwaddr base = vms->memmap[uart].base; 950 hwaddr size = vms->memmap[uart].size; 951 int irq = vms->irqmap[uart]; 952 const char compat[] = "arm,pl011\0arm,primecell"; 953 const char clocknames[] = "uartclk\0apb_pclk"; 954 DeviceState *dev = qdev_new(TYPE_PL011); 955 SysBusDevice *s = SYS_BUS_DEVICE(dev); 956 MachineState *ms = MACHINE(vms); 957 958 qdev_prop_set_chr(dev, "chardev", chr); 959 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 960 memory_region_add_subregion(mem, base, 961 sysbus_mmio_get_region(s, 0)); 962 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 963 964 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 965 qemu_fdt_add_subnode(ms->fdt, nodename); 966 /* Note that we can't use setprop_string because of the embedded NUL */ 967 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 968 compat, sizeof(compat)); 969 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 970 2, base, 2, size); 971 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 972 GIC_FDT_IRQ_TYPE_SPI, irq, 973 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 974 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 975 vms->clock_phandle, vms->clock_phandle); 976 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 977 clocknames, sizeof(clocknames)); 978 979 if (uart == VIRT_UART0) { 980 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 981 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); 982 } else { 983 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); 984 } 985 if (secure) { 986 /* Mark as not usable by the normal world */ 987 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 988 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 989 990 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 991 nodename); 992 } 993 994 g_free(nodename); 995 } 996 997 static void create_rtc(const VirtMachineState *vms) 998 { 999 char *nodename; 1000 hwaddr base = vms->memmap[VIRT_RTC].base; 1001 hwaddr size = vms->memmap[VIRT_RTC].size; 1002 int irq = vms->irqmap[VIRT_RTC]; 1003 const char compat[] = "arm,pl031\0arm,primecell"; 1004 MachineState *ms = MACHINE(vms); 1005 1006 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 1007 1008 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 1009 qemu_fdt_add_subnode(ms->fdt, nodename); 1010 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1011 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1012 2, base, 2, size); 1013 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1014 GIC_FDT_IRQ_TYPE_SPI, irq, 1015 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1016 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1017 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1018 g_free(nodename); 1019 } 1020 1021 static DeviceState *gpio_key_dev; 1022 static void virt_powerdown_req(Notifier *n, void *opaque) 1023 { 1024 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 1025 1026 if (s->acpi_dev) { 1027 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 1028 } else { 1029 /* use gpio Pin for power button event */ 1030 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 1031 } 1032 } 1033 1034 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 1035 uint32_t phandle) 1036 { 1037 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 1038 qdev_get_gpio_in(pl061_dev, 1039 GPIO_PIN_POWER_BUTTON)); 1040 1041 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 1042 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 1043 1044 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 1045 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 1046 "label", "GPIO Key Poweroff"); 1047 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 1048 KEY_POWER); 1049 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 1050 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0); 1051 } 1052 1053 #define SECURE_GPIO_POWEROFF 0 1054 #define SECURE_GPIO_RESET 1 1055 1056 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 1057 uint32_t phandle) 1058 { 1059 DeviceState *gpio_pwr_dev; 1060 1061 /* gpio-pwr */ 1062 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 1063 1064 /* connect secure pl061 to gpio-pwr */ 1065 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 1066 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 1067 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 1068 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 1069 1070 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 1071 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 1072 "gpio-poweroff"); 1073 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 1074 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 1075 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 1076 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 1077 "okay"); 1078 1079 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 1080 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 1081 "gpio-restart"); 1082 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 1083 "gpios", phandle, SECURE_GPIO_RESET, 0); 1084 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 1085 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 1086 "okay"); 1087 } 1088 1089 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 1090 MemoryRegion *mem) 1091 { 1092 char *nodename; 1093 DeviceState *pl061_dev; 1094 hwaddr base = vms->memmap[gpio].base; 1095 hwaddr size = vms->memmap[gpio].size; 1096 int irq = vms->irqmap[gpio]; 1097 const char compat[] = "arm,pl061\0arm,primecell"; 1098 SysBusDevice *s; 1099 MachineState *ms = MACHINE(vms); 1100 1101 pl061_dev = qdev_new("pl061"); 1102 /* Pull lines down to 0 if not driven by the PL061 */ 1103 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1104 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1105 s = SYS_BUS_DEVICE(pl061_dev); 1106 sysbus_realize_and_unref(s, &error_fatal); 1107 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1108 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1109 1110 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1111 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1112 qemu_fdt_add_subnode(ms->fdt, nodename); 1113 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1114 2, base, 2, size); 1115 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1116 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1117 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1118 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1119 GIC_FDT_IRQ_TYPE_SPI, irq, 1120 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1121 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1122 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1123 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1124 1125 if (gpio != VIRT_GPIO) { 1126 /* Mark as not usable by the normal world */ 1127 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1128 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1129 } 1130 g_free(nodename); 1131 1132 /* Child gpio devices */ 1133 if (gpio == VIRT_GPIO) { 1134 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1135 } else { 1136 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1137 } 1138 } 1139 1140 static void create_virtio_devices(const VirtMachineState *vms) 1141 { 1142 int i; 1143 hwaddr size = vms->memmap[VIRT_MMIO].size; 1144 MachineState *ms = MACHINE(vms); 1145 1146 /* We create the transports in forwards order. Since qbus_realize() 1147 * prepends (not appends) new child buses, the incrementing loop below will 1148 * create a list of virtio-mmio buses with decreasing base addresses. 1149 * 1150 * When a -device option is processed from the command line, 1151 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1152 * order. The upshot is that -device options in increasing command line 1153 * order are mapped to virtio-mmio buses with decreasing base addresses. 1154 * 1155 * When this code was originally written, that arrangement ensured that the 1156 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1157 * the first -device on the command line. (The end-to-end order is a 1158 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1159 * guest kernel's name-to-address assignment strategy.) 1160 * 1161 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1162 * the message, if not necessarily the code, of commit 70161ff336. 1163 * Therefore the loop now establishes the inverse of the original intent. 1164 * 1165 * Unfortunately, we can't counteract the kernel change by reversing the 1166 * loop; it would break existing command lines. 1167 * 1168 * In any case, the kernel makes no guarantee about the stability of 1169 * enumeration order of virtio devices (as demonstrated by it changing 1170 * between kernel versions). For reliable and stable identification 1171 * of disks users must use UUIDs or similar mechanisms. 1172 */ 1173 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1174 int irq = vms->irqmap[VIRT_MMIO] + i; 1175 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1176 1177 sysbus_create_simple("virtio-mmio", base, 1178 qdev_get_gpio_in(vms->gic, irq)); 1179 } 1180 1181 /* We add dtb nodes in reverse order so that they appear in the finished 1182 * device tree lowest address first. 1183 * 1184 * Note that this mapping is independent of the loop above. The previous 1185 * loop influences virtio device to virtio transport assignment, whereas 1186 * this loop controls how virtio transports are laid out in the dtb. 1187 */ 1188 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1189 char *nodename; 1190 int irq = vms->irqmap[VIRT_MMIO] + i; 1191 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1192 1193 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1194 qemu_fdt_add_subnode(ms->fdt, nodename); 1195 qemu_fdt_setprop_string(ms->fdt, nodename, 1196 "compatible", "virtio,mmio"); 1197 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1198 2, base, 2, size); 1199 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1200 GIC_FDT_IRQ_TYPE_SPI, irq, 1201 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1202 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1203 g_free(nodename); 1204 } 1205 } 1206 1207 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1208 1209 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1210 const char *name, 1211 const char *alias_prop_name) 1212 { 1213 /* 1214 * Create a single flash device. We use the same parameters as 1215 * the flash devices on the Versatile Express board. 1216 */ 1217 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1218 1219 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1220 qdev_prop_set_uint8(dev, "width", 4); 1221 qdev_prop_set_uint8(dev, "device-width", 2); 1222 qdev_prop_set_bit(dev, "big-endian", false); 1223 qdev_prop_set_uint16(dev, "id0", 0x89); 1224 qdev_prop_set_uint16(dev, "id1", 0x18); 1225 qdev_prop_set_uint16(dev, "id2", 0x00); 1226 qdev_prop_set_uint16(dev, "id3", 0x00); 1227 qdev_prop_set_string(dev, "name", name); 1228 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1229 object_property_add_alias(OBJECT(vms), alias_prop_name, 1230 OBJECT(dev), "drive"); 1231 return PFLASH_CFI01(dev); 1232 } 1233 1234 static void virt_flash_create(VirtMachineState *vms) 1235 { 1236 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1237 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1238 } 1239 1240 static void virt_flash_map1(PFlashCFI01 *flash, 1241 hwaddr base, hwaddr size, 1242 MemoryRegion *sysmem) 1243 { 1244 DeviceState *dev = DEVICE(flash); 1245 1246 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1247 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1248 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1249 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1250 1251 memory_region_add_subregion(sysmem, base, 1252 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1253 0)); 1254 } 1255 1256 static void virt_flash_map(VirtMachineState *vms, 1257 MemoryRegion *sysmem, 1258 MemoryRegion *secure_sysmem) 1259 { 1260 /* 1261 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1262 * sysmem is the system memory space. secure_sysmem is the secure view 1263 * of the system, and the first flash device should be made visible only 1264 * there. The second flash device is visible to both secure and nonsecure. 1265 * If sysmem == secure_sysmem this means there is no separate Secure 1266 * address space and both flash devices are generally visible. 1267 */ 1268 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1269 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1270 1271 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1272 secure_sysmem); 1273 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1274 sysmem); 1275 } 1276 1277 static void virt_flash_fdt(VirtMachineState *vms, 1278 MemoryRegion *sysmem, 1279 MemoryRegion *secure_sysmem) 1280 { 1281 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1282 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1283 MachineState *ms = MACHINE(vms); 1284 char *nodename; 1285 1286 if (sysmem == secure_sysmem) { 1287 /* Report both flash devices as a single node in the DT */ 1288 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1289 qemu_fdt_add_subnode(ms->fdt, nodename); 1290 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1291 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1292 2, flashbase, 2, flashsize, 1293 2, flashbase + flashsize, 2, flashsize); 1294 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1295 g_free(nodename); 1296 } else { 1297 /* 1298 * Report the devices as separate nodes so we can mark one as 1299 * only visible to the secure world. 1300 */ 1301 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1302 qemu_fdt_add_subnode(ms->fdt, nodename); 1303 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1304 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1305 2, flashbase, 2, flashsize); 1306 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1307 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1308 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1309 g_free(nodename); 1310 1311 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1312 qemu_fdt_add_subnode(ms->fdt, nodename); 1313 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1314 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1315 2, flashbase + flashsize, 2, flashsize); 1316 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1317 g_free(nodename); 1318 } 1319 } 1320 1321 static bool virt_firmware_init(VirtMachineState *vms, 1322 MemoryRegion *sysmem, 1323 MemoryRegion *secure_sysmem) 1324 { 1325 int i; 1326 const char *bios_name; 1327 BlockBackend *pflash_blk0; 1328 1329 /* Map legacy -drive if=pflash to machine properties */ 1330 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1331 pflash_cfi01_legacy_drive(vms->flash[i], 1332 drive_get(IF_PFLASH, 0, i)); 1333 } 1334 1335 virt_flash_map(vms, sysmem, secure_sysmem); 1336 1337 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1338 1339 bios_name = MACHINE(vms)->firmware; 1340 if (bios_name) { 1341 char *fname; 1342 MemoryRegion *mr; 1343 int image_size; 1344 1345 if (pflash_blk0) { 1346 error_report("The contents of the first flash device may be " 1347 "specified with -bios or with -drive if=pflash... " 1348 "but you cannot use both options at once"); 1349 exit(1); 1350 } 1351 1352 /* Fall back to -bios */ 1353 1354 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1355 if (!fname) { 1356 error_report("Could not find ROM image '%s'", bios_name); 1357 exit(1); 1358 } 1359 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1360 image_size = load_image_mr(fname, mr); 1361 g_free(fname); 1362 if (image_size < 0) { 1363 error_report("Could not load ROM image '%s'", bios_name); 1364 exit(1); 1365 } 1366 } 1367 1368 return pflash_blk0 || bios_name; 1369 } 1370 1371 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1372 { 1373 MachineState *ms = MACHINE(vms); 1374 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1375 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1376 FWCfgState *fw_cfg; 1377 char *nodename; 1378 1379 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1380 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1381 1382 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1383 qemu_fdt_add_subnode(ms->fdt, nodename); 1384 qemu_fdt_setprop_string(ms->fdt, nodename, 1385 "compatible", "qemu,fw-cfg-mmio"); 1386 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1387 2, base, 2, size); 1388 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1389 g_free(nodename); 1390 return fw_cfg; 1391 } 1392 1393 static void create_pcie_irq_map(const MachineState *ms, 1394 uint32_t gic_phandle, 1395 int first_irq, const char *nodename) 1396 { 1397 int devfn, pin; 1398 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1399 uint32_t *irq_map = full_irq_map; 1400 1401 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1402 for (pin = 0; pin < 4; pin++) { 1403 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1404 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1405 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1406 int i; 1407 1408 uint32_t map[] = { 1409 devfn << 8, 0, 0, /* devfn */ 1410 pin + 1, /* PCI pin */ 1411 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1412 1413 /* Convert map to big endian */ 1414 for (i = 0; i < 10; i++) { 1415 irq_map[i] = cpu_to_be32(map[i]); 1416 } 1417 irq_map += 10; 1418 } 1419 } 1420 1421 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1422 full_irq_map, sizeof(full_irq_map)); 1423 1424 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1425 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1426 0, 0, 1427 0x7 /* PCI irq */); 1428 } 1429 1430 static void create_smmu(const VirtMachineState *vms, 1431 PCIBus *bus) 1432 { 1433 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1434 char *node; 1435 const char compat[] = "arm,smmu-v3"; 1436 int irq = vms->irqmap[VIRT_SMMU]; 1437 int i; 1438 hwaddr base = vms->memmap[VIRT_SMMU].base; 1439 hwaddr size = vms->memmap[VIRT_SMMU].size; 1440 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1441 DeviceState *dev; 1442 MachineState *ms = MACHINE(vms); 1443 1444 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1445 return; 1446 } 1447 1448 dev = qdev_new(TYPE_ARM_SMMUV3); 1449 1450 if (!vmc->no_nested_smmu) { 1451 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal); 1452 } 1453 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1454 &error_abort); 1455 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1456 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1457 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1458 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1459 qdev_get_gpio_in(vms->gic, irq + i)); 1460 } 1461 1462 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1463 qemu_fdt_add_subnode(ms->fdt, node); 1464 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1465 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1466 1467 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1468 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1469 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1470 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1471 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1472 1473 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1474 sizeof(irq_names)); 1475 1476 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1477 1478 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1479 1480 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1481 g_free(node); 1482 } 1483 1484 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1485 { 1486 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1487 uint16_t bdf = vms->virtio_iommu_bdf; 1488 MachineState *ms = MACHINE(vms); 1489 char *node; 1490 1491 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1492 1493 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1494 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1495 qemu_fdt_add_subnode(ms->fdt, node); 1496 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1497 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1498 1, bdf << 8, 1, 0, 1, 0, 1499 1, 0, 1, 0); 1500 1501 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1502 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1503 g_free(node); 1504 1505 if (!vms->default_bus_bypass_iommu) { 1506 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1507 0x0, vms->iommu_phandle, 0x0, bdf, 1508 bdf + 1, vms->iommu_phandle, bdf + 1, 1509 0xffff - bdf); 1510 } 1511 } 1512 1513 static void create_pcie(VirtMachineState *vms) 1514 { 1515 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1516 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1517 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1518 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1519 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1520 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1521 hwaddr base_ecam, size_ecam; 1522 hwaddr base = base_mmio; 1523 int nr_pcie_buses; 1524 int irq = vms->irqmap[VIRT_PCIE]; 1525 MemoryRegion *mmio_alias; 1526 MemoryRegion *mmio_reg; 1527 MemoryRegion *ecam_alias; 1528 MemoryRegion *ecam_reg; 1529 DeviceState *dev; 1530 char *nodename; 1531 int i, ecam_id; 1532 PCIHostState *pci; 1533 MachineState *ms = MACHINE(vms); 1534 MachineClass *mc = MACHINE_GET_CLASS(ms); 1535 1536 dev = qdev_new(TYPE_GPEX_HOST); 1537 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1538 1539 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1540 base_ecam = vms->memmap[ecam_id].base; 1541 size_ecam = vms->memmap[ecam_id].size; 1542 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1543 /* Map only the first size_ecam bytes of ECAM space */ 1544 ecam_alias = g_new0(MemoryRegion, 1); 1545 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1546 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1547 ecam_reg, 0, size_ecam); 1548 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1549 1550 /* Map the MMIO window into system address space so as to expose 1551 * the section of PCI MMIO space which starts at the same base address 1552 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1553 * the window). 1554 */ 1555 mmio_alias = g_new0(MemoryRegion, 1); 1556 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1557 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1558 mmio_reg, base_mmio, size_mmio); 1559 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1560 1561 if (vms->highmem_mmio) { 1562 /* Map high MMIO space */ 1563 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1564 1565 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1566 mmio_reg, base_mmio_high, size_mmio_high); 1567 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1568 high_mmio_alias); 1569 } 1570 1571 /* Map IO port space */ 1572 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1573 1574 for (i = 0; i < PCI_NUM_PINS; i++) { 1575 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1576 qdev_get_gpio_in(vms->gic, irq + i)); 1577 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1578 } 1579 1580 pci = PCI_HOST_BRIDGE(dev); 1581 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1582 vms->bus = pci->bus; 1583 if (vms->bus) { 1584 pci_init_nic_devices(pci->bus, mc->default_nic); 1585 } 1586 1587 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1588 qemu_fdt_add_subnode(ms->fdt, nodename); 1589 qemu_fdt_setprop_string(ms->fdt, nodename, 1590 "compatible", "pci-host-ecam-generic"); 1591 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1593 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1594 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1595 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1596 nr_pcie_buses - 1); 1597 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1598 1599 if (vms->msi_phandle) { 1600 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1601 0, vms->msi_phandle, 0, 0x10000); 1602 } 1603 1604 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1605 2, base_ecam, 2, size_ecam); 1606 1607 if (vms->highmem_mmio) { 1608 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1609 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1610 2, base_pio, 2, size_pio, 1611 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1612 2, base_mmio, 2, size_mmio, 1613 1, FDT_PCI_RANGE_MMIO_64BIT, 1614 2, base_mmio_high, 1615 2, base_mmio_high, 2, size_mmio_high); 1616 } else { 1617 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1618 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1619 2, base_pio, 2, size_pio, 1620 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1621 2, base_mmio, 2, size_mmio); 1622 } 1623 1624 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1625 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1626 1627 if (vms->iommu) { 1628 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1629 1630 switch (vms->iommu) { 1631 case VIRT_IOMMU_SMMUV3: 1632 create_smmu(vms, vms->bus); 1633 if (!vms->default_bus_bypass_iommu) { 1634 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1635 0x0, vms->iommu_phandle, 0x0, 0x10000); 1636 } 1637 break; 1638 default: 1639 g_assert_not_reached(); 1640 } 1641 } 1642 } 1643 1644 static void create_cxl_host_reg_region(VirtMachineState *vms) 1645 { 1646 MemoryRegion *sysmem = get_system_memory(); 1647 MemoryRegion *mr = &vms->cxl_devices_state.host_mr; 1648 1649 memory_region_init(mr, OBJECT(vms), "cxl_host_reg", 1650 vms->memmap[VIRT_CXL_HOST].size); 1651 memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr); 1652 vms->highmem_cxl = true; 1653 } 1654 1655 static void create_platform_bus(VirtMachineState *vms) 1656 { 1657 DeviceState *dev; 1658 SysBusDevice *s; 1659 int i; 1660 MemoryRegion *sysmem = get_system_memory(); 1661 1662 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1663 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1664 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1665 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1666 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1667 vms->platform_bus_dev = dev; 1668 1669 s = SYS_BUS_DEVICE(dev); 1670 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1671 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1672 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1673 } 1674 1675 memory_region_add_subregion(sysmem, 1676 vms->memmap[VIRT_PLATFORM_BUS].base, 1677 sysbus_mmio_get_region(s, 0)); 1678 } 1679 1680 static void create_tag_ram(MemoryRegion *tag_sysmem, 1681 hwaddr base, hwaddr size, 1682 const char *name) 1683 { 1684 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1685 1686 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1687 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1688 } 1689 1690 static void create_secure_ram(VirtMachineState *vms, 1691 MemoryRegion *secure_sysmem, 1692 MemoryRegion *secure_tag_sysmem) 1693 { 1694 MemoryRegion *secram = g_new(MemoryRegion, 1); 1695 char *nodename; 1696 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1697 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1698 MachineState *ms = MACHINE(vms); 1699 1700 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1701 &error_fatal); 1702 memory_region_add_subregion(secure_sysmem, base, secram); 1703 1704 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1705 qemu_fdt_add_subnode(ms->fdt, nodename); 1706 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1707 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1708 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1709 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1710 1711 if (secure_tag_sysmem) { 1712 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1713 } 1714 1715 g_free(nodename); 1716 } 1717 1718 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1719 { 1720 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1721 bootinfo); 1722 MachineState *ms = MACHINE(board); 1723 1724 1725 *fdt_size = board->fdt_size; 1726 return ms->fdt; 1727 } 1728 1729 static void virt_build_smbios(VirtMachineState *vms) 1730 { 1731 MachineClass *mc = MACHINE_GET_CLASS(vms); 1732 MachineState *ms = MACHINE(vms); 1733 uint8_t *smbios_tables, *smbios_anchor; 1734 size_t smbios_tables_len, smbios_anchor_len; 1735 struct smbios_phys_mem_area mem_array; 1736 const char *product = "QEMU Virtual Machine"; 1737 1738 if (kvm_enabled()) { 1739 product = "KVM Virtual Machine"; 1740 } 1741 1742 smbios_set_defaults("QEMU", product, mc->name); 1743 1744 /* build the array of physical mem area from base_memmap */ 1745 mem_array.address = vms->memmap[VIRT_MEM].base; 1746 mem_array.length = ms->ram_size; 1747 1748 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1, 1749 &smbios_tables, &smbios_tables_len, 1750 &smbios_anchor, &smbios_anchor_len, 1751 &error_fatal); 1752 1753 if (smbios_anchor) { 1754 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1755 smbios_tables, smbios_tables_len); 1756 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1757 smbios_anchor, smbios_anchor_len); 1758 } 1759 } 1760 1761 static 1762 void virt_machine_done(Notifier *notifier, void *data) 1763 { 1764 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1765 machine_done); 1766 MachineState *ms = MACHINE(vms); 1767 ARMCPU *cpu = ARM_CPU(first_cpu); 1768 struct arm_boot_info *info = &vms->bootinfo; 1769 AddressSpace *as = arm_boot_address_space(cpu, info); 1770 1771 cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, 1772 &error_fatal); 1773 1774 if (vms->cxl_devices_state.is_enabled) { 1775 cxl_fmws_link_targets(&error_fatal); 1776 } 1777 /* 1778 * If the user provided a dtb, we assume the dynamic sysbus nodes 1779 * already are integrated there. This corresponds to a use case where 1780 * the dynamic sysbus nodes are complex and their generation is not yet 1781 * supported. In that case the user can take charge of the guest dt 1782 * while qemu takes charge of the qom stuff. 1783 */ 1784 if (info->dtb_filename == NULL) { 1785 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1786 vms->memmap[VIRT_PLATFORM_BUS].base, 1787 vms->memmap[VIRT_PLATFORM_BUS].size, 1788 vms->irqmap[VIRT_PLATFORM_BUS]); 1789 } 1790 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) { 1791 exit(1); 1792 } 1793 1794 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, 1795 &error_abort); 1796 1797 virt_acpi_setup(vms); 1798 virt_build_smbios(vms); 1799 } 1800 1801 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1802 { 1803 uint8_t clustersz; 1804 1805 /* 1806 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts) 1807 * and to improve SGI efficiency. 1808 */ 1809 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1810 clustersz = GIC_TARGETLIST_BITS; 1811 } else { 1812 clustersz = GICV3_TARGETLIST_BITS; 1813 } 1814 1815 return arm_build_mp_affinity(idx, clustersz); 1816 } 1817 1818 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1819 int index) 1820 { 1821 bool *enabled_array[] = { 1822 &vms->highmem_redists, 1823 &vms->highmem_cxl, 1824 &vms->highmem_ecam, 1825 &vms->highmem_mmio, 1826 }; 1827 1828 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1829 ARRAY_SIZE(enabled_array)); 1830 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1831 1832 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1833 } 1834 1835 static void virt_set_high_memmap(VirtMachineState *vms, 1836 hwaddr base, int pa_bits) 1837 { 1838 hwaddr region_base, region_size; 1839 bool *region_enabled, fits; 1840 int i; 1841 1842 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1843 region_enabled = virt_get_high_memmap_enabled(vms, i); 1844 region_base = ROUND_UP(base, extended_memmap[i].size); 1845 region_size = extended_memmap[i].size; 1846 1847 vms->memmap[i].base = region_base; 1848 vms->memmap[i].size = region_size; 1849 1850 /* 1851 * Check each device to see if it fits in the PA space, 1852 * moving highest_gpa as we go. For compatibility, move 1853 * highest_gpa for disabled fitting devices as well, if 1854 * the compact layout has been disabled. 1855 * 1856 * For each device that doesn't fit, disable it. 1857 */ 1858 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1859 *region_enabled &= fits; 1860 if (vms->highmem_compact && !*region_enabled) { 1861 continue; 1862 } 1863 1864 base = region_base + region_size; 1865 if (fits) { 1866 vms->highest_gpa = base - 1; 1867 } 1868 } 1869 } 1870 1871 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1872 { 1873 MachineState *ms = MACHINE(vms); 1874 hwaddr base, device_memory_base, device_memory_size, memtop; 1875 int i; 1876 1877 vms->memmap = extended_memmap; 1878 1879 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1880 vms->memmap[i] = base_memmap[i]; 1881 } 1882 1883 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1884 error_report("unsupported number of memory slots: %"PRIu64, 1885 ms->ram_slots); 1886 exit(EXIT_FAILURE); 1887 } 1888 1889 /* 1890 * !highmem is exactly the same as limiting the PA space to 32bit, 1891 * irrespective of the underlying capabilities of the HW. 1892 */ 1893 if (!vms->highmem) { 1894 pa_bits = 32; 1895 } 1896 1897 /* 1898 * We compute the base of the high IO region depending on the 1899 * amount of initial and device memory. The device memory start/size 1900 * is aligned on 1GiB. We never put the high IO region below 256GiB 1901 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1902 * The device region size assumes 1GiB page max alignment per slot. 1903 */ 1904 device_memory_base = 1905 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1906 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1907 1908 /* Base address of the high IO region */ 1909 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1910 if (memtop > BIT_ULL(pa_bits)) { 1911 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1912 pa_bits, memtop - BIT_ULL(pa_bits)); 1913 exit(EXIT_FAILURE); 1914 } 1915 if (base < device_memory_base) { 1916 error_report("maxmem/slots too huge"); 1917 exit(EXIT_FAILURE); 1918 } 1919 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1920 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1921 } 1922 1923 /* We know for sure that at least the memory fits in the PA space */ 1924 vms->highest_gpa = memtop - 1; 1925 1926 virt_set_high_memmap(vms, base, pa_bits); 1927 1928 if (device_memory_size > 0) { 1929 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1930 } 1931 vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1, 1932 256 * MiB), 1933 BIT_ULL(pa_bits)) - 1; 1934 } 1935 1936 static VirtGICType finalize_gic_version_do(const char *accel_name, 1937 VirtGICType gic_version, 1938 int gics_supported, 1939 unsigned int max_cpus) 1940 { 1941 /* Convert host/max/nosel to GIC version number */ 1942 switch (gic_version) { 1943 case VIRT_GIC_VERSION_HOST: 1944 if (!kvm_enabled()) { 1945 error_report("gic-version=host requires KVM"); 1946 exit(1); 1947 } 1948 1949 /* For KVM, gic-version=host means gic-version=max */ 1950 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1951 gics_supported, max_cpus); 1952 case VIRT_GIC_VERSION_MAX: 1953 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1954 gic_version = VIRT_GIC_VERSION_4; 1955 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1956 gic_version = VIRT_GIC_VERSION_3; 1957 } else { 1958 gic_version = VIRT_GIC_VERSION_2; 1959 } 1960 break; 1961 case VIRT_GIC_VERSION_NOSEL: 1962 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1963 max_cpus <= GIC_NCPU) { 1964 gic_version = VIRT_GIC_VERSION_2; 1965 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1966 /* 1967 * in case the host does not support v2 emulation or 1968 * the end-user requested more than 8 VCPUs we now default 1969 * to v3. In any case defaulting to v2 would be broken. 1970 */ 1971 gic_version = VIRT_GIC_VERSION_3; 1972 } else if (max_cpus > GIC_NCPU) { 1973 error_report("%s only supports GICv2 emulation but more than 8 " 1974 "vcpus are requested", accel_name); 1975 exit(1); 1976 } 1977 break; 1978 case VIRT_GIC_VERSION_2: 1979 case VIRT_GIC_VERSION_3: 1980 case VIRT_GIC_VERSION_4: 1981 break; 1982 } 1983 1984 /* Check chosen version is effectively supported */ 1985 switch (gic_version) { 1986 case VIRT_GIC_VERSION_2: 1987 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1988 error_report("%s does not support GICv2 emulation", accel_name); 1989 exit(1); 1990 } 1991 break; 1992 case VIRT_GIC_VERSION_3: 1993 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1994 error_report("%s does not support GICv3 emulation", accel_name); 1995 exit(1); 1996 } 1997 break; 1998 case VIRT_GIC_VERSION_4: 1999 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 2000 error_report("%s does not support GICv4 emulation, is virtualization=on?", 2001 accel_name); 2002 exit(1); 2003 } 2004 break; 2005 default: 2006 error_report("logic error in finalize_gic_version"); 2007 exit(1); 2008 break; 2009 } 2010 2011 return gic_version; 2012 } 2013 2014 /* 2015 * finalize_gic_version - Determines the final gic_version 2016 * according to the gic-version property 2017 * 2018 * Default GIC type is v2 2019 */ 2020 static void finalize_gic_version(VirtMachineState *vms) 2021 { 2022 const char *accel_name = current_accel_name(); 2023 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 2024 int gics_supported = 0; 2025 2026 /* Determine which GIC versions the current environment supports */ 2027 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 2028 int probe_bitmap = kvm_arm_vgic_probe(); 2029 2030 if (!probe_bitmap) { 2031 error_report("Unable to determine GIC version supported by host"); 2032 exit(1); 2033 } 2034 2035 if (probe_bitmap & KVM_ARM_VGIC_V2) { 2036 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2037 } 2038 if (probe_bitmap & KVM_ARM_VGIC_V3) { 2039 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2040 } 2041 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 2042 /* KVM w/o kernel irqchip can only deal with GICv2 */ 2043 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2044 accel_name = "KVM with kernel-irqchip=off"; 2045 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 2046 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2047 if (module_object_class_by_name("arm-gicv3")) { 2048 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2049 if (vms->virt) { 2050 /* GICv4 only makes sense if CPU has EL2 */ 2051 gics_supported |= VIRT_GIC_VERSION_4_MASK; 2052 } 2053 } 2054 } else { 2055 error_report("Unsupported accelerator, can not determine GIC support"); 2056 exit(1); 2057 } 2058 2059 /* 2060 * Then convert helpers like host/max to concrete GIC versions and ensure 2061 * the desired version is supported 2062 */ 2063 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 2064 gics_supported, max_cpus); 2065 } 2066 2067 /* 2068 * virt_post_cpus_gic_realized() must be called after the CPUs and 2069 * the GIC have both been realized. 2070 */ 2071 static void virt_post_cpus_gic_realized(VirtMachineState *vms, 2072 MemoryRegion *sysmem) 2073 { 2074 int max_cpus = MACHINE(vms)->smp.max_cpus; 2075 bool aarch64, pmu, steal_time; 2076 CPUState *cpu; 2077 2078 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 2079 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 2080 steal_time = object_property_get_bool(OBJECT(first_cpu), 2081 "kvm-steal-time", NULL); 2082 2083 if (kvm_enabled()) { 2084 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 2085 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 2086 2087 if (steal_time) { 2088 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 2089 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 2090 2091 /* The memory region size must be a multiple of host page size. */ 2092 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 2093 2094 if (pvtime_size > pvtime_reg_size) { 2095 error_report("pvtime requires a %" HWADDR_PRId 2096 " byte memory region for %d CPUs," 2097 " but only %" HWADDR_PRId " has been reserved", 2098 pvtime_size, max_cpus, pvtime_reg_size); 2099 exit(1); 2100 } 2101 2102 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 2103 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 2104 } 2105 if (!aarch64 && vms->virt) { 2106 error_report("KVM does not support EL2 on an AArch32 vCPU"); 2107 exit(1); 2108 } 2109 2110 CPU_FOREACH(cpu) { 2111 if (pmu) { 2112 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 2113 if (kvm_irqchip_in_kernel()) { 2114 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 2115 } 2116 kvm_arm_pmu_init(ARM_CPU(cpu)); 2117 } 2118 if (steal_time) { 2119 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 2120 + cpu->cpu_index 2121 * PVTIME_SIZE_PER_CPU); 2122 } 2123 } 2124 } else { 2125 if (aarch64 && vms->highmem) { 2126 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2127 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2128 2129 if (pamax < requested_pa_size) { 2130 error_report("VCPU supports less PA bits (%d) than " 2131 "requested by the memory map (%d)", 2132 pamax, requested_pa_size); 2133 exit(1); 2134 } 2135 } 2136 } 2137 } 2138 2139 static void machvirt_init(MachineState *machine) 2140 { 2141 VirtMachineState *vms = VIRT_MACHINE(machine); 2142 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2143 MachineClass *mc = MACHINE_GET_CLASS(machine); 2144 const CPUArchIdList *possible_cpus; 2145 MemoryRegion *sysmem = get_system_memory(); 2146 MemoryRegion *secure_sysmem = NULL; 2147 MemoryRegion *tag_sysmem = NULL; 2148 MemoryRegion *secure_tag_sysmem = NULL; 2149 int n, virt_max_cpus; 2150 bool firmware_loaded; 2151 bool aarch64 = true; 2152 bool has_ged = !vmc->no_ged; 2153 unsigned int smp_cpus = machine->smp.cpus; 2154 unsigned int max_cpus = machine->smp.max_cpus; 2155 2156 possible_cpus = mc->possible_cpu_arch_ids(machine); 2157 2158 /* 2159 * In accelerated mode, the memory map is computed earlier in kvm_type() 2160 * for Linux, or hvf_get_physical_address_range() for macOS to create a 2161 * VM with the right number of IPA bits. 2162 */ 2163 if (!vms->memmap) { 2164 Object *cpuobj; 2165 ARMCPU *armcpu; 2166 int pa_bits; 2167 2168 /* 2169 * Instantiate a temporary CPU object to find out about what 2170 * we are about to deal with. Once this is done, get rid of 2171 * the object. 2172 */ 2173 cpuobj = object_new(possible_cpus->cpus[0].type); 2174 armcpu = ARM_CPU(cpuobj); 2175 2176 pa_bits = arm_pamax(armcpu); 2177 2178 object_unref(cpuobj); 2179 2180 virt_set_memmap(vms, pa_bits); 2181 } 2182 2183 /* We can probe only here because during property set 2184 * KVM is not available yet 2185 */ 2186 finalize_gic_version(vms); 2187 2188 if (vms->secure) { 2189 /* 2190 * The Secure view of the world is the same as the NonSecure, 2191 * but with a few extra devices. Create it as a container region 2192 * containing the system memory at low priority; any secure-only 2193 * devices go in at higher priority and take precedence. 2194 */ 2195 secure_sysmem = g_new(MemoryRegion, 1); 2196 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2197 UINT64_MAX); 2198 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2199 } 2200 2201 firmware_loaded = virt_firmware_init(vms, sysmem, 2202 secure_sysmem ?: sysmem); 2203 2204 /* If we have an EL3 boot ROM then the assumption is that it will 2205 * implement PSCI itself, so disable QEMU's internal implementation 2206 * so it doesn't get in the way. Instead of starting secondary 2207 * CPUs in PSCI powerdown state we will start them all running and 2208 * let the boot ROM sort them out. 2209 * The usual case is that we do use QEMU's PSCI implementation; 2210 * if the guest has EL2 then we will use SMC as the conduit, 2211 * and otherwise we will use HVC (for backwards compatibility and 2212 * because if we're using KVM then we must use HVC). 2213 */ 2214 if (vms->secure && firmware_loaded) { 2215 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2216 } else if (vms->virt) { 2217 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2218 } else { 2219 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2220 } 2221 2222 /* 2223 * The maximum number of CPUs depends on the GIC version, or on how 2224 * many redistributors we can fit into the memory map (which in turn 2225 * depends on whether this is a GICv3 or v4). 2226 */ 2227 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2228 virt_max_cpus = GIC_NCPU; 2229 } else { 2230 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2231 if (vms->highmem_redists) { 2232 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2233 } 2234 } 2235 2236 if (max_cpus > virt_max_cpus) { 2237 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2238 "supported by machine 'mach-virt' (%d)", 2239 max_cpus, virt_max_cpus); 2240 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2241 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2242 } 2243 2244 exit(1); 2245 } 2246 2247 if (vms->secure && !tcg_enabled() && !qtest_enabled()) { 2248 error_report("mach-virt: %s does not support providing " 2249 "Security extensions (TrustZone) to the guest CPU", 2250 current_accel_name()); 2251 exit(1); 2252 } 2253 2254 if (vms->virt && kvm_enabled() && !kvm_arm_el2_supported()) { 2255 error_report("mach-virt: host kernel KVM does not support providing " 2256 "Virtualization extensions to the guest CPU"); 2257 exit(1); 2258 } 2259 2260 if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled()) { 2261 error_report("mach-virt: %s does not support providing " 2262 "Virtualization extensions to the guest CPU", 2263 current_accel_name()); 2264 exit(1); 2265 } 2266 2267 if (vms->mte && hvf_enabled()) { 2268 error_report("mach-virt: %s does not support providing " 2269 "MTE to the guest CPU", 2270 current_accel_name()); 2271 exit(1); 2272 } 2273 2274 create_fdt(vms); 2275 2276 assert(possible_cpus->len == max_cpus); 2277 for (n = 0; n < possible_cpus->len; n++) { 2278 Object *cpuobj; 2279 CPUState *cs; 2280 2281 if (n >= smp_cpus) { 2282 break; 2283 } 2284 2285 cpuobj = object_new(possible_cpus->cpus[n].type); 2286 object_property_set_int(cpuobj, "mp-affinity", 2287 possible_cpus->cpus[n].arch_id, NULL); 2288 2289 cs = CPU(cpuobj); 2290 cs->cpu_index = n; 2291 2292 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2293 &error_fatal); 2294 2295 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2296 2297 if (!vms->secure) { 2298 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2299 } 2300 2301 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2302 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2303 } 2304 2305 if (vmc->kvm_no_adjvtime && 2306 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2307 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2308 } 2309 2310 if (vmc->no_kvm_steal_time && 2311 object_property_find(cpuobj, "kvm-steal-time")) { 2312 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2313 } 2314 2315 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2316 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2317 } 2318 2319 if (object_property_find(cpuobj, "reset-cbar")) { 2320 object_property_set_int(cpuobj, "reset-cbar", 2321 vms->memmap[VIRT_CPUPERIPHS].base, 2322 &error_abort); 2323 } 2324 2325 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2326 &error_abort); 2327 if (vms->secure) { 2328 object_property_set_link(cpuobj, "secure-memory", 2329 OBJECT(secure_sysmem), &error_abort); 2330 } 2331 2332 if (vms->mte) { 2333 if (tcg_enabled()) { 2334 /* Create the memory region only once, but link to all cpus. */ 2335 if (!tag_sysmem) { 2336 /* 2337 * The property exists only if MemTag is supported. 2338 * If it is, we must allocate the ram to back that up. 2339 */ 2340 if (!object_property_find(cpuobj, "tag-memory")) { 2341 error_report("MTE requested, but not supported " 2342 "by the guest CPU"); 2343 exit(1); 2344 } 2345 2346 tag_sysmem = g_new(MemoryRegion, 1); 2347 memory_region_init(tag_sysmem, OBJECT(machine), 2348 "tag-memory", UINT64_MAX / 32); 2349 2350 if (vms->secure) { 2351 secure_tag_sysmem = g_new(MemoryRegion, 1); 2352 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2353 "secure-tag-memory", 2354 UINT64_MAX / 32); 2355 2356 /* As with ram, secure-tag takes precedence over tag. */ 2357 memory_region_add_subregion_overlap(secure_tag_sysmem, 2358 0, tag_sysmem, -1); 2359 } 2360 } 2361 2362 object_property_set_link(cpuobj, "tag-memory", 2363 OBJECT(tag_sysmem), &error_abort); 2364 if (vms->secure) { 2365 object_property_set_link(cpuobj, "secure-tag-memory", 2366 OBJECT(secure_tag_sysmem), 2367 &error_abort); 2368 } 2369 } else if (kvm_enabled()) { 2370 if (!kvm_arm_mte_supported()) { 2371 error_report("MTE requested, but not supported by KVM"); 2372 exit(1); 2373 } 2374 kvm_arm_enable_mte(cpuobj, &error_abort); 2375 } else { 2376 error_report("MTE requested, but not supported "); 2377 exit(1); 2378 } 2379 } 2380 2381 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2382 object_unref(cpuobj); 2383 } 2384 2385 /* Now we've created the CPUs we can see if they have the hypvirt timer */ 2386 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && 2387 !vmc->no_ns_el2_virt_timer_irq; 2388 2389 fdt_add_timer_nodes(vms); 2390 fdt_add_cpu_nodes(vms); 2391 2392 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2393 machine->ram); 2394 2395 cxl_fmws_update_mmio(); 2396 2397 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2398 2399 create_gic(vms, sysmem); 2400 2401 virt_post_cpus_gic_realized(vms, sysmem); 2402 2403 fdt_add_pmu_nodes(vms); 2404 2405 /* 2406 * The first UART always exists. If the security extensions are 2407 * enabled, the second UART also always exists. Otherwise, it only exists 2408 * if a backend is configured explicitly via '-serial <backend>'. 2409 * This avoids potentially breaking existing user setups that expect 2410 * only one NonSecure UART to be present (for instance, older EDK2 2411 * binaries). 2412 * 2413 * The nodes end up in the DTB in reverse order of creation, so we must 2414 * create UART0 last to ensure it appears as the first node in the DTB, 2415 * for compatibility with guest software that just iterates through the 2416 * DTB to find the first UART, as older versions of EDK2 do. 2417 * DTB readers that follow the spec, as Linux does, should honour the 2418 * aliases node information and /chosen/stdout-path regardless of 2419 * the order that nodes appear in the DTB. 2420 * 2421 * For similar back-compatibility reasons, if UART1 is the secure UART 2422 * we create it second (and so it appears first in the DTB), because 2423 * that's what QEMU has always done. 2424 */ 2425 if (!vms->secure) { 2426 Chardev *serial1 = serial_hd(1); 2427 2428 if (serial1) { 2429 vms->second_ns_uart_present = true; 2430 create_uart(vms, VIRT_UART1, sysmem, serial1, false); 2431 } 2432 } 2433 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false); 2434 if (vms->secure) { 2435 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true); 2436 } 2437 2438 if (vms->secure) { 2439 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2440 } 2441 2442 if (tag_sysmem) { 2443 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2444 machine->ram_size, "mach-virt.tag"); 2445 } 2446 2447 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2448 2449 create_rtc(vms); 2450 2451 create_pcie(vms); 2452 create_cxl_host_reg_region(vms); 2453 2454 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2455 vms->acpi_dev = create_acpi_ged(vms); 2456 } else { 2457 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2458 } 2459 2460 if (vms->secure && !vmc->no_secure_gpio) { 2461 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2462 } 2463 2464 /* connect powerdown request */ 2465 vms->powerdown_notifier.notify = virt_powerdown_req; 2466 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2467 2468 /* Create mmio transports, so the user can create virtio backends 2469 * (which will be automatically plugged in to the transports). If 2470 * no backend is created the transport will just sit harmlessly idle. 2471 */ 2472 create_virtio_devices(vms); 2473 2474 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2475 rom_set_fw(vms->fw_cfg); 2476 2477 create_platform_bus(vms); 2478 2479 if (machine->nvdimms_state->is_enabled) { 2480 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2481 .space_id = AML_AS_SYSTEM_MEMORY, 2482 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2483 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2484 }; 2485 2486 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2487 arm_virt_nvdimm_acpi_dsmio, 2488 vms->fw_cfg, OBJECT(vms)); 2489 } 2490 2491 vms->bootinfo.ram_size = machine->ram_size; 2492 vms->bootinfo.board_id = -1; 2493 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2494 vms->bootinfo.get_dtb = machvirt_dtb; 2495 vms->bootinfo.skip_dtb_autoload = true; 2496 vms->bootinfo.firmware_loaded = firmware_loaded; 2497 vms->bootinfo.psci_conduit = vms->psci_conduit; 2498 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2499 2500 vms->machine_done.notify = virt_machine_done; 2501 qemu_add_machine_init_done_notifier(&vms->machine_done); 2502 } 2503 2504 static bool virt_get_secure(Object *obj, Error **errp) 2505 { 2506 VirtMachineState *vms = VIRT_MACHINE(obj); 2507 2508 return vms->secure; 2509 } 2510 2511 static void virt_set_secure(Object *obj, bool value, Error **errp) 2512 { 2513 VirtMachineState *vms = VIRT_MACHINE(obj); 2514 2515 vms->secure = value; 2516 } 2517 2518 static bool virt_get_virt(Object *obj, Error **errp) 2519 { 2520 VirtMachineState *vms = VIRT_MACHINE(obj); 2521 2522 return vms->virt; 2523 } 2524 2525 static void virt_set_virt(Object *obj, bool value, Error **errp) 2526 { 2527 VirtMachineState *vms = VIRT_MACHINE(obj); 2528 2529 vms->virt = value; 2530 } 2531 2532 static bool virt_get_highmem(Object *obj, Error **errp) 2533 { 2534 VirtMachineState *vms = VIRT_MACHINE(obj); 2535 2536 return vms->highmem; 2537 } 2538 2539 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2540 { 2541 VirtMachineState *vms = VIRT_MACHINE(obj); 2542 2543 vms->highmem = value; 2544 } 2545 2546 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2547 { 2548 VirtMachineState *vms = VIRT_MACHINE(obj); 2549 2550 return vms->highmem_compact; 2551 } 2552 2553 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2554 { 2555 VirtMachineState *vms = VIRT_MACHINE(obj); 2556 2557 vms->highmem_compact = value; 2558 } 2559 2560 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2561 { 2562 VirtMachineState *vms = VIRT_MACHINE(obj); 2563 2564 return vms->highmem_redists; 2565 } 2566 2567 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2568 { 2569 VirtMachineState *vms = VIRT_MACHINE(obj); 2570 2571 vms->highmem_redists = value; 2572 } 2573 2574 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2575 { 2576 VirtMachineState *vms = VIRT_MACHINE(obj); 2577 2578 return vms->highmem_ecam; 2579 } 2580 2581 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2582 { 2583 VirtMachineState *vms = VIRT_MACHINE(obj); 2584 2585 vms->highmem_ecam = value; 2586 } 2587 2588 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2589 { 2590 VirtMachineState *vms = VIRT_MACHINE(obj); 2591 2592 return vms->highmem_mmio; 2593 } 2594 2595 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2596 { 2597 VirtMachineState *vms = VIRT_MACHINE(obj); 2598 2599 vms->highmem_mmio = value; 2600 } 2601 2602 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, 2603 const char *name, void *opaque, 2604 Error **errp) 2605 { 2606 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size; 2607 2608 visit_type_size(v, name, &size, errp); 2609 } 2610 2611 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, 2612 const char *name, void *opaque, 2613 Error **errp) 2614 { 2615 uint64_t size; 2616 2617 if (!visit_type_size(v, name, &size, errp)) { 2618 return; 2619 } 2620 2621 if (!is_power_of_2(size)) { 2622 error_setg(errp, "highmem-mmio-size is not a power of 2"); 2623 return; 2624 } 2625 2626 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { 2627 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); 2628 error_setg(errp, "highmem-mmio-size cannot be set to a lower value " 2629 "than the default (%s)", sz); 2630 g_free(sz); 2631 return; 2632 } 2633 2634 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size; 2635 } 2636 2637 static bool virt_get_its(Object *obj, Error **errp) 2638 { 2639 VirtMachineState *vms = VIRT_MACHINE(obj); 2640 2641 return vms->its; 2642 } 2643 2644 static void virt_set_its(Object *obj, bool value, Error **errp) 2645 { 2646 VirtMachineState *vms = VIRT_MACHINE(obj); 2647 2648 vms->its = value; 2649 } 2650 2651 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2652 { 2653 VirtMachineState *vms = VIRT_MACHINE(obj); 2654 2655 return vms->dtb_randomness; 2656 } 2657 2658 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2659 { 2660 VirtMachineState *vms = VIRT_MACHINE(obj); 2661 2662 vms->dtb_randomness = value; 2663 } 2664 2665 static char *virt_get_oem_id(Object *obj, Error **errp) 2666 { 2667 VirtMachineState *vms = VIRT_MACHINE(obj); 2668 2669 return g_strdup(vms->oem_id); 2670 } 2671 2672 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2673 { 2674 VirtMachineState *vms = VIRT_MACHINE(obj); 2675 size_t len = strlen(value); 2676 2677 if (len > 6) { 2678 error_setg(errp, 2679 "User specified oem-id value is bigger than 6 bytes in size"); 2680 return; 2681 } 2682 2683 strncpy(vms->oem_id, value, 6); 2684 } 2685 2686 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2687 { 2688 VirtMachineState *vms = VIRT_MACHINE(obj); 2689 2690 return g_strdup(vms->oem_table_id); 2691 } 2692 2693 static void virt_set_oem_table_id(Object *obj, const char *value, 2694 Error **errp) 2695 { 2696 VirtMachineState *vms = VIRT_MACHINE(obj); 2697 size_t len = strlen(value); 2698 2699 if (len > 8) { 2700 error_setg(errp, 2701 "User specified oem-table-id value is bigger than 8 bytes in size"); 2702 return; 2703 } 2704 strncpy(vms->oem_table_id, value, 8); 2705 } 2706 2707 2708 bool virt_is_acpi_enabled(VirtMachineState *vms) 2709 { 2710 if (vms->acpi == ON_OFF_AUTO_OFF) { 2711 return false; 2712 } 2713 return true; 2714 } 2715 2716 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2717 void *opaque, Error **errp) 2718 { 2719 VirtMachineState *vms = VIRT_MACHINE(obj); 2720 OnOffAuto acpi = vms->acpi; 2721 2722 visit_type_OnOffAuto(v, name, &acpi, errp); 2723 } 2724 2725 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2726 void *opaque, Error **errp) 2727 { 2728 VirtMachineState *vms = VIRT_MACHINE(obj); 2729 2730 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2731 } 2732 2733 static bool virt_get_ras(Object *obj, Error **errp) 2734 { 2735 VirtMachineState *vms = VIRT_MACHINE(obj); 2736 2737 return vms->ras; 2738 } 2739 2740 static void virt_set_ras(Object *obj, bool value, Error **errp) 2741 { 2742 VirtMachineState *vms = VIRT_MACHINE(obj); 2743 2744 vms->ras = value; 2745 } 2746 2747 static bool virt_get_mte(Object *obj, Error **errp) 2748 { 2749 VirtMachineState *vms = VIRT_MACHINE(obj); 2750 2751 return vms->mte; 2752 } 2753 2754 static void virt_set_mte(Object *obj, bool value, Error **errp) 2755 { 2756 VirtMachineState *vms = VIRT_MACHINE(obj); 2757 2758 vms->mte = value; 2759 } 2760 2761 static char *virt_get_gic_version(Object *obj, Error **errp) 2762 { 2763 VirtMachineState *vms = VIRT_MACHINE(obj); 2764 const char *val; 2765 2766 switch (vms->gic_version) { 2767 case VIRT_GIC_VERSION_4: 2768 val = "4"; 2769 break; 2770 case VIRT_GIC_VERSION_3: 2771 val = "3"; 2772 break; 2773 default: 2774 val = "2"; 2775 break; 2776 } 2777 return g_strdup(val); 2778 } 2779 2780 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2781 { 2782 VirtMachineState *vms = VIRT_MACHINE(obj); 2783 2784 if (!strcmp(value, "4")) { 2785 vms->gic_version = VIRT_GIC_VERSION_4; 2786 } else if (!strcmp(value, "3")) { 2787 vms->gic_version = VIRT_GIC_VERSION_3; 2788 } else if (!strcmp(value, "2")) { 2789 vms->gic_version = VIRT_GIC_VERSION_2; 2790 } else if (!strcmp(value, "host")) { 2791 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2792 } else if (!strcmp(value, "max")) { 2793 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2794 } else { 2795 error_setg(errp, "Invalid gic-version value"); 2796 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2797 } 2798 } 2799 2800 static char *virt_get_iommu(Object *obj, Error **errp) 2801 { 2802 VirtMachineState *vms = VIRT_MACHINE(obj); 2803 2804 switch (vms->iommu) { 2805 case VIRT_IOMMU_NONE: 2806 return g_strdup("none"); 2807 case VIRT_IOMMU_SMMUV3: 2808 return g_strdup("smmuv3"); 2809 default: 2810 g_assert_not_reached(); 2811 } 2812 } 2813 2814 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2815 { 2816 VirtMachineState *vms = VIRT_MACHINE(obj); 2817 2818 if (!strcmp(value, "smmuv3")) { 2819 vms->iommu = VIRT_IOMMU_SMMUV3; 2820 } else if (!strcmp(value, "none")) { 2821 vms->iommu = VIRT_IOMMU_NONE; 2822 } else { 2823 error_setg(errp, "Invalid iommu value"); 2824 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2825 } 2826 } 2827 2828 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2829 { 2830 VirtMachineState *vms = VIRT_MACHINE(obj); 2831 2832 return vms->default_bus_bypass_iommu; 2833 } 2834 2835 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2836 Error **errp) 2837 { 2838 VirtMachineState *vms = VIRT_MACHINE(obj); 2839 2840 vms->default_bus_bypass_iommu = value; 2841 } 2842 2843 static CpuInstanceProperties 2844 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2845 { 2846 MachineClass *mc = MACHINE_GET_CLASS(ms); 2847 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2848 2849 assert(cpu_index < possible_cpus->len); 2850 return possible_cpus->cpus[cpu_index].props; 2851 } 2852 2853 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2854 { 2855 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2856 2857 return socket_id % ms->numa_state->num_nodes; 2858 } 2859 2860 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2861 { 2862 int n; 2863 unsigned int max_cpus = ms->smp.max_cpus; 2864 VirtMachineState *vms = VIRT_MACHINE(ms); 2865 MachineClass *mc = MACHINE_GET_CLASS(vms); 2866 2867 if (ms->possible_cpus) { 2868 assert(ms->possible_cpus->len == max_cpus); 2869 return ms->possible_cpus; 2870 } 2871 2872 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2873 sizeof(CPUArchId) * max_cpus); 2874 ms->possible_cpus->len = max_cpus; 2875 for (n = 0; n < ms->possible_cpus->len; n++) { 2876 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2877 ms->possible_cpus->cpus[n].arch_id = 2878 virt_cpu_mp_affinity(vms, n); 2879 2880 assert(!mc->smp_props.dies_supported); 2881 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2882 ms->possible_cpus->cpus[n].props.socket_id = 2883 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2884 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2885 ms->possible_cpus->cpus[n].props.cluster_id = 2886 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2887 ms->possible_cpus->cpus[n].props.has_core_id = true; 2888 ms->possible_cpus->cpus[n].props.core_id = 2889 (n / ms->smp.threads) % ms->smp.cores; 2890 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2891 ms->possible_cpus->cpus[n].props.thread_id = 2892 n % ms->smp.threads; 2893 } 2894 return ms->possible_cpus; 2895 } 2896 2897 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2898 Error **errp) 2899 { 2900 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2901 const MachineState *ms = MACHINE(hotplug_dev); 2902 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2903 2904 if (!vms->acpi_dev) { 2905 error_setg(errp, 2906 "memory hotplug is not enabled: missing acpi-ged device"); 2907 return; 2908 } 2909 2910 if (vms->mte) { 2911 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2912 return; 2913 } 2914 2915 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2916 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2917 return; 2918 } 2919 2920 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 2921 } 2922 2923 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2924 DeviceState *dev, Error **errp) 2925 { 2926 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2927 MachineState *ms = MACHINE(hotplug_dev); 2928 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2929 2930 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2931 2932 if (is_nvdimm) { 2933 nvdimm_plug(ms->nvdimms_state); 2934 } 2935 2936 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2937 dev, &error_abort); 2938 } 2939 2940 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2941 DeviceState *dev, Error **errp) 2942 { 2943 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2944 2945 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2946 virt_memory_pre_plug(hotplug_dev, dev, errp); 2947 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2948 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2949 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2950 hwaddr db_start = 0, db_end = 0; 2951 QList *reserved_regions; 2952 char *resv_prop_str; 2953 2954 if (vms->iommu != VIRT_IOMMU_NONE) { 2955 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2956 return; 2957 } 2958 2959 switch (vms->msi_controller) { 2960 case VIRT_MSI_CTRL_NONE: 2961 return; 2962 case VIRT_MSI_CTRL_ITS: 2963 /* GITS_TRANSLATER page */ 2964 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2965 db_end = base_memmap[VIRT_GIC_ITS].base + 2966 base_memmap[VIRT_GIC_ITS].size - 1; 2967 break; 2968 case VIRT_MSI_CTRL_GICV2M: 2969 /* MSI_SETSPI_NS page */ 2970 db_start = base_memmap[VIRT_GIC_V2M].base; 2971 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2972 break; 2973 } 2974 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2975 db_start, db_end, 2976 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2977 2978 reserved_regions = qlist_new(); 2979 qlist_append_str(reserved_regions, resv_prop_str); 2980 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2981 g_free(resv_prop_str); 2982 } 2983 } 2984 2985 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2986 DeviceState *dev, Error **errp) 2987 { 2988 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2989 2990 if (vms->platform_bus_dev) { 2991 MachineClass *mc = MACHINE_GET_CLASS(vms); 2992 2993 if (device_is_dynamic_sysbus(mc, dev)) { 2994 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2995 SYS_BUS_DEVICE(dev)); 2996 } 2997 } 2998 2999 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3000 virt_memory_plug(hotplug_dev, dev, errp); 3001 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3002 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 3003 } 3004 3005 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 3006 PCIDevice *pdev = PCI_DEVICE(dev); 3007 3008 vms->iommu = VIRT_IOMMU_VIRTIO; 3009 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 3010 create_virtio_iommu_dt_bindings(vms); 3011 } 3012 } 3013 3014 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 3015 DeviceState *dev, Error **errp) 3016 { 3017 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 3018 3019 if (!vms->acpi_dev) { 3020 error_setg(errp, 3021 "memory hotplug is not enabled: missing acpi-ged device"); 3022 return; 3023 } 3024 3025 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3026 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3027 return; 3028 } 3029 3030 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 3031 errp); 3032 } 3033 3034 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 3035 DeviceState *dev, Error **errp) 3036 { 3037 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 3038 Error *local_err = NULL; 3039 3040 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 3041 if (local_err) { 3042 goto out; 3043 } 3044 3045 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 3046 qdev_unrealize(dev); 3047 3048 out: 3049 error_propagate(errp, local_err); 3050 } 3051 3052 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 3053 DeviceState *dev, Error **errp) 3054 { 3055 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3056 virt_dimm_unplug_request(hotplug_dev, dev, errp); 3057 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3058 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 3059 errp); 3060 } else { 3061 error_setg(errp, "device unplug request for unsupported device" 3062 " type: %s", object_get_typename(OBJECT(dev))); 3063 } 3064 } 3065 3066 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 3067 DeviceState *dev, Error **errp) 3068 { 3069 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3070 virt_dimm_unplug(hotplug_dev, dev, errp); 3071 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3072 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 3073 } else { 3074 error_setg(errp, "virt: device unplug for unsupported device" 3075 " type: %s", object_get_typename(OBJECT(dev))); 3076 } 3077 } 3078 3079 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 3080 DeviceState *dev) 3081 { 3082 MachineClass *mc = MACHINE_GET_CLASS(machine); 3083 3084 if (device_is_dynamic_sysbus(mc, dev) || 3085 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3086 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 3087 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 3088 return HOTPLUG_HANDLER(machine); 3089 } 3090 return NULL; 3091 } 3092 3093 /* 3094 * for arm64 kvm_type [7-0] encodes the requested number of bits 3095 * in the IPA address space 3096 */ 3097 static int virt_kvm_type(MachineState *ms, const char *type_str) 3098 { 3099 VirtMachineState *vms = VIRT_MACHINE(ms); 3100 int max_vm_pa_size, requested_pa_size; 3101 bool fixed_ipa; 3102 3103 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 3104 3105 /* we freeze the memory map to compute the highest gpa */ 3106 virt_set_memmap(vms, max_vm_pa_size); 3107 3108 requested_pa_size = 64 - clz64(vms->highest_gpa); 3109 3110 /* 3111 * KVM requires the IPA size to be at least 32 bits. 3112 */ 3113 if (requested_pa_size < 32) { 3114 requested_pa_size = 32; 3115 } 3116 3117 if (requested_pa_size > max_vm_pa_size) { 3118 error_report("-m and ,maxmem option values " 3119 "require an IPA range (%d bits) larger than " 3120 "the one supported by the host (%d bits)", 3121 requested_pa_size, max_vm_pa_size); 3122 return -1; 3123 } 3124 /* 3125 * We return the requested PA log size, unless KVM only supports 3126 * the implicit legacy 40b IPA setting, in which case the kvm_type 3127 * must be 0. 3128 */ 3129 return fixed_ipa ? 0 : requested_pa_size; 3130 } 3131 3132 static int virt_hvf_get_physical_address_range(MachineState *ms) 3133 { 3134 VirtMachineState *vms = VIRT_MACHINE(ms); 3135 3136 int default_ipa_size = hvf_arm_get_default_ipa_bit_size(); 3137 int max_ipa_size = hvf_arm_get_max_ipa_bit_size(); 3138 3139 /* We freeze the memory map to compute the highest gpa */ 3140 virt_set_memmap(vms, max_ipa_size); 3141 3142 int requested_ipa_size = 64 - clz64(vms->highest_gpa); 3143 3144 /* 3145 * If we're <= the default IPA size just use the default. 3146 * If we're above the default but below the maximum, round up to 3147 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only 3148 * returns values that are valid ARM PARange values. 3149 */ 3150 if (requested_ipa_size <= default_ipa_size) { 3151 requested_ipa_size = default_ipa_size; 3152 } else if (requested_ipa_size <= max_ipa_size) { 3153 requested_ipa_size = max_ipa_size; 3154 } else { 3155 error_report("-m and ,maxmem option values " 3156 "require an IPA range (%d bits) larger than " 3157 "the one supported by the host (%d bits)", 3158 requested_ipa_size, max_ipa_size); 3159 return -1; 3160 } 3161 3162 return requested_ipa_size; 3163 } 3164 3165 static void virt_machine_class_init(ObjectClass *oc, const void *data) 3166 { 3167 MachineClass *mc = MACHINE_CLASS(oc); 3168 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3169 static const char * const valid_cpu_types[] = { 3170 #ifdef CONFIG_TCG 3171 ARM_CPU_TYPE_NAME("cortex-a7"), 3172 ARM_CPU_TYPE_NAME("cortex-a15"), 3173 #ifdef TARGET_AARCH64 3174 ARM_CPU_TYPE_NAME("cortex-a35"), 3175 ARM_CPU_TYPE_NAME("cortex-a55"), 3176 ARM_CPU_TYPE_NAME("cortex-a72"), 3177 ARM_CPU_TYPE_NAME("cortex-a76"), 3178 ARM_CPU_TYPE_NAME("cortex-a710"), 3179 ARM_CPU_TYPE_NAME("a64fx"), 3180 ARM_CPU_TYPE_NAME("neoverse-n1"), 3181 ARM_CPU_TYPE_NAME("neoverse-v1"), 3182 ARM_CPU_TYPE_NAME("neoverse-n2"), 3183 #endif /* TARGET_AARCH64 */ 3184 #endif /* CONFIG_TCG */ 3185 #ifdef TARGET_AARCH64 3186 ARM_CPU_TYPE_NAME("cortex-a53"), 3187 ARM_CPU_TYPE_NAME("cortex-a57"), 3188 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 3189 ARM_CPU_TYPE_NAME("host"), 3190 #endif /* CONFIG_KVM || CONFIG_HVF */ 3191 #endif /* TARGET_AARCH64 */ 3192 ARM_CPU_TYPE_NAME("max"), 3193 NULL 3194 }; 3195 3196 mc->init = machvirt_init; 3197 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 3198 * The value may be reduced later when we have more information about the 3199 * configuration of the particular instance. 3200 */ 3201 mc->max_cpus = 512; 3202 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3203 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3204 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3205 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3206 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 3207 #ifdef CONFIG_TPM 3208 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3209 #endif 3210 mc->block_default_type = IF_VIRTIO; 3211 mc->no_cdrom = 1; 3212 mc->pci_allow_0_address = true; 3213 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3214 mc->minimum_page_bits = 12; 3215 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3216 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3217 #ifdef CONFIG_TCG 3218 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3219 #else 3220 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3221 #endif 3222 mc->valid_cpu_types = valid_cpu_types; 3223 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3224 mc->kvm_type = virt_kvm_type; 3225 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; 3226 assert(!mc->get_hotplug_handler); 3227 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3228 hc->pre_plug = virt_machine_device_pre_plug_cb; 3229 hc->plug = virt_machine_device_plug_cb; 3230 hc->unplug_request = virt_machine_device_unplug_request_cb; 3231 hc->unplug = virt_machine_device_unplug_cb; 3232 mc->nvdimm_supported = true; 3233 mc->smp_props.clusters_supported = true; 3234 mc->auto_enable_numa_with_memhp = true; 3235 mc->auto_enable_numa_with_memdev = true; 3236 /* platform instead of architectural choice */ 3237 mc->cpu_cluster_has_numa_boundary = true; 3238 mc->default_ram_id = "mach-virt.ram"; 3239 mc->default_nic = "virtio-net-pci"; 3240 3241 object_class_property_add(oc, "acpi", "OnOffAuto", 3242 virt_get_acpi, virt_set_acpi, 3243 NULL, NULL); 3244 object_class_property_set_description(oc, "acpi", 3245 "Enable ACPI"); 3246 object_class_property_add_bool(oc, "secure", virt_get_secure, 3247 virt_set_secure); 3248 object_class_property_set_description(oc, "secure", 3249 "Set on/off to enable/disable the ARM " 3250 "Security Extensions (TrustZone)"); 3251 3252 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3253 virt_set_virt); 3254 object_class_property_set_description(oc, "virtualization", 3255 "Set on/off to enable/disable emulating a " 3256 "guest CPU which implements the ARM " 3257 "Virtualization Extensions"); 3258 3259 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3260 virt_set_highmem); 3261 object_class_property_set_description(oc, "highmem", 3262 "Set on/off to enable/disable using " 3263 "physical address space above 32 bits"); 3264 3265 object_class_property_add_bool(oc, "compact-highmem", 3266 virt_get_compact_highmem, 3267 virt_set_compact_highmem); 3268 object_class_property_set_description(oc, "compact-highmem", 3269 "Set on/off to enable/disable compact " 3270 "layout for high memory regions"); 3271 3272 object_class_property_add_bool(oc, "highmem-redists", 3273 virt_get_highmem_redists, 3274 virt_set_highmem_redists); 3275 object_class_property_set_description(oc, "highmem-redists", 3276 "Set on/off to enable/disable high " 3277 "memory region for GICv3 or GICv4 " 3278 "redistributor"); 3279 3280 object_class_property_add_bool(oc, "highmem-ecam", 3281 virt_get_highmem_ecam, 3282 virt_set_highmem_ecam); 3283 object_class_property_set_description(oc, "highmem-ecam", 3284 "Set on/off to enable/disable high " 3285 "memory region for PCI ECAM"); 3286 3287 object_class_property_add_bool(oc, "highmem-mmio", 3288 virt_get_highmem_mmio, 3289 virt_set_highmem_mmio); 3290 object_class_property_set_description(oc, "highmem-mmio", 3291 "Set on/off to enable/disable high " 3292 "memory region for PCI MMIO"); 3293 3294 object_class_property_add(oc, "highmem-mmio-size", "size", 3295 virt_get_highmem_mmio_size, 3296 virt_set_highmem_mmio_size, 3297 NULL, NULL); 3298 object_class_property_set_description(oc, "highmem-mmio-size", 3299 "Set the high memory region size " 3300 "for PCI MMIO"); 3301 3302 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3303 virt_set_gic_version); 3304 object_class_property_set_description(oc, "gic-version", 3305 "Set GIC version. " 3306 "Valid values are 2, 3, 4, host and max"); 3307 3308 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3309 object_class_property_set_description(oc, "iommu", 3310 "Set the IOMMU type. " 3311 "Valid values are none and smmuv3"); 3312 3313 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3314 virt_get_default_bus_bypass_iommu, 3315 virt_set_default_bus_bypass_iommu); 3316 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3317 "Set on/off to enable/disable " 3318 "bypass_iommu for default root bus"); 3319 3320 object_class_property_add_bool(oc, "ras", virt_get_ras, 3321 virt_set_ras); 3322 object_class_property_set_description(oc, "ras", 3323 "Set on/off to enable/disable reporting host memory errors " 3324 "to a KVM guest using ACPI and guest external abort exceptions"); 3325 3326 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3327 object_class_property_set_description(oc, "mte", 3328 "Set on/off to enable/disable emulating a " 3329 "guest CPU which implements the ARM " 3330 "Memory Tagging Extension"); 3331 3332 object_class_property_add_bool(oc, "its", virt_get_its, 3333 virt_set_its); 3334 object_class_property_set_description(oc, "its", 3335 "Set on/off to enable/disable " 3336 "ITS instantiation"); 3337 3338 object_class_property_add_bool(oc, "dtb-randomness", 3339 virt_get_dtb_randomness, 3340 virt_set_dtb_randomness); 3341 object_class_property_set_description(oc, "dtb-randomness", 3342 "Set off to disable passing random or " 3343 "non-deterministic dtb nodes to guest"); 3344 3345 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3346 virt_get_dtb_randomness, 3347 virt_set_dtb_randomness); 3348 object_class_property_set_description(oc, "dtb-kaslr-seed", 3349 "Deprecated synonym of dtb-randomness"); 3350 3351 object_class_property_add_str(oc, "x-oem-id", 3352 virt_get_oem_id, 3353 virt_set_oem_id); 3354 object_class_property_set_description(oc, "x-oem-id", 3355 "Override the default value of field OEMID " 3356 "in ACPI table header." 3357 "The string may be up to 6 bytes in size"); 3358 3359 3360 object_class_property_add_str(oc, "x-oem-table-id", 3361 virt_get_oem_table_id, 3362 virt_set_oem_table_id); 3363 object_class_property_set_description(oc, "x-oem-table-id", 3364 "Override the default value of field OEM Table ID " 3365 "in ACPI table header." 3366 "The string may be up to 8 bytes in size"); 3367 3368 } 3369 3370 static void virt_instance_init(Object *obj) 3371 { 3372 VirtMachineState *vms = VIRT_MACHINE(obj); 3373 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3374 3375 /* EL3 is disabled by default on virt: this makes us consistent 3376 * between KVM and TCG for this board, and it also allows us to 3377 * boot UEFI blobs which assume no TrustZone support. 3378 */ 3379 vms->secure = false; 3380 3381 /* EL2 is also disabled by default, for similar reasons */ 3382 vms->virt = false; 3383 3384 /* High memory is enabled by default */ 3385 vms->highmem = true; 3386 vms->highmem_compact = !vmc->no_highmem_compact; 3387 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3388 3389 vms->highmem_ecam = true; 3390 vms->highmem_mmio = true; 3391 vms->highmem_redists = true; 3392 3393 /* Default allows ITS instantiation */ 3394 vms->its = true; 3395 /* Allow ITS emulation if the machine version supports it */ 3396 vms->tcg_its = !vmc->no_tcg_its; 3397 3398 /* Default disallows iommu instantiation */ 3399 vms->iommu = VIRT_IOMMU_NONE; 3400 3401 /* The default root bus is attached to iommu by default */ 3402 vms->default_bus_bypass_iommu = false; 3403 3404 /* Default disallows RAS instantiation */ 3405 vms->ras = false; 3406 3407 /* MTE is disabled by default. */ 3408 vms->mte = false; 3409 3410 /* Supply kaslr-seed and rng-seed by default */ 3411 vms->dtb_randomness = true; 3412 3413 vms->irqmap = a15irqmap; 3414 3415 virt_flash_create(vms); 3416 3417 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3418 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3419 cxl_machine_init(obj, &vms->cxl_devices_state); 3420 } 3421 3422 static const TypeInfo virt_machine_info = { 3423 .name = TYPE_VIRT_MACHINE, 3424 .parent = TYPE_MACHINE, 3425 .abstract = true, 3426 .instance_size = sizeof(VirtMachineState), 3427 .class_size = sizeof(VirtMachineClass), 3428 .class_init = virt_machine_class_init, 3429 .instance_init = virt_instance_init, 3430 .interfaces = (const InterfaceInfo[]) { 3431 { TYPE_HOTPLUG_HANDLER }, 3432 { } 3433 }, 3434 }; 3435 3436 static void machvirt_machine_init(void) 3437 { 3438 type_register_static(&virt_machine_info); 3439 } 3440 type_init(machvirt_machine_init); 3441 3442 static void virt_machine_10_1_options(MachineClass *mc) 3443 { 3444 } 3445 DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) 3446 3447 static void virt_machine_10_0_options(MachineClass *mc) 3448 { 3449 virt_machine_10_1_options(mc); 3450 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); 3451 } 3452 DEFINE_VIRT_MACHINE(10, 0) 3453 3454 static void virt_machine_9_2_options(MachineClass *mc) 3455 { 3456 virt_machine_10_0_options(mc); 3457 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); 3458 } 3459 DEFINE_VIRT_MACHINE(9, 2) 3460 3461 static void virt_machine_9_1_options(MachineClass *mc) 3462 { 3463 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3464 3465 virt_machine_9_2_options(mc); 3466 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 3467 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */ 3468 vmc->no_nested_smmu = true; 3469 } 3470 DEFINE_VIRT_MACHINE(9, 1) 3471 3472 static void virt_machine_9_0_options(MachineClass *mc) 3473 { 3474 virt_machine_9_1_options(mc); 3475 mc->smbios_memory_device_size = 16 * GiB; 3476 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 3477 } 3478 DEFINE_VIRT_MACHINE(9, 0) 3479 3480 static void virt_machine_8_2_options(MachineClass *mc) 3481 { 3482 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3483 3484 virt_machine_9_0_options(mc); 3485 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3486 /* 3487 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and 3488 * earlier machines. (Exposing it tickles a bug in older EDK2 3489 * guest BIOS binaries.) 3490 */ 3491 vmc->no_ns_el2_virt_timer_irq = true; 3492 } 3493 DEFINE_VIRT_MACHINE(8, 2) 3494 3495 static void virt_machine_8_1_options(MachineClass *mc) 3496 { 3497 virt_machine_8_2_options(mc); 3498 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3499 } 3500 DEFINE_VIRT_MACHINE(8, 1) 3501 3502 static void virt_machine_8_0_options(MachineClass *mc) 3503 { 3504 virt_machine_8_1_options(mc); 3505 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3506 } 3507 DEFINE_VIRT_MACHINE(8, 0) 3508 3509 static void virt_machine_7_2_options(MachineClass *mc) 3510 { 3511 virt_machine_8_0_options(mc); 3512 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3513 } 3514 DEFINE_VIRT_MACHINE(7, 2) 3515 3516 static void virt_machine_7_1_options(MachineClass *mc) 3517 { 3518 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3519 3520 virt_machine_7_2_options(mc); 3521 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3522 /* Compact layout for high memory regions was introduced with 7.2 */ 3523 vmc->no_highmem_compact = true; 3524 } 3525 DEFINE_VIRT_MACHINE(7, 1) 3526 3527 static void virt_machine_7_0_options(MachineClass *mc) 3528 { 3529 virt_machine_7_1_options(mc); 3530 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3531 } 3532 DEFINE_VIRT_MACHINE(7, 0) 3533 3534 static void virt_machine_6_2_options(MachineClass *mc) 3535 { 3536 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3537 3538 virt_machine_7_0_options(mc); 3539 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3540 vmc->no_tcg_lpa2 = true; 3541 } 3542 DEFINE_VIRT_MACHINE(6, 2) 3543 3544 static void virt_machine_6_1_options(MachineClass *mc) 3545 { 3546 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3547 3548 virt_machine_6_2_options(mc); 3549 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3550 mc->smp_props.prefer_sockets = true; 3551 vmc->no_cpu_topology = true; 3552 3553 /* qemu ITS was introduced with 6.2 */ 3554 vmc->no_tcg_its = true; 3555 } 3556 DEFINE_VIRT_MACHINE(6, 1) 3557 3558 static void virt_machine_6_0_options(MachineClass *mc) 3559 { 3560 virt_machine_6_1_options(mc); 3561 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3562 } 3563 DEFINE_VIRT_MACHINE(6, 0) 3564 3565 static void virt_machine_5_2_options(MachineClass *mc) 3566 { 3567 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3568 3569 virt_machine_6_0_options(mc); 3570 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3571 vmc->no_secure_gpio = true; 3572 } 3573 DEFINE_VIRT_MACHINE(5, 2) 3574 3575 static void virt_machine_5_1_options(MachineClass *mc) 3576 { 3577 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3578 3579 virt_machine_5_2_options(mc); 3580 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3581 vmc->no_kvm_steal_time = true; 3582 } 3583 DEFINE_VIRT_MACHINE(5, 1) 3584 3585 static void virt_machine_5_0_options(MachineClass *mc) 3586 { 3587 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3588 3589 virt_machine_5_1_options(mc); 3590 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3591 mc->numa_mem_supported = true; 3592 vmc->acpi_expose_flash = true; 3593 mc->auto_enable_numa_with_memdev = false; 3594 } 3595 DEFINE_VIRT_MACHINE(5, 0) 3596 3597 static void virt_machine_4_2_options(MachineClass *mc) 3598 { 3599 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3600 3601 virt_machine_5_0_options(mc); 3602 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3603 vmc->kvm_no_adjvtime = true; 3604 } 3605 DEFINE_VIRT_MACHINE(4, 2) 3606 3607 static void virt_machine_4_1_options(MachineClass *mc) 3608 { 3609 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3610 3611 virt_machine_4_2_options(mc); 3612 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3613 vmc->no_ged = true; 3614 mc->auto_enable_numa_with_memhp = false; 3615 } 3616 DEFINE_VIRT_MACHINE(4, 1) 3617