1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/primecell.h" 40 #include "hw/arm/virt.h" 41 #include "hw/block/flash.h" 42 #include "hw/vfio/vfio-calxeda-xgmac.h" 43 #include "hw/vfio/vfio-amd-xgbe.h" 44 #include "hw/display/ramfb.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/tpm.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "hw/loader.h" 53 #include "qapi/error.h" 54 #include "qemu/bitops.h" 55 #include "qemu/error-report.h" 56 #include "qemu/module.h" 57 #include "hw/pci-host/gpex.h" 58 #include "hw/virtio/virtio-pci.h" 59 #include "hw/arm/sysbus-fdt.h" 60 #include "hw/platform-bus.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/arm/fdt.h" 63 #include "hw/intc/arm_gic.h" 64 #include "hw/intc/arm_gicv3_common.h" 65 #include "hw/irq.h" 66 #include "kvm_arm.h" 67 #include "hw/firmware/smbios.h" 68 #include "qapi/visitor.h" 69 #include "qapi/qapi-visit-common.h" 70 #include "standard-headers/linux/input.h" 71 #include "hw/arm/smmuv3.h" 72 #include "hw/acpi/acpi.h" 73 #include "target/arm/internals.h" 74 #include "hw/mem/memory-device.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-mem-pci.h" 79 #include "hw/virtio/virtio-iommu.h" 80 #include "hw/char/pl011.h" 81 #include "qemu/guest-random.h" 82 83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 85 void *data) \ 86 { \ 87 MachineClass *mc = MACHINE_CLASS(oc); \ 88 virt_machine_##major##_##minor##_options(mc); \ 89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 90 if (latest) { \ 91 mc->alias = "virt"; \ 92 } \ 93 } \ 94 static const TypeInfo machvirt_##major##_##minor##_info = { \ 95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 96 .parent = TYPE_VIRT_MACHINE, \ 97 .class_init = virt_##major##_##minor##_class_init, \ 98 }; \ 99 static void machvirt_machine_##major##_##minor##_init(void) \ 100 { \ 101 type_register_static(&machvirt_##major##_##minor##_info); \ 102 } \ 103 type_init(machvirt_machine_##major##_##minor##_init); 104 105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 107 #define DEFINE_VIRT_MACHINE(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 109 110 111 /* Number of external interrupt lines to configure the GIC with */ 112 #define NUM_IRQS 256 113 114 #define PLATFORM_BUS_NUM_IRQS 64 115 116 /* Legacy RAM limit in GB (< version 4.0) */ 117 #define LEGACY_RAMLIMIT_GB 255 118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 119 120 /* Addresses and sizes of our components. 121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 122 * 128MB..256MB is used for miscellaneous device I/O. 123 * 256MB..1GB is reserved for possible future PCI support (ie where the 124 * PCI memory window will go if we add a PCI host controller). 125 * 1GB and up is RAM (which may happily spill over into the 126 * high memory region beyond 4GB). 127 * This represents a compromise between how much RAM can be given to 128 * a 32 bit VM and leaving space for expansion and in particular for PCI. 129 * Note that devices should generally be placed at multiples of 0x10000, 130 * to accommodate guests using 64K pages. 131 */ 132 static const MemMapEntry base_memmap[] = { 133 /* Space up to 0x8000000 is reserved for a boot ROM */ 134 [VIRT_FLASH] = { 0, 0x08000000 }, 135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 144 /* This redistributor space allows up to 2*64kB*123 CPUs */ 145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 146 [VIRT_UART] = { 0x09000000, 0x00001000 }, 147 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 149 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 151 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 164 /* Actual RAM size depends on initial RAM and device memory settings */ 165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 166 }; 167 168 /* 169 * Highmem IO Regions: This memory map is floating, located after the RAM. 170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 171 * top of the RAM, so that its base get the same alignment as the size, 172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 174 * Note the extended_memmap is sized so that it eventually also includes the 175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 176 * index of base_memmap). 177 */ 178 static MemMapEntry extended_memmap[] = { 179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 180 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 181 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 182 /* Second PCIe window */ 183 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 184 }; 185 186 static const int a15irqmap[] = { 187 [VIRT_UART] = 1, 188 [VIRT_RTC] = 2, 189 [VIRT_PCIE] = 3, /* ... to 6 */ 190 [VIRT_GPIO] = 7, 191 [VIRT_SECURE_UART] = 8, 192 [VIRT_ACPI_GED] = 9, 193 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 194 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 195 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 196 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 197 }; 198 199 static const char *valid_cpus[] = { 200 ARM_CPU_TYPE_NAME("cortex-a7"), 201 ARM_CPU_TYPE_NAME("cortex-a15"), 202 ARM_CPU_TYPE_NAME("cortex-a53"), 203 ARM_CPU_TYPE_NAME("cortex-a57"), 204 ARM_CPU_TYPE_NAME("cortex-a72"), 205 ARM_CPU_TYPE_NAME("a64fx"), 206 ARM_CPU_TYPE_NAME("host"), 207 ARM_CPU_TYPE_NAME("max"), 208 }; 209 210 static bool cpu_type_valid(const char *cpu) 211 { 212 int i; 213 214 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 215 if (strcmp(cpu, valid_cpus[i]) == 0) { 216 return true; 217 } 218 } 219 return false; 220 } 221 222 static void create_kaslr_seed(MachineState *ms, const char *node) 223 { 224 uint64_t seed; 225 226 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 227 return; 228 } 229 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed); 230 } 231 232 static void create_fdt(VirtMachineState *vms) 233 { 234 MachineState *ms = MACHINE(vms); 235 int nb_numa_nodes = ms->numa_state->num_nodes; 236 void *fdt = create_device_tree(&vms->fdt_size); 237 238 if (!fdt) { 239 error_report("create_device_tree() failed"); 240 exit(1); 241 } 242 243 ms->fdt = fdt; 244 245 /* Header */ 246 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 247 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 248 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 249 250 /* /chosen must exist for load_dtb to fill in necessary properties later */ 251 qemu_fdt_add_subnode(fdt, "/chosen"); 252 if (vms->dtb_kaslr_seed) { 253 create_kaslr_seed(ms, "/chosen"); 254 } 255 256 if (vms->secure) { 257 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 258 if (vms->dtb_kaslr_seed) { 259 create_kaslr_seed(ms, "/secure-chosen"); 260 } 261 } 262 263 /* Clock node, for the benefit of the UART. The kernel device tree 264 * binding documentation claims the PL011 node clock properties are 265 * optional but in practice if you omit them the kernel refuses to 266 * probe for the device. 267 */ 268 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 269 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 270 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 271 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 272 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 273 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 274 "clk24mhz"); 275 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 276 277 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 278 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 279 uint32_t *matrix = g_malloc0(size); 280 int idx, i, j; 281 282 for (i = 0; i < nb_numa_nodes; i++) { 283 for (j = 0; j < nb_numa_nodes; j++) { 284 idx = (i * nb_numa_nodes + j) * 3; 285 matrix[idx + 0] = cpu_to_be32(i); 286 matrix[idx + 1] = cpu_to_be32(j); 287 matrix[idx + 2] = 288 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 289 } 290 } 291 292 qemu_fdt_add_subnode(fdt, "/distance-map"); 293 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 294 "numa-distance-map-v1"); 295 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 296 matrix, size); 297 g_free(matrix); 298 } 299 } 300 301 static void fdt_add_timer_nodes(const VirtMachineState *vms) 302 { 303 /* On real hardware these interrupts are level-triggered. 304 * On KVM they were edge-triggered before host kernel version 4.4, 305 * and level-triggered afterwards. 306 * On emulated QEMU they are level-triggered. 307 * 308 * Getting the DTB info about them wrong is awkward for some 309 * guest kernels: 310 * pre-4.8 ignore the DT and leave the interrupt configured 311 * with whatever the GIC reset value (or the bootloader) left it at 312 * 4.8 before rc6 honour the incorrect data by programming it back 313 * into the GIC, causing problems 314 * 4.8rc6 and later ignore the DT and always write "level triggered" 315 * into the GIC 316 * 317 * For backwards-compatibility, virt-2.8 and earlier will continue 318 * to say these are edge-triggered, but later machines will report 319 * the correct information. 320 */ 321 ARMCPU *armcpu; 322 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 323 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 324 MachineState *ms = MACHINE(vms); 325 326 if (vmc->claim_edge_triggered_timers) { 327 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 328 } 329 330 if (vms->gic_version == VIRT_GIC_VERSION_2) { 331 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 332 GIC_FDT_IRQ_PPI_CPU_WIDTH, 333 (1 << MACHINE(vms)->smp.cpus) - 1); 334 } 335 336 qemu_fdt_add_subnode(ms->fdt, "/timer"); 337 338 armcpu = ARM_CPU(qemu_get_cpu(0)); 339 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 340 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 341 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 342 compat, sizeof(compat)); 343 } else { 344 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 345 "arm,armv7-timer"); 346 } 347 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 348 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 349 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 350 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 351 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 352 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 353 } 354 355 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 356 { 357 int cpu; 358 int addr_cells = 1; 359 const MachineState *ms = MACHINE(vms); 360 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 361 int smp_cpus = ms->smp.cpus; 362 363 /* 364 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 365 * On ARM v8 64-bit systems value should be set to 2, 366 * that corresponds to the MPIDR_EL1 register size. 367 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 368 * in the system, #address-cells can be set to 1, since 369 * MPIDR_EL1[63:32] bits are not used for CPUs 370 * identification. 371 * 372 * Here we actually don't know whether our system is 32- or 64-bit one. 373 * The simplest way to go is to examine affinity IDs of all our CPUs. If 374 * at least one of them has Aff3 populated, we set #address-cells to 2. 375 */ 376 for (cpu = 0; cpu < smp_cpus; cpu++) { 377 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 378 379 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 380 addr_cells = 2; 381 break; 382 } 383 } 384 385 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 386 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 387 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 388 389 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 390 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 391 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 392 CPUState *cs = CPU(armcpu); 393 394 qemu_fdt_add_subnode(ms->fdt, nodename); 395 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 396 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 397 armcpu->dtb_compatible); 398 399 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 400 qemu_fdt_setprop_string(ms->fdt, nodename, 401 "enable-method", "psci"); 402 } 403 404 if (addr_cells == 2) { 405 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 406 armcpu->mp_affinity); 407 } else { 408 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 409 armcpu->mp_affinity); 410 } 411 412 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 413 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 414 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 415 } 416 417 if (!vmc->no_cpu_topology) { 418 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 419 qemu_fdt_alloc_phandle(ms->fdt)); 420 } 421 422 g_free(nodename); 423 } 424 425 if (!vmc->no_cpu_topology) { 426 /* 427 * Add vCPU topology description through fdt node cpu-map. 428 * 429 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 430 * In a SMP system, the hierarchy of CPUs can be defined through 431 * four entities that are used to describe the layout of CPUs in 432 * the system: socket/cluster/core/thread. 433 * 434 * A socket node represents the boundary of system physical package 435 * and its child nodes must be one or more cluster nodes. A system 436 * can contain several layers of clustering within a single physical 437 * package and cluster nodes can be contained in parent cluster nodes. 438 * 439 * Note: currently we only support one layer of clustering within 440 * each physical package. 441 */ 442 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 443 444 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 445 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 446 char *map_path; 447 448 if (ms->smp.threads > 1) { 449 map_path = g_strdup_printf( 450 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 451 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 452 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 453 (cpu / ms->smp.threads) % ms->smp.cores, 454 cpu % ms->smp.threads); 455 } else { 456 map_path = g_strdup_printf( 457 "/cpus/cpu-map/socket%d/cluster%d/core%d", 458 cpu / (ms->smp.clusters * ms->smp.cores), 459 (cpu / ms->smp.cores) % ms->smp.clusters, 460 cpu % ms->smp.cores); 461 } 462 qemu_fdt_add_path(ms->fdt, map_path); 463 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 464 465 g_free(map_path); 466 g_free(cpu_path); 467 } 468 } 469 } 470 471 static void fdt_add_its_gic_node(VirtMachineState *vms) 472 { 473 char *nodename; 474 MachineState *ms = MACHINE(vms); 475 476 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 477 nodename = g_strdup_printf("/intc/its@%" PRIx64, 478 vms->memmap[VIRT_GIC_ITS].base); 479 qemu_fdt_add_subnode(ms->fdt, nodename); 480 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 481 "arm,gic-v3-its"); 482 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 483 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 484 2, vms->memmap[VIRT_GIC_ITS].base, 485 2, vms->memmap[VIRT_GIC_ITS].size); 486 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 487 g_free(nodename); 488 } 489 490 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 491 { 492 MachineState *ms = MACHINE(vms); 493 char *nodename; 494 495 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 496 vms->memmap[VIRT_GIC_V2M].base); 497 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 498 qemu_fdt_add_subnode(ms->fdt, nodename); 499 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 500 "arm,gic-v2m-frame"); 501 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 502 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 503 2, vms->memmap[VIRT_GIC_V2M].base, 504 2, vms->memmap[VIRT_GIC_V2M].size); 505 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 506 g_free(nodename); 507 } 508 509 static void fdt_add_gic_node(VirtMachineState *vms) 510 { 511 MachineState *ms = MACHINE(vms); 512 char *nodename; 513 514 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 515 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 516 517 nodename = g_strdup_printf("/intc@%" PRIx64, 518 vms->memmap[VIRT_GIC_DIST].base); 519 qemu_fdt_add_subnode(ms->fdt, nodename); 520 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 521 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 522 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 523 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 524 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 525 if (vms->gic_version != VIRT_GIC_VERSION_2) { 526 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 527 528 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 529 "arm,gic-v3"); 530 531 qemu_fdt_setprop_cell(ms->fdt, nodename, 532 "#redistributor-regions", nb_redist_regions); 533 534 if (nb_redist_regions == 1) { 535 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 536 2, vms->memmap[VIRT_GIC_DIST].base, 537 2, vms->memmap[VIRT_GIC_DIST].size, 538 2, vms->memmap[VIRT_GIC_REDIST].base, 539 2, vms->memmap[VIRT_GIC_REDIST].size); 540 } else { 541 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 542 2, vms->memmap[VIRT_GIC_DIST].base, 543 2, vms->memmap[VIRT_GIC_DIST].size, 544 2, vms->memmap[VIRT_GIC_REDIST].base, 545 2, vms->memmap[VIRT_GIC_REDIST].size, 546 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 547 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 548 } 549 550 if (vms->virt) { 551 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 552 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 553 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 554 } 555 } else { 556 /* 'cortex-a15-gic' means 'GIC v2' */ 557 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 558 "arm,cortex-a15-gic"); 559 if (!vms->virt) { 560 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 561 2, vms->memmap[VIRT_GIC_DIST].base, 562 2, vms->memmap[VIRT_GIC_DIST].size, 563 2, vms->memmap[VIRT_GIC_CPU].base, 564 2, vms->memmap[VIRT_GIC_CPU].size); 565 } else { 566 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 567 2, vms->memmap[VIRT_GIC_DIST].base, 568 2, vms->memmap[VIRT_GIC_DIST].size, 569 2, vms->memmap[VIRT_GIC_CPU].base, 570 2, vms->memmap[VIRT_GIC_CPU].size, 571 2, vms->memmap[VIRT_GIC_HYP].base, 572 2, vms->memmap[VIRT_GIC_HYP].size, 573 2, vms->memmap[VIRT_GIC_VCPU].base, 574 2, vms->memmap[VIRT_GIC_VCPU].size); 575 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 576 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 577 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 578 } 579 } 580 581 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 582 g_free(nodename); 583 } 584 585 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 586 { 587 ARMCPU *armcpu = ARM_CPU(first_cpu); 588 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 589 MachineState *ms = MACHINE(vms); 590 591 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 592 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 593 return; 594 } 595 596 if (vms->gic_version == VIRT_GIC_VERSION_2) { 597 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 598 GIC_FDT_IRQ_PPI_CPU_WIDTH, 599 (1 << MACHINE(vms)->smp.cpus) - 1); 600 } 601 602 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 603 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 604 const char compat[] = "arm,armv8-pmuv3"; 605 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 606 compat, sizeof(compat)); 607 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 608 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 609 } 610 } 611 612 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 613 { 614 DeviceState *dev; 615 MachineState *ms = MACHINE(vms); 616 int irq = vms->irqmap[VIRT_ACPI_GED]; 617 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 618 619 if (ms->ram_slots) { 620 event |= ACPI_GED_MEM_HOTPLUG_EVT; 621 } 622 623 if (ms->nvdimms_state->is_enabled) { 624 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 625 } 626 627 dev = qdev_new(TYPE_ACPI_GED); 628 qdev_prop_set_uint32(dev, "ged-event", event); 629 630 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 631 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 632 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 633 634 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 635 636 return dev; 637 } 638 639 static void create_its(VirtMachineState *vms) 640 { 641 const char *itsclass = its_class_name(); 642 DeviceState *dev; 643 644 if (!strcmp(itsclass, "arm-gicv3-its")) { 645 if (!vms->tcg_its) { 646 itsclass = NULL; 647 } 648 } 649 650 if (!itsclass) { 651 /* Do nothing if not supported */ 652 return; 653 } 654 655 dev = qdev_new(itsclass); 656 657 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 658 &error_abort); 659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 660 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 661 662 fdt_add_its_gic_node(vms); 663 vms->msi_controller = VIRT_MSI_CTRL_ITS; 664 } 665 666 static void create_v2m(VirtMachineState *vms) 667 { 668 int i; 669 int irq = vms->irqmap[VIRT_GIC_V2M]; 670 DeviceState *dev; 671 672 dev = qdev_new("arm-gicv2m"); 673 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 674 qdev_prop_set_uint32(dev, "base-spi", irq); 675 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 676 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 677 678 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 679 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 680 qdev_get_gpio_in(vms->gic, irq + i)); 681 } 682 683 fdt_add_v2m_gic_node(vms); 684 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 685 } 686 687 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 688 { 689 MachineState *ms = MACHINE(vms); 690 /* We create a standalone GIC */ 691 SysBusDevice *gicbusdev; 692 const char *gictype; 693 int i; 694 unsigned int smp_cpus = ms->smp.cpus; 695 uint32_t nb_redist_regions = 0; 696 int revision; 697 698 if (vms->gic_version == VIRT_GIC_VERSION_2) { 699 gictype = gic_class_name(); 700 } else { 701 gictype = gicv3_class_name(); 702 } 703 704 switch (vms->gic_version) { 705 case VIRT_GIC_VERSION_2: 706 revision = 2; 707 break; 708 case VIRT_GIC_VERSION_3: 709 revision = 3; 710 break; 711 case VIRT_GIC_VERSION_4: 712 revision = 4; 713 break; 714 default: 715 g_assert_not_reached(); 716 } 717 vms->gic = qdev_new(gictype); 718 qdev_prop_set_uint32(vms->gic, "revision", revision); 719 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 720 /* Note that the num-irq property counts both internal and external 721 * interrupts; there are always 32 of the former (mandated by GIC spec). 722 */ 723 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 724 if (!kvm_irqchip_in_kernel()) { 725 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 726 } 727 728 if (vms->gic_version != VIRT_GIC_VERSION_2) { 729 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 730 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 731 732 nb_redist_regions = virt_gicv3_redist_region_count(vms); 733 734 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 735 nb_redist_regions); 736 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 737 738 if (!kvm_irqchip_in_kernel()) { 739 if (vms->tcg_its) { 740 object_property_set_link(OBJECT(vms->gic), "sysmem", 741 OBJECT(mem), &error_fatal); 742 qdev_prop_set_bit(vms->gic, "has-lpi", true); 743 } 744 } 745 746 if (nb_redist_regions == 2) { 747 uint32_t redist1_capacity = 748 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 749 750 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 751 MIN(smp_cpus - redist0_count, redist1_capacity)); 752 } 753 } else { 754 if (!kvm_irqchip_in_kernel()) { 755 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 756 vms->virt); 757 } 758 } 759 gicbusdev = SYS_BUS_DEVICE(vms->gic); 760 sysbus_realize_and_unref(gicbusdev, &error_fatal); 761 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 762 if (vms->gic_version != VIRT_GIC_VERSION_2) { 763 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 764 if (nb_redist_regions == 2) { 765 sysbus_mmio_map(gicbusdev, 2, 766 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 767 } 768 } else { 769 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 770 if (vms->virt) { 771 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 772 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 773 } 774 } 775 776 /* Wire the outputs from each CPU's generic timer and the GICv3 777 * maintenance interrupt signal to the appropriate GIC PPI inputs, 778 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 779 */ 780 for (i = 0; i < smp_cpus; i++) { 781 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 782 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 783 int irq; 784 /* Mapping from the output timer irq lines from the CPU to the 785 * GIC PPI inputs we use for the virt board. 786 */ 787 const int timer_irq[] = { 788 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 789 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 790 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 791 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 792 }; 793 794 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 795 qdev_connect_gpio_out(cpudev, irq, 796 qdev_get_gpio_in(vms->gic, 797 ppibase + timer_irq[irq])); 798 } 799 800 if (vms->gic_version != VIRT_GIC_VERSION_2) { 801 qemu_irq irq = qdev_get_gpio_in(vms->gic, 802 ppibase + ARCH_GIC_MAINT_IRQ); 803 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 804 0, irq); 805 } else if (vms->virt) { 806 qemu_irq irq = qdev_get_gpio_in(vms->gic, 807 ppibase + ARCH_GIC_MAINT_IRQ); 808 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 809 } 810 811 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 812 qdev_get_gpio_in(vms->gic, ppibase 813 + VIRTUAL_PMU_IRQ)); 814 815 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 816 sysbus_connect_irq(gicbusdev, i + smp_cpus, 817 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 818 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 819 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 820 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 821 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 822 } 823 824 fdt_add_gic_node(vms); 825 826 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 827 create_its(vms); 828 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 829 create_v2m(vms); 830 } 831 } 832 833 static void create_uart(const VirtMachineState *vms, int uart, 834 MemoryRegion *mem, Chardev *chr) 835 { 836 char *nodename; 837 hwaddr base = vms->memmap[uart].base; 838 hwaddr size = vms->memmap[uart].size; 839 int irq = vms->irqmap[uart]; 840 const char compat[] = "arm,pl011\0arm,primecell"; 841 const char clocknames[] = "uartclk\0apb_pclk"; 842 DeviceState *dev = qdev_new(TYPE_PL011); 843 SysBusDevice *s = SYS_BUS_DEVICE(dev); 844 MachineState *ms = MACHINE(vms); 845 846 qdev_prop_set_chr(dev, "chardev", chr); 847 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 848 memory_region_add_subregion(mem, base, 849 sysbus_mmio_get_region(s, 0)); 850 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 851 852 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 853 qemu_fdt_add_subnode(ms->fdt, nodename); 854 /* Note that we can't use setprop_string because of the embedded NUL */ 855 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 856 compat, sizeof(compat)); 857 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 858 2, base, 2, size); 859 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 860 GIC_FDT_IRQ_TYPE_SPI, irq, 861 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 862 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 863 vms->clock_phandle, vms->clock_phandle); 864 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 865 clocknames, sizeof(clocknames)); 866 867 if (uart == VIRT_UART) { 868 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 869 } else { 870 /* Mark as not usable by the normal world */ 871 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 872 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 873 874 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 875 nodename); 876 } 877 878 g_free(nodename); 879 } 880 881 static void create_rtc(const VirtMachineState *vms) 882 { 883 char *nodename; 884 hwaddr base = vms->memmap[VIRT_RTC].base; 885 hwaddr size = vms->memmap[VIRT_RTC].size; 886 int irq = vms->irqmap[VIRT_RTC]; 887 const char compat[] = "arm,pl031\0arm,primecell"; 888 MachineState *ms = MACHINE(vms); 889 890 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 891 892 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 893 qemu_fdt_add_subnode(ms->fdt, nodename); 894 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 895 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 896 2, base, 2, size); 897 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 898 GIC_FDT_IRQ_TYPE_SPI, irq, 899 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 900 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 901 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 902 g_free(nodename); 903 } 904 905 static DeviceState *gpio_key_dev; 906 static void virt_powerdown_req(Notifier *n, void *opaque) 907 { 908 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 909 910 if (s->acpi_dev) { 911 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 912 } else { 913 /* use gpio Pin 3 for power button event */ 914 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 915 } 916 } 917 918 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 919 uint32_t phandle) 920 { 921 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 922 qdev_get_gpio_in(pl061_dev, 3)); 923 924 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 925 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 926 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0); 927 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1); 928 929 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 930 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 931 "label", "GPIO Key Poweroff"); 932 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 933 KEY_POWER); 934 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 935 "gpios", phandle, 3, 0); 936 } 937 938 #define SECURE_GPIO_POWEROFF 0 939 #define SECURE_GPIO_RESET 1 940 941 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 942 uint32_t phandle) 943 { 944 DeviceState *gpio_pwr_dev; 945 946 /* gpio-pwr */ 947 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 948 949 /* connect secure pl061 to gpio-pwr */ 950 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 951 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 952 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 953 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 954 955 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 956 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 957 "gpio-poweroff"); 958 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 959 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 960 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 961 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 962 "okay"); 963 964 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 965 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 966 "gpio-restart"); 967 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 968 "gpios", phandle, SECURE_GPIO_RESET, 0); 969 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 970 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 971 "okay"); 972 } 973 974 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 975 MemoryRegion *mem) 976 { 977 char *nodename; 978 DeviceState *pl061_dev; 979 hwaddr base = vms->memmap[gpio].base; 980 hwaddr size = vms->memmap[gpio].size; 981 int irq = vms->irqmap[gpio]; 982 const char compat[] = "arm,pl061\0arm,primecell"; 983 SysBusDevice *s; 984 MachineState *ms = MACHINE(vms); 985 986 pl061_dev = qdev_new("pl061"); 987 /* Pull lines down to 0 if not driven by the PL061 */ 988 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 989 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 990 s = SYS_BUS_DEVICE(pl061_dev); 991 sysbus_realize_and_unref(s, &error_fatal); 992 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 993 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 994 995 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 996 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 997 qemu_fdt_add_subnode(ms->fdt, nodename); 998 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 999 2, base, 2, size); 1000 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1001 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1002 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1003 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1004 GIC_FDT_IRQ_TYPE_SPI, irq, 1005 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1007 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1008 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1009 1010 if (gpio != VIRT_GPIO) { 1011 /* Mark as not usable by the normal world */ 1012 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1013 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1014 } 1015 g_free(nodename); 1016 1017 /* Child gpio devices */ 1018 if (gpio == VIRT_GPIO) { 1019 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1020 } else { 1021 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1022 } 1023 } 1024 1025 static void create_virtio_devices(const VirtMachineState *vms) 1026 { 1027 int i; 1028 hwaddr size = vms->memmap[VIRT_MMIO].size; 1029 MachineState *ms = MACHINE(vms); 1030 1031 /* We create the transports in forwards order. Since qbus_realize() 1032 * prepends (not appends) new child buses, the incrementing loop below will 1033 * create a list of virtio-mmio buses with decreasing base addresses. 1034 * 1035 * When a -device option is processed from the command line, 1036 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1037 * order. The upshot is that -device options in increasing command line 1038 * order are mapped to virtio-mmio buses with decreasing base addresses. 1039 * 1040 * When this code was originally written, that arrangement ensured that the 1041 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1042 * the first -device on the command line. (The end-to-end order is a 1043 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1044 * guest kernel's name-to-address assignment strategy.) 1045 * 1046 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1047 * the message, if not necessarily the code, of commit 70161ff336. 1048 * Therefore the loop now establishes the inverse of the original intent. 1049 * 1050 * Unfortunately, we can't counteract the kernel change by reversing the 1051 * loop; it would break existing command lines. 1052 * 1053 * In any case, the kernel makes no guarantee about the stability of 1054 * enumeration order of virtio devices (as demonstrated by it changing 1055 * between kernel versions). For reliable and stable identification 1056 * of disks users must use UUIDs or similar mechanisms. 1057 */ 1058 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1059 int irq = vms->irqmap[VIRT_MMIO] + i; 1060 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1061 1062 sysbus_create_simple("virtio-mmio", base, 1063 qdev_get_gpio_in(vms->gic, irq)); 1064 } 1065 1066 /* We add dtb nodes in reverse order so that they appear in the finished 1067 * device tree lowest address first. 1068 * 1069 * Note that this mapping is independent of the loop above. The previous 1070 * loop influences virtio device to virtio transport assignment, whereas 1071 * this loop controls how virtio transports are laid out in the dtb. 1072 */ 1073 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1074 char *nodename; 1075 int irq = vms->irqmap[VIRT_MMIO] + i; 1076 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1077 1078 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1079 qemu_fdt_add_subnode(ms->fdt, nodename); 1080 qemu_fdt_setprop_string(ms->fdt, nodename, 1081 "compatible", "virtio,mmio"); 1082 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1083 2, base, 2, size); 1084 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1085 GIC_FDT_IRQ_TYPE_SPI, irq, 1086 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1087 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1088 g_free(nodename); 1089 } 1090 } 1091 1092 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1093 1094 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1095 const char *name, 1096 const char *alias_prop_name) 1097 { 1098 /* 1099 * Create a single flash device. We use the same parameters as 1100 * the flash devices on the Versatile Express board. 1101 */ 1102 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1103 1104 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1105 qdev_prop_set_uint8(dev, "width", 4); 1106 qdev_prop_set_uint8(dev, "device-width", 2); 1107 qdev_prop_set_bit(dev, "big-endian", false); 1108 qdev_prop_set_uint16(dev, "id0", 0x89); 1109 qdev_prop_set_uint16(dev, "id1", 0x18); 1110 qdev_prop_set_uint16(dev, "id2", 0x00); 1111 qdev_prop_set_uint16(dev, "id3", 0x00); 1112 qdev_prop_set_string(dev, "name", name); 1113 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1114 object_property_add_alias(OBJECT(vms), alias_prop_name, 1115 OBJECT(dev), "drive"); 1116 return PFLASH_CFI01(dev); 1117 } 1118 1119 static void virt_flash_create(VirtMachineState *vms) 1120 { 1121 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1122 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1123 } 1124 1125 static void virt_flash_map1(PFlashCFI01 *flash, 1126 hwaddr base, hwaddr size, 1127 MemoryRegion *sysmem) 1128 { 1129 DeviceState *dev = DEVICE(flash); 1130 1131 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1132 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1133 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1134 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1135 1136 memory_region_add_subregion(sysmem, base, 1137 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1138 0)); 1139 } 1140 1141 static void virt_flash_map(VirtMachineState *vms, 1142 MemoryRegion *sysmem, 1143 MemoryRegion *secure_sysmem) 1144 { 1145 /* 1146 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1147 * sysmem is the system memory space. secure_sysmem is the secure view 1148 * of the system, and the first flash device should be made visible only 1149 * there. The second flash device is visible to both secure and nonsecure. 1150 * If sysmem == secure_sysmem this means there is no separate Secure 1151 * address space and both flash devices are generally visible. 1152 */ 1153 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1154 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1155 1156 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1157 secure_sysmem); 1158 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1159 sysmem); 1160 } 1161 1162 static void virt_flash_fdt(VirtMachineState *vms, 1163 MemoryRegion *sysmem, 1164 MemoryRegion *secure_sysmem) 1165 { 1166 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1167 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1168 MachineState *ms = MACHINE(vms); 1169 char *nodename; 1170 1171 if (sysmem == secure_sysmem) { 1172 /* Report both flash devices as a single node in the DT */ 1173 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1174 qemu_fdt_add_subnode(ms->fdt, nodename); 1175 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1176 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1177 2, flashbase, 2, flashsize, 1178 2, flashbase + flashsize, 2, flashsize); 1179 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1180 g_free(nodename); 1181 } else { 1182 /* 1183 * Report the devices as separate nodes so we can mark one as 1184 * only visible to the secure world. 1185 */ 1186 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1187 qemu_fdt_add_subnode(ms->fdt, nodename); 1188 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1189 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1190 2, flashbase, 2, flashsize); 1191 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1192 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1193 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1194 g_free(nodename); 1195 1196 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1197 qemu_fdt_add_subnode(ms->fdt, nodename); 1198 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1199 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1200 2, flashbase + flashsize, 2, flashsize); 1201 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1202 g_free(nodename); 1203 } 1204 } 1205 1206 static bool virt_firmware_init(VirtMachineState *vms, 1207 MemoryRegion *sysmem, 1208 MemoryRegion *secure_sysmem) 1209 { 1210 int i; 1211 const char *bios_name; 1212 BlockBackend *pflash_blk0; 1213 1214 /* Map legacy -drive if=pflash to machine properties */ 1215 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1216 pflash_cfi01_legacy_drive(vms->flash[i], 1217 drive_get(IF_PFLASH, 0, i)); 1218 } 1219 1220 virt_flash_map(vms, sysmem, secure_sysmem); 1221 1222 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1223 1224 bios_name = MACHINE(vms)->firmware; 1225 if (bios_name) { 1226 char *fname; 1227 MemoryRegion *mr; 1228 int image_size; 1229 1230 if (pflash_blk0) { 1231 error_report("The contents of the first flash device may be " 1232 "specified with -bios or with -drive if=pflash... " 1233 "but you cannot use both options at once"); 1234 exit(1); 1235 } 1236 1237 /* Fall back to -bios */ 1238 1239 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1240 if (!fname) { 1241 error_report("Could not find ROM image '%s'", bios_name); 1242 exit(1); 1243 } 1244 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1245 image_size = load_image_mr(fname, mr); 1246 g_free(fname); 1247 if (image_size < 0) { 1248 error_report("Could not load ROM image '%s'", bios_name); 1249 exit(1); 1250 } 1251 } 1252 1253 return pflash_blk0 || bios_name; 1254 } 1255 1256 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1257 { 1258 MachineState *ms = MACHINE(vms); 1259 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1260 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1261 FWCfgState *fw_cfg; 1262 char *nodename; 1263 1264 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1265 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1266 1267 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1268 qemu_fdt_add_subnode(ms->fdt, nodename); 1269 qemu_fdt_setprop_string(ms->fdt, nodename, 1270 "compatible", "qemu,fw-cfg-mmio"); 1271 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1272 2, base, 2, size); 1273 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1274 g_free(nodename); 1275 return fw_cfg; 1276 } 1277 1278 static void create_pcie_irq_map(const MachineState *ms, 1279 uint32_t gic_phandle, 1280 int first_irq, const char *nodename) 1281 { 1282 int devfn, pin; 1283 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1284 uint32_t *irq_map = full_irq_map; 1285 1286 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1287 for (pin = 0; pin < 4; pin++) { 1288 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1289 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1290 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1291 int i; 1292 1293 uint32_t map[] = { 1294 devfn << 8, 0, 0, /* devfn */ 1295 pin + 1, /* PCI pin */ 1296 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1297 1298 /* Convert map to big endian */ 1299 for (i = 0; i < 10; i++) { 1300 irq_map[i] = cpu_to_be32(map[i]); 1301 } 1302 irq_map += 10; 1303 } 1304 } 1305 1306 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1307 full_irq_map, sizeof(full_irq_map)); 1308 1309 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1310 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1311 0, 0, 1312 0x7 /* PCI irq */); 1313 } 1314 1315 static void create_smmu(const VirtMachineState *vms, 1316 PCIBus *bus) 1317 { 1318 char *node; 1319 const char compat[] = "arm,smmu-v3"; 1320 int irq = vms->irqmap[VIRT_SMMU]; 1321 int i; 1322 hwaddr base = vms->memmap[VIRT_SMMU].base; 1323 hwaddr size = vms->memmap[VIRT_SMMU].size; 1324 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1325 DeviceState *dev; 1326 MachineState *ms = MACHINE(vms); 1327 1328 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1329 return; 1330 } 1331 1332 dev = qdev_new("arm-smmuv3"); 1333 1334 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1335 &error_abort); 1336 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1337 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1338 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1339 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1340 qdev_get_gpio_in(vms->gic, irq + i)); 1341 } 1342 1343 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1344 qemu_fdt_add_subnode(ms->fdt, node); 1345 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1346 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1347 1348 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1349 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1350 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1351 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1352 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1353 1354 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1355 sizeof(irq_names)); 1356 1357 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); 1358 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); 1359 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1360 1361 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1362 1363 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1364 g_free(node); 1365 } 1366 1367 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1368 { 1369 const char compat[] = "virtio,pci-iommu"; 1370 uint16_t bdf = vms->virtio_iommu_bdf; 1371 MachineState *ms = MACHINE(vms); 1372 char *node; 1373 1374 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1375 1376 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1377 qemu_fdt_add_subnode(ms->fdt, node); 1378 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1379 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1380 1, bdf << 8, 1, 0, 1, 0, 1381 1, 0, 1, 0); 1382 1383 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1384 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1385 g_free(node); 1386 1387 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1388 0x0, vms->iommu_phandle, 0x0, bdf, 1389 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1390 } 1391 1392 static void create_pcie(VirtMachineState *vms) 1393 { 1394 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1395 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1396 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1397 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1398 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1399 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1400 hwaddr base_ecam, size_ecam; 1401 hwaddr base = base_mmio; 1402 int nr_pcie_buses; 1403 int irq = vms->irqmap[VIRT_PCIE]; 1404 MemoryRegion *mmio_alias; 1405 MemoryRegion *mmio_reg; 1406 MemoryRegion *ecam_alias; 1407 MemoryRegion *ecam_reg; 1408 DeviceState *dev; 1409 char *nodename; 1410 int i, ecam_id; 1411 PCIHostState *pci; 1412 MachineState *ms = MACHINE(vms); 1413 1414 dev = qdev_new(TYPE_GPEX_HOST); 1415 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1416 1417 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1418 base_ecam = vms->memmap[ecam_id].base; 1419 size_ecam = vms->memmap[ecam_id].size; 1420 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1421 /* Map only the first size_ecam bytes of ECAM space */ 1422 ecam_alias = g_new0(MemoryRegion, 1); 1423 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1424 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1425 ecam_reg, 0, size_ecam); 1426 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1427 1428 /* Map the MMIO window into system address space so as to expose 1429 * the section of PCI MMIO space which starts at the same base address 1430 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1431 * the window). 1432 */ 1433 mmio_alias = g_new0(MemoryRegion, 1); 1434 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1435 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1436 mmio_reg, base_mmio, size_mmio); 1437 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1438 1439 if (vms->highmem_mmio) { 1440 /* Map high MMIO space */ 1441 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1442 1443 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1444 mmio_reg, base_mmio_high, size_mmio_high); 1445 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1446 high_mmio_alias); 1447 } 1448 1449 /* Map IO port space */ 1450 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1451 1452 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1453 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1454 qdev_get_gpio_in(vms->gic, irq + i)); 1455 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1456 } 1457 1458 pci = PCI_HOST_BRIDGE(dev); 1459 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1460 vms->bus = pci->bus; 1461 if (vms->bus) { 1462 for (i = 0; i < nb_nics; i++) { 1463 NICInfo *nd = &nd_table[i]; 1464 1465 if (!nd->model) { 1466 nd->model = g_strdup("virtio"); 1467 } 1468 1469 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1470 } 1471 } 1472 1473 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1474 qemu_fdt_add_subnode(ms->fdt, nodename); 1475 qemu_fdt_setprop_string(ms->fdt, nodename, 1476 "compatible", "pci-host-ecam-generic"); 1477 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1478 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1479 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1480 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1481 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1482 nr_pcie_buses - 1); 1483 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1484 1485 if (vms->msi_phandle) { 1486 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent", 1487 vms->msi_phandle); 1488 } 1489 1490 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1491 2, base_ecam, 2, size_ecam); 1492 1493 if (vms->highmem_mmio) { 1494 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1495 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1496 2, base_pio, 2, size_pio, 1497 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1498 2, base_mmio, 2, size_mmio, 1499 1, FDT_PCI_RANGE_MMIO_64BIT, 1500 2, base_mmio_high, 1501 2, base_mmio_high, 2, size_mmio_high); 1502 } else { 1503 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1504 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1505 2, base_pio, 2, size_pio, 1506 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1507 2, base_mmio, 2, size_mmio); 1508 } 1509 1510 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1511 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1512 1513 if (vms->iommu) { 1514 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1515 1516 switch (vms->iommu) { 1517 case VIRT_IOMMU_SMMUV3: 1518 create_smmu(vms, vms->bus); 1519 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1520 0x0, vms->iommu_phandle, 0x0, 0x10000); 1521 break; 1522 default: 1523 g_assert_not_reached(); 1524 } 1525 } 1526 } 1527 1528 static void create_platform_bus(VirtMachineState *vms) 1529 { 1530 DeviceState *dev; 1531 SysBusDevice *s; 1532 int i; 1533 MemoryRegion *sysmem = get_system_memory(); 1534 1535 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1536 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1537 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1538 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1539 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1540 vms->platform_bus_dev = dev; 1541 1542 s = SYS_BUS_DEVICE(dev); 1543 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1544 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1545 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1546 } 1547 1548 memory_region_add_subregion(sysmem, 1549 vms->memmap[VIRT_PLATFORM_BUS].base, 1550 sysbus_mmio_get_region(s, 0)); 1551 } 1552 1553 static void create_tag_ram(MemoryRegion *tag_sysmem, 1554 hwaddr base, hwaddr size, 1555 const char *name) 1556 { 1557 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1558 1559 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1560 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1561 } 1562 1563 static void create_secure_ram(VirtMachineState *vms, 1564 MemoryRegion *secure_sysmem, 1565 MemoryRegion *secure_tag_sysmem) 1566 { 1567 MemoryRegion *secram = g_new(MemoryRegion, 1); 1568 char *nodename; 1569 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1570 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1571 MachineState *ms = MACHINE(vms); 1572 1573 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1574 &error_fatal); 1575 memory_region_add_subregion(secure_sysmem, base, secram); 1576 1577 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1578 qemu_fdt_add_subnode(ms->fdt, nodename); 1579 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1580 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1581 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1582 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1583 1584 if (secure_tag_sysmem) { 1585 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1586 } 1587 1588 g_free(nodename); 1589 } 1590 1591 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1592 { 1593 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1594 bootinfo); 1595 MachineState *ms = MACHINE(board); 1596 1597 1598 *fdt_size = board->fdt_size; 1599 return ms->fdt; 1600 } 1601 1602 static void virt_build_smbios(VirtMachineState *vms) 1603 { 1604 MachineClass *mc = MACHINE_GET_CLASS(vms); 1605 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1606 uint8_t *smbios_tables, *smbios_anchor; 1607 size_t smbios_tables_len, smbios_anchor_len; 1608 const char *product = "QEMU Virtual Machine"; 1609 1610 if (kvm_enabled()) { 1611 product = "KVM Virtual Machine"; 1612 } 1613 1614 smbios_set_defaults("QEMU", product, 1615 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1616 true, SMBIOS_ENTRY_POINT_TYPE_64); 1617 1618 smbios_get_tables(MACHINE(vms), NULL, 0, 1619 &smbios_tables, &smbios_tables_len, 1620 &smbios_anchor, &smbios_anchor_len, 1621 &error_fatal); 1622 1623 if (smbios_anchor) { 1624 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1625 smbios_tables, smbios_tables_len); 1626 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1627 smbios_anchor, smbios_anchor_len); 1628 } 1629 } 1630 1631 static 1632 void virt_machine_done(Notifier *notifier, void *data) 1633 { 1634 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1635 machine_done); 1636 MachineState *ms = MACHINE(vms); 1637 ARMCPU *cpu = ARM_CPU(first_cpu); 1638 struct arm_boot_info *info = &vms->bootinfo; 1639 AddressSpace *as = arm_boot_address_space(cpu, info); 1640 1641 /* 1642 * If the user provided a dtb, we assume the dynamic sysbus nodes 1643 * already are integrated there. This corresponds to a use case where 1644 * the dynamic sysbus nodes are complex and their generation is not yet 1645 * supported. In that case the user can take charge of the guest dt 1646 * while qemu takes charge of the qom stuff. 1647 */ 1648 if (info->dtb_filename == NULL) { 1649 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1650 vms->memmap[VIRT_PLATFORM_BUS].base, 1651 vms->memmap[VIRT_PLATFORM_BUS].size, 1652 vms->irqmap[VIRT_PLATFORM_BUS]); 1653 } 1654 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1655 exit(1); 1656 } 1657 1658 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1659 1660 virt_acpi_setup(vms); 1661 virt_build_smbios(vms); 1662 } 1663 1664 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1665 { 1666 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1667 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1668 1669 if (!vmc->disallow_affinity_adjustment) { 1670 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1671 * GIC's target-list limitations. 32-bit KVM hosts currently 1672 * always create clusters of 4 CPUs, but that is expected to 1673 * change when they gain support for gicv3. When KVM is enabled 1674 * it will override the changes we make here, therefore our 1675 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1676 * and to improve SGI efficiency. 1677 */ 1678 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1679 clustersz = GIC_TARGETLIST_BITS; 1680 } else { 1681 clustersz = GICV3_TARGETLIST_BITS; 1682 } 1683 } 1684 return arm_cpu_mp_affinity(idx, clustersz); 1685 } 1686 1687 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1688 { 1689 MachineState *ms = MACHINE(vms); 1690 hwaddr base, device_memory_base, device_memory_size, memtop; 1691 int i; 1692 1693 vms->memmap = extended_memmap; 1694 1695 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1696 vms->memmap[i] = base_memmap[i]; 1697 } 1698 1699 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1700 error_report("unsupported number of memory slots: %"PRIu64, 1701 ms->ram_slots); 1702 exit(EXIT_FAILURE); 1703 } 1704 1705 /* 1706 * !highmem is exactly the same as limiting the PA space to 32bit, 1707 * irrespective of the underlying capabilities of the HW. 1708 */ 1709 if (!vms->highmem) { 1710 pa_bits = 32; 1711 } 1712 1713 /* 1714 * We compute the base of the high IO region depending on the 1715 * amount of initial and device memory. The device memory start/size 1716 * is aligned on 1GiB. We never put the high IO region below 256GiB 1717 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1718 * The device region size assumes 1GiB page max alignment per slot. 1719 */ 1720 device_memory_base = 1721 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1722 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1723 1724 /* Base address of the high IO region */ 1725 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1726 if (memtop > BIT_ULL(pa_bits)) { 1727 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1728 pa_bits, memtop - BIT_ULL(pa_bits)); 1729 exit(EXIT_FAILURE); 1730 } 1731 if (base < device_memory_base) { 1732 error_report("maxmem/slots too huge"); 1733 exit(EXIT_FAILURE); 1734 } 1735 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1736 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1737 } 1738 1739 /* We know for sure that at least the memory fits in the PA space */ 1740 vms->highest_gpa = memtop - 1; 1741 1742 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1743 hwaddr size = extended_memmap[i].size; 1744 bool fits; 1745 1746 base = ROUND_UP(base, size); 1747 vms->memmap[i].base = base; 1748 vms->memmap[i].size = size; 1749 1750 /* 1751 * Check each device to see if they fit in the PA space, 1752 * moving highest_gpa as we go. 1753 * 1754 * For each device that doesn't fit, disable it. 1755 */ 1756 fits = (base + size) <= BIT_ULL(pa_bits); 1757 if (fits) { 1758 vms->highest_gpa = base + size - 1; 1759 } 1760 1761 switch (i) { 1762 case VIRT_HIGH_GIC_REDIST2: 1763 vms->highmem_redists &= fits; 1764 break; 1765 case VIRT_HIGH_PCIE_ECAM: 1766 vms->highmem_ecam &= fits; 1767 break; 1768 case VIRT_HIGH_PCIE_MMIO: 1769 vms->highmem_mmio &= fits; 1770 break; 1771 } 1772 1773 base += size; 1774 } 1775 1776 if (device_memory_size > 0) { 1777 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1778 ms->device_memory->base = device_memory_base; 1779 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1780 "device-memory", device_memory_size); 1781 } 1782 } 1783 1784 /* 1785 * finalize_gic_version - Determines the final gic_version 1786 * according to the gic-version property 1787 * 1788 * Default GIC type is v2 1789 */ 1790 static void finalize_gic_version(VirtMachineState *vms) 1791 { 1792 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1793 1794 if (kvm_enabled()) { 1795 int probe_bitmap; 1796 1797 if (!kvm_irqchip_in_kernel()) { 1798 switch (vms->gic_version) { 1799 case VIRT_GIC_VERSION_HOST: 1800 warn_report( 1801 "gic-version=host not relevant with kernel-irqchip=off " 1802 "as only userspace GICv2 is supported. Using v2 ..."); 1803 return; 1804 case VIRT_GIC_VERSION_MAX: 1805 case VIRT_GIC_VERSION_NOSEL: 1806 vms->gic_version = VIRT_GIC_VERSION_2; 1807 return; 1808 case VIRT_GIC_VERSION_2: 1809 return; 1810 case VIRT_GIC_VERSION_3: 1811 error_report( 1812 "gic-version=3 is not supported with kernel-irqchip=off"); 1813 exit(1); 1814 case VIRT_GIC_VERSION_4: 1815 error_report( 1816 "gic-version=4 is not supported with kernel-irqchip=off"); 1817 exit(1); 1818 } 1819 } 1820 1821 probe_bitmap = kvm_arm_vgic_probe(); 1822 if (!probe_bitmap) { 1823 error_report("Unable to determine GIC version supported by host"); 1824 exit(1); 1825 } 1826 1827 switch (vms->gic_version) { 1828 case VIRT_GIC_VERSION_HOST: 1829 case VIRT_GIC_VERSION_MAX: 1830 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1831 vms->gic_version = VIRT_GIC_VERSION_3; 1832 } else { 1833 vms->gic_version = VIRT_GIC_VERSION_2; 1834 } 1835 return; 1836 case VIRT_GIC_VERSION_NOSEL: 1837 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1838 vms->gic_version = VIRT_GIC_VERSION_2; 1839 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1840 /* 1841 * in case the host does not support v2 in-kernel emulation or 1842 * the end-user requested more than 8 VCPUs we now default 1843 * to v3. In any case defaulting to v2 would be broken. 1844 */ 1845 vms->gic_version = VIRT_GIC_VERSION_3; 1846 } else if (max_cpus > GIC_NCPU) { 1847 error_report("host only supports in-kernel GICv2 emulation " 1848 "but more than 8 vcpus are requested"); 1849 exit(1); 1850 } 1851 break; 1852 case VIRT_GIC_VERSION_2: 1853 case VIRT_GIC_VERSION_3: 1854 break; 1855 case VIRT_GIC_VERSION_4: 1856 error_report("gic-version=4 is not supported with KVM"); 1857 exit(1); 1858 } 1859 1860 /* Check chosen version is effectively supported by the host */ 1861 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1862 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1863 error_report("host does not support in-kernel GICv2 emulation"); 1864 exit(1); 1865 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1866 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1867 error_report("host does not support in-kernel GICv3 emulation"); 1868 exit(1); 1869 } 1870 return; 1871 } 1872 1873 /* TCG mode */ 1874 switch (vms->gic_version) { 1875 case VIRT_GIC_VERSION_NOSEL: 1876 vms->gic_version = VIRT_GIC_VERSION_2; 1877 break; 1878 case VIRT_GIC_VERSION_MAX: 1879 if (module_object_class_by_name("arm-gicv3")) { 1880 /* CONFIG_ARM_GICV3_TCG was set */ 1881 if (vms->virt) { 1882 /* GICv4 only makes sense if CPU has EL2 */ 1883 vms->gic_version = VIRT_GIC_VERSION_4; 1884 } else { 1885 vms->gic_version = VIRT_GIC_VERSION_3; 1886 } 1887 } else { 1888 vms->gic_version = VIRT_GIC_VERSION_2; 1889 } 1890 break; 1891 case VIRT_GIC_VERSION_HOST: 1892 error_report("gic-version=host requires KVM"); 1893 exit(1); 1894 case VIRT_GIC_VERSION_4: 1895 if (!vms->virt) { 1896 error_report("gic-version=4 requires virtualization enabled"); 1897 exit(1); 1898 } 1899 break; 1900 case VIRT_GIC_VERSION_2: 1901 case VIRT_GIC_VERSION_3: 1902 break; 1903 } 1904 } 1905 1906 /* 1907 * virt_cpu_post_init() must be called after the CPUs have 1908 * been realized and the GIC has been created. 1909 */ 1910 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1911 { 1912 int max_cpus = MACHINE(vms)->smp.max_cpus; 1913 bool aarch64, pmu, steal_time; 1914 CPUState *cpu; 1915 1916 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1917 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1918 steal_time = object_property_get_bool(OBJECT(first_cpu), 1919 "kvm-steal-time", NULL); 1920 1921 if (kvm_enabled()) { 1922 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1923 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1924 1925 if (steal_time) { 1926 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1927 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1928 1929 /* The memory region size must be a multiple of host page size. */ 1930 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1931 1932 if (pvtime_size > pvtime_reg_size) { 1933 error_report("pvtime requires a %" HWADDR_PRId 1934 " byte memory region for %d CPUs," 1935 " but only %" HWADDR_PRId " has been reserved", 1936 pvtime_size, max_cpus, pvtime_reg_size); 1937 exit(1); 1938 } 1939 1940 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1941 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1942 } 1943 1944 CPU_FOREACH(cpu) { 1945 if (pmu) { 1946 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1947 if (kvm_irqchip_in_kernel()) { 1948 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1949 } 1950 kvm_arm_pmu_init(cpu); 1951 } 1952 if (steal_time) { 1953 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1954 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1955 } 1956 } 1957 } else { 1958 if (aarch64 && vms->highmem) { 1959 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1960 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1961 1962 if (pamax < requested_pa_size) { 1963 error_report("VCPU supports less PA bits (%d) than " 1964 "requested by the memory map (%d)", 1965 pamax, requested_pa_size); 1966 exit(1); 1967 } 1968 } 1969 } 1970 } 1971 1972 static void machvirt_init(MachineState *machine) 1973 { 1974 VirtMachineState *vms = VIRT_MACHINE(machine); 1975 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1976 MachineClass *mc = MACHINE_GET_CLASS(machine); 1977 const CPUArchIdList *possible_cpus; 1978 MemoryRegion *sysmem = get_system_memory(); 1979 MemoryRegion *secure_sysmem = NULL; 1980 MemoryRegion *tag_sysmem = NULL; 1981 MemoryRegion *secure_tag_sysmem = NULL; 1982 int n, virt_max_cpus; 1983 bool firmware_loaded; 1984 bool aarch64 = true; 1985 bool has_ged = !vmc->no_ged; 1986 unsigned int smp_cpus = machine->smp.cpus; 1987 unsigned int max_cpus = machine->smp.max_cpus; 1988 1989 if (!cpu_type_valid(machine->cpu_type)) { 1990 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1991 exit(1); 1992 } 1993 1994 possible_cpus = mc->possible_cpu_arch_ids(machine); 1995 1996 /* 1997 * In accelerated mode, the memory map is computed earlier in kvm_type() 1998 * to create a VM with the right number of IPA bits. 1999 */ 2000 if (!vms->memmap) { 2001 Object *cpuobj; 2002 ARMCPU *armcpu; 2003 int pa_bits; 2004 2005 /* 2006 * Instanciate a temporary CPU object to find out about what 2007 * we are about to deal with. Once this is done, get rid of 2008 * the object. 2009 */ 2010 cpuobj = object_new(possible_cpus->cpus[0].type); 2011 armcpu = ARM_CPU(cpuobj); 2012 2013 if (object_property_get_bool(cpuobj, "aarch64", NULL)) { 2014 pa_bits = arm_pamax(armcpu); 2015 } else if (arm_feature(&armcpu->env, ARM_FEATURE_LPAE)) { 2016 /* v7 with LPAE */ 2017 pa_bits = 40; 2018 } else { 2019 /* Anything else */ 2020 pa_bits = 32; 2021 } 2022 2023 object_unref(cpuobj); 2024 2025 virt_set_memmap(vms, pa_bits); 2026 } 2027 2028 /* We can probe only here because during property set 2029 * KVM is not available yet 2030 */ 2031 finalize_gic_version(vms); 2032 2033 if (vms->secure) { 2034 /* 2035 * The Secure view of the world is the same as the NonSecure, 2036 * but with a few extra devices. Create it as a container region 2037 * containing the system memory at low priority; any secure-only 2038 * devices go in at higher priority and take precedence. 2039 */ 2040 secure_sysmem = g_new(MemoryRegion, 1); 2041 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2042 UINT64_MAX); 2043 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2044 } 2045 2046 firmware_loaded = virt_firmware_init(vms, sysmem, 2047 secure_sysmem ?: sysmem); 2048 2049 /* If we have an EL3 boot ROM then the assumption is that it will 2050 * implement PSCI itself, so disable QEMU's internal implementation 2051 * so it doesn't get in the way. Instead of starting secondary 2052 * CPUs in PSCI powerdown state we will start them all running and 2053 * let the boot ROM sort them out. 2054 * The usual case is that we do use QEMU's PSCI implementation; 2055 * if the guest has EL2 then we will use SMC as the conduit, 2056 * and otherwise we will use HVC (for backwards compatibility and 2057 * because if we're using KVM then we must use HVC). 2058 */ 2059 if (vms->secure && firmware_loaded) { 2060 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2061 } else if (vms->virt) { 2062 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2063 } else { 2064 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2065 } 2066 2067 /* 2068 * The maximum number of CPUs depends on the GIC version, or on how 2069 * many redistributors we can fit into the memory map (which in turn 2070 * depends on whether this is a GICv3 or v4). 2071 */ 2072 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2073 virt_max_cpus = GIC_NCPU; 2074 } else { 2075 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + 2076 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2077 } 2078 2079 if (max_cpus > virt_max_cpus) { 2080 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2081 "supported by machine 'mach-virt' (%d)", 2082 max_cpus, virt_max_cpus); 2083 exit(1); 2084 } 2085 2086 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2087 error_report("mach-virt: %s does not support providing " 2088 "Security extensions (TrustZone) to the guest CPU", 2089 kvm_enabled() ? "KVM" : "HVF"); 2090 exit(1); 2091 } 2092 2093 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2094 error_report("mach-virt: %s does not support providing " 2095 "Virtualization extensions to the guest CPU", 2096 kvm_enabled() ? "KVM" : "HVF"); 2097 exit(1); 2098 } 2099 2100 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2101 error_report("mach-virt: %s does not support providing " 2102 "MTE to the guest CPU", 2103 kvm_enabled() ? "KVM" : "HVF"); 2104 exit(1); 2105 } 2106 2107 create_fdt(vms); 2108 2109 assert(possible_cpus->len == max_cpus); 2110 for (n = 0; n < possible_cpus->len; n++) { 2111 Object *cpuobj; 2112 CPUState *cs; 2113 2114 if (n >= smp_cpus) { 2115 break; 2116 } 2117 2118 cpuobj = object_new(possible_cpus->cpus[n].type); 2119 object_property_set_int(cpuobj, "mp-affinity", 2120 possible_cpus->cpus[n].arch_id, NULL); 2121 2122 cs = CPU(cpuobj); 2123 cs->cpu_index = n; 2124 2125 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2126 &error_fatal); 2127 2128 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2129 2130 if (!vms->secure) { 2131 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2132 } 2133 2134 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2135 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2136 } 2137 2138 if (vmc->kvm_no_adjvtime && 2139 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2140 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2141 } 2142 2143 if (vmc->no_kvm_steal_time && 2144 object_property_find(cpuobj, "kvm-steal-time")) { 2145 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2146 } 2147 2148 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2149 object_property_set_bool(cpuobj, "pmu", false, NULL); 2150 } 2151 2152 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2153 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2154 } 2155 2156 if (object_property_find(cpuobj, "reset-cbar")) { 2157 object_property_set_int(cpuobj, "reset-cbar", 2158 vms->memmap[VIRT_CPUPERIPHS].base, 2159 &error_abort); 2160 } 2161 2162 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2163 &error_abort); 2164 if (vms->secure) { 2165 object_property_set_link(cpuobj, "secure-memory", 2166 OBJECT(secure_sysmem), &error_abort); 2167 } 2168 2169 if (vms->mte) { 2170 /* Create the memory region only once, but link to all cpus. */ 2171 if (!tag_sysmem) { 2172 /* 2173 * The property exists only if MemTag is supported. 2174 * If it is, we must allocate the ram to back that up. 2175 */ 2176 if (!object_property_find(cpuobj, "tag-memory")) { 2177 error_report("MTE requested, but not supported " 2178 "by the guest CPU"); 2179 exit(1); 2180 } 2181 2182 tag_sysmem = g_new(MemoryRegion, 1); 2183 memory_region_init(tag_sysmem, OBJECT(machine), 2184 "tag-memory", UINT64_MAX / 32); 2185 2186 if (vms->secure) { 2187 secure_tag_sysmem = g_new(MemoryRegion, 1); 2188 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2189 "secure-tag-memory", UINT64_MAX / 32); 2190 2191 /* As with ram, secure-tag takes precedence over tag. */ 2192 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2193 tag_sysmem, -1); 2194 } 2195 } 2196 2197 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2198 &error_abort); 2199 if (vms->secure) { 2200 object_property_set_link(cpuobj, "secure-tag-memory", 2201 OBJECT(secure_tag_sysmem), 2202 &error_abort); 2203 } 2204 } 2205 2206 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2207 object_unref(cpuobj); 2208 } 2209 fdt_add_timer_nodes(vms); 2210 fdt_add_cpu_nodes(vms); 2211 2212 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2213 machine->ram); 2214 if (machine->device_memory) { 2215 memory_region_add_subregion(sysmem, machine->device_memory->base, 2216 &machine->device_memory->mr); 2217 } 2218 2219 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2220 2221 create_gic(vms, sysmem); 2222 2223 virt_cpu_post_init(vms, sysmem); 2224 2225 fdt_add_pmu_nodes(vms); 2226 2227 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2228 2229 if (vms->secure) { 2230 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2231 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2232 } 2233 2234 if (tag_sysmem) { 2235 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2236 machine->ram_size, "mach-virt.tag"); 2237 } 2238 2239 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2240 2241 create_rtc(vms); 2242 2243 create_pcie(vms); 2244 2245 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2246 vms->acpi_dev = create_acpi_ged(vms); 2247 } else { 2248 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2249 } 2250 2251 if (vms->secure && !vmc->no_secure_gpio) { 2252 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2253 } 2254 2255 /* connect powerdown request */ 2256 vms->powerdown_notifier.notify = virt_powerdown_req; 2257 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2258 2259 /* Create mmio transports, so the user can create virtio backends 2260 * (which will be automatically plugged in to the transports). If 2261 * no backend is created the transport will just sit harmlessly idle. 2262 */ 2263 create_virtio_devices(vms); 2264 2265 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2266 rom_set_fw(vms->fw_cfg); 2267 2268 create_platform_bus(vms); 2269 2270 if (machine->nvdimms_state->is_enabled) { 2271 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2272 .space_id = AML_AS_SYSTEM_MEMORY, 2273 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2274 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2275 }; 2276 2277 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2278 arm_virt_nvdimm_acpi_dsmio, 2279 vms->fw_cfg, OBJECT(vms)); 2280 } 2281 2282 vms->bootinfo.ram_size = machine->ram_size; 2283 vms->bootinfo.board_id = -1; 2284 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2285 vms->bootinfo.get_dtb = machvirt_dtb; 2286 vms->bootinfo.skip_dtb_autoload = true; 2287 vms->bootinfo.firmware_loaded = firmware_loaded; 2288 vms->bootinfo.psci_conduit = vms->psci_conduit; 2289 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2290 2291 vms->machine_done.notify = virt_machine_done; 2292 qemu_add_machine_init_done_notifier(&vms->machine_done); 2293 } 2294 2295 static bool virt_get_secure(Object *obj, Error **errp) 2296 { 2297 VirtMachineState *vms = VIRT_MACHINE(obj); 2298 2299 return vms->secure; 2300 } 2301 2302 static void virt_set_secure(Object *obj, bool value, Error **errp) 2303 { 2304 VirtMachineState *vms = VIRT_MACHINE(obj); 2305 2306 vms->secure = value; 2307 } 2308 2309 static bool virt_get_virt(Object *obj, Error **errp) 2310 { 2311 VirtMachineState *vms = VIRT_MACHINE(obj); 2312 2313 return vms->virt; 2314 } 2315 2316 static void virt_set_virt(Object *obj, bool value, Error **errp) 2317 { 2318 VirtMachineState *vms = VIRT_MACHINE(obj); 2319 2320 vms->virt = value; 2321 } 2322 2323 static bool virt_get_highmem(Object *obj, Error **errp) 2324 { 2325 VirtMachineState *vms = VIRT_MACHINE(obj); 2326 2327 return vms->highmem; 2328 } 2329 2330 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2331 { 2332 VirtMachineState *vms = VIRT_MACHINE(obj); 2333 2334 vms->highmem = value; 2335 } 2336 2337 static bool virt_get_its(Object *obj, Error **errp) 2338 { 2339 VirtMachineState *vms = VIRT_MACHINE(obj); 2340 2341 return vms->its; 2342 } 2343 2344 static void virt_set_its(Object *obj, bool value, Error **errp) 2345 { 2346 VirtMachineState *vms = VIRT_MACHINE(obj); 2347 2348 vms->its = value; 2349 } 2350 2351 static bool virt_get_dtb_kaslr_seed(Object *obj, Error **errp) 2352 { 2353 VirtMachineState *vms = VIRT_MACHINE(obj); 2354 2355 return vms->dtb_kaslr_seed; 2356 } 2357 2358 static void virt_set_dtb_kaslr_seed(Object *obj, bool value, Error **errp) 2359 { 2360 VirtMachineState *vms = VIRT_MACHINE(obj); 2361 2362 vms->dtb_kaslr_seed = value; 2363 } 2364 2365 static char *virt_get_oem_id(Object *obj, Error **errp) 2366 { 2367 VirtMachineState *vms = VIRT_MACHINE(obj); 2368 2369 return g_strdup(vms->oem_id); 2370 } 2371 2372 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2373 { 2374 VirtMachineState *vms = VIRT_MACHINE(obj); 2375 size_t len = strlen(value); 2376 2377 if (len > 6) { 2378 error_setg(errp, 2379 "User specified oem-id value is bigger than 6 bytes in size"); 2380 return; 2381 } 2382 2383 strncpy(vms->oem_id, value, 6); 2384 } 2385 2386 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2387 { 2388 VirtMachineState *vms = VIRT_MACHINE(obj); 2389 2390 return g_strdup(vms->oem_table_id); 2391 } 2392 2393 static void virt_set_oem_table_id(Object *obj, const char *value, 2394 Error **errp) 2395 { 2396 VirtMachineState *vms = VIRT_MACHINE(obj); 2397 size_t len = strlen(value); 2398 2399 if (len > 8) { 2400 error_setg(errp, 2401 "User specified oem-table-id value is bigger than 8 bytes in size"); 2402 return; 2403 } 2404 strncpy(vms->oem_table_id, value, 8); 2405 } 2406 2407 2408 bool virt_is_acpi_enabled(VirtMachineState *vms) 2409 { 2410 if (vms->acpi == ON_OFF_AUTO_OFF) { 2411 return false; 2412 } 2413 return true; 2414 } 2415 2416 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2417 void *opaque, Error **errp) 2418 { 2419 VirtMachineState *vms = VIRT_MACHINE(obj); 2420 OnOffAuto acpi = vms->acpi; 2421 2422 visit_type_OnOffAuto(v, name, &acpi, errp); 2423 } 2424 2425 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2426 void *opaque, Error **errp) 2427 { 2428 VirtMachineState *vms = VIRT_MACHINE(obj); 2429 2430 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2431 } 2432 2433 static bool virt_get_ras(Object *obj, Error **errp) 2434 { 2435 VirtMachineState *vms = VIRT_MACHINE(obj); 2436 2437 return vms->ras; 2438 } 2439 2440 static void virt_set_ras(Object *obj, bool value, Error **errp) 2441 { 2442 VirtMachineState *vms = VIRT_MACHINE(obj); 2443 2444 vms->ras = value; 2445 } 2446 2447 static bool virt_get_mte(Object *obj, Error **errp) 2448 { 2449 VirtMachineState *vms = VIRT_MACHINE(obj); 2450 2451 return vms->mte; 2452 } 2453 2454 static void virt_set_mte(Object *obj, bool value, Error **errp) 2455 { 2456 VirtMachineState *vms = VIRT_MACHINE(obj); 2457 2458 vms->mte = value; 2459 } 2460 2461 static char *virt_get_gic_version(Object *obj, Error **errp) 2462 { 2463 VirtMachineState *vms = VIRT_MACHINE(obj); 2464 const char *val; 2465 2466 switch (vms->gic_version) { 2467 case VIRT_GIC_VERSION_4: 2468 val = "4"; 2469 break; 2470 case VIRT_GIC_VERSION_3: 2471 val = "3"; 2472 break; 2473 default: 2474 val = "2"; 2475 break; 2476 } 2477 return g_strdup(val); 2478 } 2479 2480 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2481 { 2482 VirtMachineState *vms = VIRT_MACHINE(obj); 2483 2484 if (!strcmp(value, "4")) { 2485 vms->gic_version = VIRT_GIC_VERSION_4; 2486 } else if (!strcmp(value, "3")) { 2487 vms->gic_version = VIRT_GIC_VERSION_3; 2488 } else if (!strcmp(value, "2")) { 2489 vms->gic_version = VIRT_GIC_VERSION_2; 2490 } else if (!strcmp(value, "host")) { 2491 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2492 } else if (!strcmp(value, "max")) { 2493 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2494 } else { 2495 error_setg(errp, "Invalid gic-version value"); 2496 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2497 } 2498 } 2499 2500 static char *virt_get_iommu(Object *obj, Error **errp) 2501 { 2502 VirtMachineState *vms = VIRT_MACHINE(obj); 2503 2504 switch (vms->iommu) { 2505 case VIRT_IOMMU_NONE: 2506 return g_strdup("none"); 2507 case VIRT_IOMMU_SMMUV3: 2508 return g_strdup("smmuv3"); 2509 default: 2510 g_assert_not_reached(); 2511 } 2512 } 2513 2514 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2515 { 2516 VirtMachineState *vms = VIRT_MACHINE(obj); 2517 2518 if (!strcmp(value, "smmuv3")) { 2519 vms->iommu = VIRT_IOMMU_SMMUV3; 2520 } else if (!strcmp(value, "none")) { 2521 vms->iommu = VIRT_IOMMU_NONE; 2522 } else { 2523 error_setg(errp, "Invalid iommu value"); 2524 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2525 } 2526 } 2527 2528 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2529 { 2530 VirtMachineState *vms = VIRT_MACHINE(obj); 2531 2532 return vms->default_bus_bypass_iommu; 2533 } 2534 2535 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2536 Error **errp) 2537 { 2538 VirtMachineState *vms = VIRT_MACHINE(obj); 2539 2540 vms->default_bus_bypass_iommu = value; 2541 } 2542 2543 static CpuInstanceProperties 2544 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2545 { 2546 MachineClass *mc = MACHINE_GET_CLASS(ms); 2547 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2548 2549 assert(cpu_index < possible_cpus->len); 2550 return possible_cpus->cpus[cpu_index].props; 2551 } 2552 2553 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2554 { 2555 return idx % ms->numa_state->num_nodes; 2556 } 2557 2558 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2559 { 2560 int n; 2561 unsigned int max_cpus = ms->smp.max_cpus; 2562 VirtMachineState *vms = VIRT_MACHINE(ms); 2563 2564 if (ms->possible_cpus) { 2565 assert(ms->possible_cpus->len == max_cpus); 2566 return ms->possible_cpus; 2567 } 2568 2569 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2570 sizeof(CPUArchId) * max_cpus); 2571 ms->possible_cpus->len = max_cpus; 2572 for (n = 0; n < ms->possible_cpus->len; n++) { 2573 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2574 ms->possible_cpus->cpus[n].arch_id = 2575 virt_cpu_mp_affinity(vms, n); 2576 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2577 ms->possible_cpus->cpus[n].props.thread_id = n; 2578 } 2579 return ms->possible_cpus; 2580 } 2581 2582 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2583 Error **errp) 2584 { 2585 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2586 const MachineState *ms = MACHINE(hotplug_dev); 2587 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2588 2589 if (!vms->acpi_dev) { 2590 error_setg(errp, 2591 "memory hotplug is not enabled: missing acpi-ged device"); 2592 return; 2593 } 2594 2595 if (vms->mte) { 2596 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2597 return; 2598 } 2599 2600 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2601 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2602 return; 2603 } 2604 2605 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2606 } 2607 2608 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2609 DeviceState *dev, Error **errp) 2610 { 2611 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2612 MachineState *ms = MACHINE(hotplug_dev); 2613 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2614 2615 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2616 2617 if (is_nvdimm) { 2618 nvdimm_plug(ms->nvdimms_state); 2619 } 2620 2621 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2622 dev, &error_abort); 2623 } 2624 2625 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2626 DeviceState *dev, Error **errp) 2627 { 2628 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2629 Error *local_err = NULL; 2630 2631 if (!hotplug_dev2 && dev->hotplugged) { 2632 /* 2633 * Without a bus hotplug handler, we cannot control the plug/unplug 2634 * order. We should never reach this point when hotplugging on ARM. 2635 * However, it's nice to add a safety net, similar to what we have 2636 * on x86. 2637 */ 2638 error_setg(errp, "hotplug of virtio based memory devices not supported" 2639 " on this bus."); 2640 return; 2641 } 2642 /* 2643 * First, see if we can plug this memory device at all. If that 2644 * succeeds, branch of to the actual hotplug handler. 2645 */ 2646 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2647 &local_err); 2648 if (!local_err && hotplug_dev2) { 2649 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2650 } 2651 error_propagate(errp, local_err); 2652 } 2653 2654 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2655 DeviceState *dev, Error **errp) 2656 { 2657 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2658 Error *local_err = NULL; 2659 2660 /* 2661 * Plug the memory device first and then branch off to the actual 2662 * hotplug handler. If that one fails, we can easily undo the memory 2663 * device bits. 2664 */ 2665 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2666 if (hotplug_dev2) { 2667 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2668 if (local_err) { 2669 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2670 } 2671 } 2672 error_propagate(errp, local_err); 2673 } 2674 2675 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2676 DeviceState *dev, Error **errp) 2677 { 2678 /* We don't support hot unplug of virtio based memory devices */ 2679 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2680 } 2681 2682 2683 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2684 DeviceState *dev, Error **errp) 2685 { 2686 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2687 2688 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2689 virt_memory_pre_plug(hotplug_dev, dev, errp); 2690 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2691 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2692 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2693 hwaddr db_start = 0, db_end = 0; 2694 char *resv_prop_str; 2695 2696 if (vms->iommu != VIRT_IOMMU_NONE) { 2697 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2698 return; 2699 } 2700 2701 switch (vms->msi_controller) { 2702 case VIRT_MSI_CTRL_NONE: 2703 return; 2704 case VIRT_MSI_CTRL_ITS: 2705 /* GITS_TRANSLATER page */ 2706 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2707 db_end = base_memmap[VIRT_GIC_ITS].base + 2708 base_memmap[VIRT_GIC_ITS].size - 1; 2709 break; 2710 case VIRT_MSI_CTRL_GICV2M: 2711 /* MSI_SETSPI_NS page */ 2712 db_start = base_memmap[VIRT_GIC_V2M].base; 2713 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2714 break; 2715 } 2716 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2717 db_start, db_end, 2718 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2719 2720 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2721 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2722 resv_prop_str, errp); 2723 g_free(resv_prop_str); 2724 } 2725 } 2726 2727 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2728 DeviceState *dev, Error **errp) 2729 { 2730 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2731 2732 if (vms->platform_bus_dev) { 2733 MachineClass *mc = MACHINE_GET_CLASS(vms); 2734 2735 if (device_is_dynamic_sysbus(mc, dev)) { 2736 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2737 SYS_BUS_DEVICE(dev)); 2738 } 2739 } 2740 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2741 virt_memory_plug(hotplug_dev, dev, errp); 2742 } 2743 2744 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2745 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2746 } 2747 2748 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2749 PCIDevice *pdev = PCI_DEVICE(dev); 2750 2751 vms->iommu = VIRT_IOMMU_VIRTIO; 2752 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2753 create_virtio_iommu_dt_bindings(vms); 2754 } 2755 } 2756 2757 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2758 DeviceState *dev, Error **errp) 2759 { 2760 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2761 Error *local_err = NULL; 2762 2763 if (!vms->acpi_dev) { 2764 error_setg(&local_err, 2765 "memory hotplug is not enabled: missing acpi-ged device"); 2766 goto out; 2767 } 2768 2769 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2770 error_setg(&local_err, 2771 "nvdimm device hot unplug is not supported yet."); 2772 goto out; 2773 } 2774 2775 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2776 &local_err); 2777 out: 2778 error_propagate(errp, local_err); 2779 } 2780 2781 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2782 DeviceState *dev, Error **errp) 2783 { 2784 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2785 Error *local_err = NULL; 2786 2787 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2788 if (local_err) { 2789 goto out; 2790 } 2791 2792 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2793 qdev_unrealize(dev); 2794 2795 out: 2796 error_propagate(errp, local_err); 2797 } 2798 2799 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2800 DeviceState *dev, Error **errp) 2801 { 2802 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2803 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2804 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2805 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2806 } else { 2807 error_setg(errp, "device unplug request for unsupported device" 2808 " type: %s", object_get_typename(OBJECT(dev))); 2809 } 2810 } 2811 2812 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2813 DeviceState *dev, Error **errp) 2814 { 2815 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2816 virt_dimm_unplug(hotplug_dev, dev, errp); 2817 } else { 2818 error_setg(errp, "virt: device unplug for unsupported device" 2819 " type: %s", object_get_typename(OBJECT(dev))); 2820 } 2821 } 2822 2823 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2824 DeviceState *dev) 2825 { 2826 MachineClass *mc = MACHINE_GET_CLASS(machine); 2827 2828 if (device_is_dynamic_sysbus(mc, dev) || 2829 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2830 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2831 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2832 return HOTPLUG_HANDLER(machine); 2833 } 2834 return NULL; 2835 } 2836 2837 /* 2838 * for arm64 kvm_type [7-0] encodes the requested number of bits 2839 * in the IPA address space 2840 */ 2841 static int virt_kvm_type(MachineState *ms, const char *type_str) 2842 { 2843 VirtMachineState *vms = VIRT_MACHINE(ms); 2844 int max_vm_pa_size, requested_pa_size; 2845 bool fixed_ipa; 2846 2847 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2848 2849 /* we freeze the memory map to compute the highest gpa */ 2850 virt_set_memmap(vms, max_vm_pa_size); 2851 2852 requested_pa_size = 64 - clz64(vms->highest_gpa); 2853 2854 /* 2855 * KVM requires the IPA size to be at least 32 bits. 2856 */ 2857 if (requested_pa_size < 32) { 2858 requested_pa_size = 32; 2859 } 2860 2861 if (requested_pa_size > max_vm_pa_size) { 2862 error_report("-m and ,maxmem option values " 2863 "require an IPA range (%d bits) larger than " 2864 "the one supported by the host (%d bits)", 2865 requested_pa_size, max_vm_pa_size); 2866 exit(1); 2867 } 2868 /* 2869 * We return the requested PA log size, unless KVM only supports 2870 * the implicit legacy 40b IPA setting, in which case the kvm_type 2871 * must be 0. 2872 */ 2873 return fixed_ipa ? 0 : requested_pa_size; 2874 } 2875 2876 static void virt_machine_class_init(ObjectClass *oc, void *data) 2877 { 2878 MachineClass *mc = MACHINE_CLASS(oc); 2879 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2880 2881 mc->init = machvirt_init; 2882 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2883 * The value may be reduced later when we have more information about the 2884 * configuration of the particular instance. 2885 */ 2886 mc->max_cpus = 512; 2887 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2888 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2889 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2890 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2891 #ifdef CONFIG_TPM 2892 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2893 #endif 2894 mc->block_default_type = IF_VIRTIO; 2895 mc->no_cdrom = 1; 2896 mc->pci_allow_0_address = true; 2897 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2898 mc->minimum_page_bits = 12; 2899 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2900 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2901 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2902 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2903 mc->kvm_type = virt_kvm_type; 2904 assert(!mc->get_hotplug_handler); 2905 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2906 hc->pre_plug = virt_machine_device_pre_plug_cb; 2907 hc->plug = virt_machine_device_plug_cb; 2908 hc->unplug_request = virt_machine_device_unplug_request_cb; 2909 hc->unplug = virt_machine_device_unplug_cb; 2910 mc->nvdimm_supported = true; 2911 mc->smp_props.clusters_supported = true; 2912 mc->auto_enable_numa_with_memhp = true; 2913 mc->auto_enable_numa_with_memdev = true; 2914 mc->default_ram_id = "mach-virt.ram"; 2915 2916 object_class_property_add(oc, "acpi", "OnOffAuto", 2917 virt_get_acpi, virt_set_acpi, 2918 NULL, NULL); 2919 object_class_property_set_description(oc, "acpi", 2920 "Enable ACPI"); 2921 object_class_property_add_bool(oc, "secure", virt_get_secure, 2922 virt_set_secure); 2923 object_class_property_set_description(oc, "secure", 2924 "Set on/off to enable/disable the ARM " 2925 "Security Extensions (TrustZone)"); 2926 2927 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2928 virt_set_virt); 2929 object_class_property_set_description(oc, "virtualization", 2930 "Set on/off to enable/disable emulating a " 2931 "guest CPU which implements the ARM " 2932 "Virtualization Extensions"); 2933 2934 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2935 virt_set_highmem); 2936 object_class_property_set_description(oc, "highmem", 2937 "Set on/off to enable/disable using " 2938 "physical address space above 32 bits"); 2939 2940 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 2941 virt_set_gic_version); 2942 object_class_property_set_description(oc, "gic-version", 2943 "Set GIC version. " 2944 "Valid values are 2, 3, 4, host and max"); 2945 2946 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 2947 object_class_property_set_description(oc, "iommu", 2948 "Set the IOMMU type. " 2949 "Valid values are none and smmuv3"); 2950 2951 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 2952 virt_get_default_bus_bypass_iommu, 2953 virt_set_default_bus_bypass_iommu); 2954 object_class_property_set_description(oc, "default-bus-bypass-iommu", 2955 "Set on/off to enable/disable " 2956 "bypass_iommu for default root bus"); 2957 2958 object_class_property_add_bool(oc, "ras", virt_get_ras, 2959 virt_set_ras); 2960 object_class_property_set_description(oc, "ras", 2961 "Set on/off to enable/disable reporting host memory errors " 2962 "to a KVM guest using ACPI and guest external abort exceptions"); 2963 2964 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 2965 object_class_property_set_description(oc, "mte", 2966 "Set on/off to enable/disable emulating a " 2967 "guest CPU which implements the ARM " 2968 "Memory Tagging Extension"); 2969 2970 object_class_property_add_bool(oc, "its", virt_get_its, 2971 virt_set_its); 2972 object_class_property_set_description(oc, "its", 2973 "Set on/off to enable/disable " 2974 "ITS instantiation"); 2975 2976 object_class_property_add_bool(oc, "dtb-kaslr-seed", 2977 virt_get_dtb_kaslr_seed, 2978 virt_set_dtb_kaslr_seed); 2979 object_class_property_set_description(oc, "dtb-kaslr-seed", 2980 "Set off to disable passing of kaslr-seed " 2981 "dtb node to guest"); 2982 2983 object_class_property_add_str(oc, "x-oem-id", 2984 virt_get_oem_id, 2985 virt_set_oem_id); 2986 object_class_property_set_description(oc, "x-oem-id", 2987 "Override the default value of field OEMID " 2988 "in ACPI table header." 2989 "The string may be up to 6 bytes in size"); 2990 2991 2992 object_class_property_add_str(oc, "x-oem-table-id", 2993 virt_get_oem_table_id, 2994 virt_set_oem_table_id); 2995 object_class_property_set_description(oc, "x-oem-table-id", 2996 "Override the default value of field OEM Table ID " 2997 "in ACPI table header." 2998 "The string may be up to 8 bytes in size"); 2999 3000 } 3001 3002 static void virt_instance_init(Object *obj) 3003 { 3004 VirtMachineState *vms = VIRT_MACHINE(obj); 3005 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3006 3007 /* EL3 is disabled by default on virt: this makes us consistent 3008 * between KVM and TCG for this board, and it also allows us to 3009 * boot UEFI blobs which assume no TrustZone support. 3010 */ 3011 vms->secure = false; 3012 3013 /* EL2 is also disabled by default, for similar reasons */ 3014 vms->virt = false; 3015 3016 /* High memory is enabled by default */ 3017 vms->highmem = true; 3018 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3019 3020 vms->highmem_ecam = !vmc->no_highmem_ecam; 3021 vms->highmem_mmio = true; 3022 vms->highmem_redists = true; 3023 3024 if (vmc->no_its) { 3025 vms->its = false; 3026 } else { 3027 /* Default allows ITS instantiation */ 3028 vms->its = true; 3029 3030 if (vmc->no_tcg_its) { 3031 vms->tcg_its = false; 3032 } else { 3033 vms->tcg_its = true; 3034 } 3035 } 3036 3037 /* Default disallows iommu instantiation */ 3038 vms->iommu = VIRT_IOMMU_NONE; 3039 3040 /* The default root bus is attached to iommu by default */ 3041 vms->default_bus_bypass_iommu = false; 3042 3043 /* Default disallows RAS instantiation */ 3044 vms->ras = false; 3045 3046 /* MTE is disabled by default. */ 3047 vms->mte = false; 3048 3049 /* Supply a kaslr-seed by default */ 3050 vms->dtb_kaslr_seed = true; 3051 3052 vms->irqmap = a15irqmap; 3053 3054 virt_flash_create(vms); 3055 3056 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3057 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3058 } 3059 3060 static const TypeInfo virt_machine_info = { 3061 .name = TYPE_VIRT_MACHINE, 3062 .parent = TYPE_MACHINE, 3063 .abstract = true, 3064 .instance_size = sizeof(VirtMachineState), 3065 .class_size = sizeof(VirtMachineClass), 3066 .class_init = virt_machine_class_init, 3067 .instance_init = virt_instance_init, 3068 .interfaces = (InterfaceInfo[]) { 3069 { TYPE_HOTPLUG_HANDLER }, 3070 { } 3071 }, 3072 }; 3073 3074 static void machvirt_machine_init(void) 3075 { 3076 type_register_static(&virt_machine_info); 3077 } 3078 type_init(machvirt_machine_init); 3079 3080 static void virt_machine_7_1_options(MachineClass *mc) 3081 { 3082 } 3083 DEFINE_VIRT_MACHINE_AS_LATEST(7, 1) 3084 3085 static void virt_machine_7_0_options(MachineClass *mc) 3086 { 3087 virt_machine_7_1_options(mc); 3088 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3089 } 3090 DEFINE_VIRT_MACHINE(7, 0) 3091 3092 static void virt_machine_6_2_options(MachineClass *mc) 3093 { 3094 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3095 3096 virt_machine_7_0_options(mc); 3097 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3098 vmc->no_tcg_lpa2 = true; 3099 } 3100 DEFINE_VIRT_MACHINE(6, 2) 3101 3102 static void virt_machine_6_1_options(MachineClass *mc) 3103 { 3104 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3105 3106 virt_machine_6_2_options(mc); 3107 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3108 mc->smp_props.prefer_sockets = true; 3109 vmc->no_cpu_topology = true; 3110 3111 /* qemu ITS was introduced with 6.2 */ 3112 vmc->no_tcg_its = true; 3113 } 3114 DEFINE_VIRT_MACHINE(6, 1) 3115 3116 static void virt_machine_6_0_options(MachineClass *mc) 3117 { 3118 virt_machine_6_1_options(mc); 3119 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3120 } 3121 DEFINE_VIRT_MACHINE(6, 0) 3122 3123 static void virt_machine_5_2_options(MachineClass *mc) 3124 { 3125 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3126 3127 virt_machine_6_0_options(mc); 3128 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3129 vmc->no_secure_gpio = true; 3130 } 3131 DEFINE_VIRT_MACHINE(5, 2) 3132 3133 static void virt_machine_5_1_options(MachineClass *mc) 3134 { 3135 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3136 3137 virt_machine_5_2_options(mc); 3138 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3139 vmc->no_kvm_steal_time = true; 3140 } 3141 DEFINE_VIRT_MACHINE(5, 1) 3142 3143 static void virt_machine_5_0_options(MachineClass *mc) 3144 { 3145 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3146 3147 virt_machine_5_1_options(mc); 3148 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3149 mc->numa_mem_supported = true; 3150 vmc->acpi_expose_flash = true; 3151 mc->auto_enable_numa_with_memdev = false; 3152 } 3153 DEFINE_VIRT_MACHINE(5, 0) 3154 3155 static void virt_machine_4_2_options(MachineClass *mc) 3156 { 3157 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3158 3159 virt_machine_5_0_options(mc); 3160 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3161 vmc->kvm_no_adjvtime = true; 3162 } 3163 DEFINE_VIRT_MACHINE(4, 2) 3164 3165 static void virt_machine_4_1_options(MachineClass *mc) 3166 { 3167 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3168 3169 virt_machine_4_2_options(mc); 3170 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3171 vmc->no_ged = true; 3172 mc->auto_enable_numa_with_memhp = false; 3173 } 3174 DEFINE_VIRT_MACHINE(4, 1) 3175 3176 static void virt_machine_4_0_options(MachineClass *mc) 3177 { 3178 virt_machine_4_1_options(mc); 3179 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3180 } 3181 DEFINE_VIRT_MACHINE(4, 0) 3182 3183 static void virt_machine_3_1_options(MachineClass *mc) 3184 { 3185 virt_machine_4_0_options(mc); 3186 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3187 } 3188 DEFINE_VIRT_MACHINE(3, 1) 3189 3190 static void virt_machine_3_0_options(MachineClass *mc) 3191 { 3192 virt_machine_3_1_options(mc); 3193 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3194 } 3195 DEFINE_VIRT_MACHINE(3, 0) 3196 3197 static void virt_machine_2_12_options(MachineClass *mc) 3198 { 3199 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3200 3201 virt_machine_3_0_options(mc); 3202 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3203 vmc->no_highmem_ecam = true; 3204 mc->max_cpus = 255; 3205 } 3206 DEFINE_VIRT_MACHINE(2, 12) 3207 3208 static void virt_machine_2_11_options(MachineClass *mc) 3209 { 3210 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3211 3212 virt_machine_2_12_options(mc); 3213 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3214 vmc->smbios_old_sys_ver = true; 3215 } 3216 DEFINE_VIRT_MACHINE(2, 11) 3217 3218 static void virt_machine_2_10_options(MachineClass *mc) 3219 { 3220 virt_machine_2_11_options(mc); 3221 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3222 /* before 2.11 we never faulted accesses to bad addresses */ 3223 mc->ignore_memory_transaction_failures = true; 3224 } 3225 DEFINE_VIRT_MACHINE(2, 10) 3226 3227 static void virt_machine_2_9_options(MachineClass *mc) 3228 { 3229 virt_machine_2_10_options(mc); 3230 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3231 } 3232 DEFINE_VIRT_MACHINE(2, 9) 3233 3234 static void virt_machine_2_8_options(MachineClass *mc) 3235 { 3236 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3237 3238 virt_machine_2_9_options(mc); 3239 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3240 /* For 2.8 and earlier we falsely claimed in the DT that 3241 * our timers were edge-triggered, not level-triggered. 3242 */ 3243 vmc->claim_edge_triggered_timers = true; 3244 } 3245 DEFINE_VIRT_MACHINE(2, 8) 3246 3247 static void virt_machine_2_7_options(MachineClass *mc) 3248 { 3249 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3250 3251 virt_machine_2_8_options(mc); 3252 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3253 /* ITS was introduced with 2.8 */ 3254 vmc->no_its = true; 3255 /* Stick with 1K pages for migration compatibility */ 3256 mc->minimum_page_bits = 0; 3257 } 3258 DEFINE_VIRT_MACHINE(2, 7) 3259 3260 static void virt_machine_2_6_options(MachineClass *mc) 3261 { 3262 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3263 3264 virt_machine_2_7_options(mc); 3265 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3266 vmc->disallow_affinity_adjustment = true; 3267 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3268 vmc->no_pmu = true; 3269 } 3270 DEFINE_VIRT_MACHINE(2, 6) 3271