1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/compat.h" 45 #include "hw/loader.h" 46 #include "exec/address-spaces.h" 47 #include "qemu/bitops.h" 48 #include "qemu/error-report.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/arm/sysbus-fdt.h" 51 #include "hw/platform-bus.h" 52 #include "hw/arm/fdt.h" 53 #include "hw/intc/arm_gic.h" 54 #include "hw/intc/arm_gicv3_common.h" 55 #include "kvm_arm.h" 56 #include "hw/smbios/smbios.h" 57 #include "qapi/visitor.h" 58 #include "standard-headers/linux/input.h" 59 60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 62 void *data) \ 63 { \ 64 MachineClass *mc = MACHINE_CLASS(oc); \ 65 virt_machine_##major##_##minor##_options(mc); \ 66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 67 if (latest) { \ 68 mc->alias = "virt"; \ 69 } \ 70 } \ 71 static const TypeInfo machvirt_##major##_##minor##_info = { \ 72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 73 .parent = TYPE_VIRT_MACHINE, \ 74 .instance_init = virt_##major##_##minor##_instance_init, \ 75 .class_init = virt_##major##_##minor##_class_init, \ 76 }; \ 77 static void machvirt_machine_##major##_##minor##_init(void) \ 78 { \ 79 type_register_static(&machvirt_##major##_##minor##_info); \ 80 } \ 81 type_init(machvirt_machine_##major##_##minor##_init); 82 83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 85 #define DEFINE_VIRT_MACHINE(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 87 88 89 /* Number of external interrupt lines to configure the GIC with */ 90 #define NUM_IRQS 256 91 92 #define PLATFORM_BUS_NUM_IRQS 64 93 94 static ARMPlatformBusSystemParams platform_bus_params; 95 96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 97 * RAM can go up to the 256GB mark, leaving 256GB of the physical 98 * address space unallocated and free for future use between 256G and 512G. 99 * If we need to provide more RAM to VMs in the future then we need to: 100 * * allocate a second bank of RAM starting at 2TB and working up 101 * * fix the DT and ACPI table generation code in QEMU to correctly 102 * report two split lumps of RAM to the guest 103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 104 * (We don't want to fill all the way up to 512GB with RAM because 105 * we might want it for non-RAM purposes later. Conversely it seems 106 * reasonable to assume that anybody configuring a VM with a quarter 107 * of a terabyte of RAM will be doing it on a host with more than a 108 * terabyte of physical address space.) 109 */ 110 #define RAMLIMIT_GB 255 111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 112 113 /* Addresses and sizes of our components. 114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 115 * 128MB..256MB is used for miscellaneous device I/O. 116 * 256MB..1GB is reserved for possible future PCI support (ie where the 117 * PCI memory window will go if we add a PCI host controller). 118 * 1GB and up is RAM (which may happily spill over into the 119 * high memory region beyond 4GB). 120 * This represents a compromise between how much RAM can be given to 121 * a 32 bit VM and leaving space for expansion and in particular for PCI. 122 * Note that devices should generally be placed at multiples of 0x10000, 123 * to accommodate guests using 64K pages. 124 */ 125 static const MemMapEntry a15memmap[] = { 126 /* Space up to 0x8000000 is reserved for a boot ROM */ 127 [VIRT_FLASH] = { 0, 0x08000000 }, 128 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 130 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 131 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 132 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 134 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 135 /* This redistributor space allows up to 2*64kB*123 CPUs */ 136 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 137 [VIRT_UART] = { 0x09000000, 0x00001000 }, 138 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 139 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 140 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 141 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 142 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 144 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 145 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 146 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 147 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 148 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 149 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 150 /* Second PCIe window, 512GB wide at the 512GB boundary */ 151 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 152 }; 153 154 static const int a15irqmap[] = { 155 [VIRT_UART] = 1, 156 [VIRT_RTC] = 2, 157 [VIRT_PCIE] = 3, /* ... to 6 */ 158 [VIRT_GPIO] = 7, 159 [VIRT_SECURE_UART] = 8, 160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 163 }; 164 165 static const char *valid_cpus[] = { 166 "cortex-a15", 167 "cortex-a53", 168 "cortex-a57", 169 "host", 170 }; 171 172 static bool cpuname_valid(const char *cpu) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 177 if (strcmp(cpu, valid_cpus[i]) == 0) { 178 return true; 179 } 180 } 181 return false; 182 } 183 184 static void create_fdt(VirtMachineState *vms) 185 { 186 void *fdt = create_device_tree(&vms->fdt_size); 187 188 if (!fdt) { 189 error_report("create_device_tree() failed"); 190 exit(1); 191 } 192 193 vms->fdt = fdt; 194 195 /* Header */ 196 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 197 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 198 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 199 200 /* 201 * /chosen and /memory nodes must exist for load_dtb 202 * to fill in necessary properties later 203 */ 204 qemu_fdt_add_subnode(fdt, "/chosen"); 205 qemu_fdt_add_subnode(fdt, "/memory"); 206 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 207 208 /* Clock node, for the benefit of the UART. The kernel device tree 209 * binding documentation claims the PL011 node clock properties are 210 * optional but in practice if you omit them the kernel refuses to 211 * probe for the device. 212 */ 213 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 214 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 215 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 216 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 217 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 218 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 219 "clk24mhz"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 221 222 } 223 224 static void fdt_add_psci_node(const VirtMachineState *vms) 225 { 226 uint32_t cpu_suspend_fn; 227 uint32_t cpu_off_fn; 228 uint32_t cpu_on_fn; 229 uint32_t migrate_fn; 230 void *fdt = vms->fdt; 231 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 232 233 if (!vms->using_psci) { 234 return; 235 } 236 237 qemu_fdt_add_subnode(fdt, "/psci"); 238 if (armcpu->psci_version == 2) { 239 const char comp[] = "arm,psci-0.2\0arm,psci"; 240 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 241 242 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 243 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 244 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 245 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 246 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 247 } else { 248 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 249 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 250 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 251 } 252 } else { 253 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 254 255 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 256 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 257 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 258 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 259 } 260 261 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 262 * to the instruction that should be used to invoke PSCI functions. 263 * However, the device tree binding uses 'method' instead, so that is 264 * what we should use here. 265 */ 266 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 267 268 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 269 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 270 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 271 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 272 } 273 274 static void fdt_add_timer_nodes(const VirtMachineState *vms) 275 { 276 /* On real hardware these interrupts are level-triggered. 277 * On KVM they were edge-triggered before host kernel version 4.4, 278 * and level-triggered afterwards. 279 * On emulated QEMU they are level-triggered. 280 * 281 * Getting the DTB info about them wrong is awkward for some 282 * guest kernels: 283 * pre-4.8 ignore the DT and leave the interrupt configured 284 * with whatever the GIC reset value (or the bootloader) left it at 285 * 4.8 before rc6 honour the incorrect data by programming it back 286 * into the GIC, causing problems 287 * 4.8rc6 and later ignore the DT and always write "level triggered" 288 * into the GIC 289 * 290 * For backwards-compatibility, virt-2.8 and earlier will continue 291 * to say these are edge-triggered, but later machines will report 292 * the correct information. 293 */ 294 ARMCPU *armcpu; 295 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 296 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 297 298 if (vmc->claim_edge_triggered_timers) { 299 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 300 } 301 302 if (vms->gic_version == 2) { 303 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 304 GIC_FDT_IRQ_PPI_CPU_WIDTH, 305 (1 << vms->smp_cpus) - 1); 306 } 307 308 qemu_fdt_add_subnode(vms->fdt, "/timer"); 309 310 armcpu = ARM_CPU(qemu_get_cpu(0)); 311 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 312 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 313 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 314 compat, sizeof(compat)); 315 } else { 316 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 317 "arm,armv7-timer"); 318 } 319 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 320 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 321 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 322 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 323 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 324 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 325 } 326 327 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 328 { 329 int cpu; 330 int addr_cells = 1; 331 unsigned int i; 332 333 /* 334 * From Documentation/devicetree/bindings/arm/cpus.txt 335 * On ARM v8 64-bit systems value should be set to 2, 336 * that corresponds to the MPIDR_EL1 register size. 337 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 338 * in the system, #address-cells can be set to 1, since 339 * MPIDR_EL1[63:32] bits are not used for CPUs 340 * identification. 341 * 342 * Here we actually don't know whether our system is 32- or 64-bit one. 343 * The simplest way to go is to examine affinity IDs of all our CPUs. If 344 * at least one of them has Aff3 populated, we set #address-cells to 2. 345 */ 346 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 347 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 348 349 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 350 addr_cells = 2; 351 break; 352 } 353 } 354 355 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 356 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 357 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 358 359 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 360 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 361 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 362 363 qemu_fdt_add_subnode(vms->fdt, nodename); 364 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 365 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 366 armcpu->dtb_compatible); 367 368 if (vms->using_psci && vms->smp_cpus > 1) { 369 qemu_fdt_setprop_string(vms->fdt, nodename, 370 "enable-method", "psci"); 371 } 372 373 if (addr_cells == 2) { 374 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 375 armcpu->mp_affinity); 376 } else { 377 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 378 armcpu->mp_affinity); 379 } 380 381 i = numa_get_node_for_cpu(cpu); 382 if (i < nb_numa_nodes) { 383 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", i); 384 } 385 386 g_free(nodename); 387 } 388 } 389 390 static void fdt_add_its_gic_node(VirtMachineState *vms) 391 { 392 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 393 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 394 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 395 "arm,gic-v3-its"); 396 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 397 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 398 2, vms->memmap[VIRT_GIC_ITS].base, 399 2, vms->memmap[VIRT_GIC_ITS].size); 400 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 401 } 402 403 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 404 { 405 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 406 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 407 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 408 "arm,gic-v2m-frame"); 409 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 410 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 411 2, vms->memmap[VIRT_GIC_V2M].base, 412 2, vms->memmap[VIRT_GIC_V2M].size); 413 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 414 } 415 416 static void fdt_add_gic_node(VirtMachineState *vms) 417 { 418 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 419 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 420 421 qemu_fdt_add_subnode(vms->fdt, "/intc"); 422 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 423 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 424 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 425 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 426 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 427 if (vms->gic_version == 3) { 428 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 429 "arm,gic-v3"); 430 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 431 2, vms->memmap[VIRT_GIC_DIST].base, 432 2, vms->memmap[VIRT_GIC_DIST].size, 433 2, vms->memmap[VIRT_GIC_REDIST].base, 434 2, vms->memmap[VIRT_GIC_REDIST].size); 435 } else { 436 /* 'cortex-a15-gic' means 'GIC v2' */ 437 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 438 "arm,cortex-a15-gic"); 439 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 440 2, vms->memmap[VIRT_GIC_DIST].base, 441 2, vms->memmap[VIRT_GIC_DIST].size, 442 2, vms->memmap[VIRT_GIC_CPU].base, 443 2, vms->memmap[VIRT_GIC_CPU].size); 444 } 445 446 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 447 } 448 449 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 450 { 451 CPUState *cpu; 452 ARMCPU *armcpu; 453 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 454 455 CPU_FOREACH(cpu) { 456 armcpu = ARM_CPU(cpu); 457 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || 458 !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { 459 return; 460 } 461 } 462 463 if (vms->gic_version == 2) { 464 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 465 GIC_FDT_IRQ_PPI_CPU_WIDTH, 466 (1 << vms->smp_cpus) - 1); 467 } 468 469 armcpu = ARM_CPU(qemu_get_cpu(0)); 470 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 471 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 472 const char compat[] = "arm,armv8-pmuv3"; 473 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 474 compat, sizeof(compat)); 475 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 476 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 477 } 478 } 479 480 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 481 { 482 const char *itsclass = its_class_name(); 483 DeviceState *dev; 484 485 if (!itsclass) { 486 /* Do nothing if not supported */ 487 return; 488 } 489 490 dev = qdev_create(NULL, itsclass); 491 492 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 493 &error_abort); 494 qdev_init_nofail(dev); 495 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 496 497 fdt_add_its_gic_node(vms); 498 } 499 500 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 501 { 502 int i; 503 int irq = vms->irqmap[VIRT_GIC_V2M]; 504 DeviceState *dev; 505 506 dev = qdev_create(NULL, "arm-gicv2m"); 507 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 508 qdev_prop_set_uint32(dev, "base-spi", irq); 509 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 510 qdev_init_nofail(dev); 511 512 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 513 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 514 } 515 516 fdt_add_v2m_gic_node(vms); 517 } 518 519 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 520 { 521 /* We create a standalone GIC */ 522 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 523 DeviceState *gicdev; 524 SysBusDevice *gicbusdev; 525 const char *gictype; 526 int type = vms->gic_version, i; 527 528 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 529 530 gicdev = qdev_create(NULL, gictype); 531 qdev_prop_set_uint32(gicdev, "revision", type); 532 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 533 /* Note that the num-irq property counts both internal and external 534 * interrupts; there are always 32 of the former (mandated by GIC spec). 535 */ 536 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 537 if (!kvm_irqchip_in_kernel()) { 538 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 539 } 540 qdev_init_nofail(gicdev); 541 gicbusdev = SYS_BUS_DEVICE(gicdev); 542 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 543 if (type == 3) { 544 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 545 } else { 546 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 547 } 548 549 /* Wire the outputs from each CPU's generic timer to the 550 * appropriate GIC PPI inputs, and the GIC's IRQ output to 551 * the CPU's IRQ input. 552 */ 553 for (i = 0; i < smp_cpus; i++) { 554 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 555 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 556 int irq; 557 /* Mapping from the output timer irq lines from the CPU to the 558 * GIC PPI inputs we use for the virt board. 559 */ 560 const int timer_irq[] = { 561 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 562 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 563 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 564 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 565 }; 566 567 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 568 qdev_connect_gpio_out(cpudev, irq, 569 qdev_get_gpio_in(gicdev, 570 ppibase + timer_irq[irq])); 571 } 572 573 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 574 sysbus_connect_irq(gicbusdev, i + smp_cpus, 575 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 576 } 577 578 for (i = 0; i < NUM_IRQS; i++) { 579 pic[i] = qdev_get_gpio_in(gicdev, i); 580 } 581 582 fdt_add_gic_node(vms); 583 584 if (type == 3 && !vmc->no_its) { 585 create_its(vms, gicdev); 586 } else if (type == 2) { 587 create_v2m(vms, pic); 588 } 589 } 590 591 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 592 MemoryRegion *mem, CharDriverState *chr) 593 { 594 char *nodename; 595 hwaddr base = vms->memmap[uart].base; 596 hwaddr size = vms->memmap[uart].size; 597 int irq = vms->irqmap[uart]; 598 const char compat[] = "arm,pl011\0arm,primecell"; 599 const char clocknames[] = "uartclk\0apb_pclk"; 600 DeviceState *dev = qdev_create(NULL, "pl011"); 601 SysBusDevice *s = SYS_BUS_DEVICE(dev); 602 603 qdev_prop_set_chr(dev, "chardev", chr); 604 qdev_init_nofail(dev); 605 memory_region_add_subregion(mem, base, 606 sysbus_mmio_get_region(s, 0)); 607 sysbus_connect_irq(s, 0, pic[irq]); 608 609 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 610 qemu_fdt_add_subnode(vms->fdt, nodename); 611 /* Note that we can't use setprop_string because of the embedded NUL */ 612 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 613 compat, sizeof(compat)); 614 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 615 2, base, 2, size); 616 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 617 GIC_FDT_IRQ_TYPE_SPI, irq, 618 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 619 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 620 vms->clock_phandle, vms->clock_phandle); 621 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 622 clocknames, sizeof(clocknames)); 623 624 if (uart == VIRT_UART) { 625 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 626 } else { 627 /* Mark as not usable by the normal world */ 628 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 629 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 630 } 631 632 g_free(nodename); 633 } 634 635 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 636 { 637 char *nodename; 638 hwaddr base = vms->memmap[VIRT_RTC].base; 639 hwaddr size = vms->memmap[VIRT_RTC].size; 640 int irq = vms->irqmap[VIRT_RTC]; 641 const char compat[] = "arm,pl031\0arm,primecell"; 642 643 sysbus_create_simple("pl031", base, pic[irq]); 644 645 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 646 qemu_fdt_add_subnode(vms->fdt, nodename); 647 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 648 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 649 2, base, 2, size); 650 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 651 GIC_FDT_IRQ_TYPE_SPI, irq, 652 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 653 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 654 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 655 g_free(nodename); 656 } 657 658 static DeviceState *gpio_key_dev; 659 static void virt_powerdown_req(Notifier *n, void *opaque) 660 { 661 /* use gpio Pin 3 for power button event */ 662 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 663 } 664 665 static Notifier virt_system_powerdown_notifier = { 666 .notify = virt_powerdown_req 667 }; 668 669 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 670 { 671 char *nodename; 672 DeviceState *pl061_dev; 673 hwaddr base = vms->memmap[VIRT_GPIO].base; 674 hwaddr size = vms->memmap[VIRT_GPIO].size; 675 int irq = vms->irqmap[VIRT_GPIO]; 676 const char compat[] = "arm,pl061\0arm,primecell"; 677 678 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 679 680 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 681 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 682 qemu_fdt_add_subnode(vms->fdt, nodename); 683 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 684 2, base, 2, size); 685 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 686 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 687 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 688 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 689 GIC_FDT_IRQ_TYPE_SPI, irq, 690 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 691 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 692 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 693 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 694 695 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 696 qdev_get_gpio_in(pl061_dev, 3)); 697 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 698 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 699 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 700 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 701 702 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 703 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 704 "label", "GPIO Key Poweroff"); 705 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 706 KEY_POWER); 707 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 708 "gpios", phandle, 3, 0); 709 710 /* connect powerdown request */ 711 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 712 713 g_free(nodename); 714 } 715 716 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 717 { 718 int i; 719 hwaddr size = vms->memmap[VIRT_MMIO].size; 720 721 /* We create the transports in forwards order. Since qbus_realize() 722 * prepends (not appends) new child buses, the incrementing loop below will 723 * create a list of virtio-mmio buses with decreasing base addresses. 724 * 725 * When a -device option is processed from the command line, 726 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 727 * order. The upshot is that -device options in increasing command line 728 * order are mapped to virtio-mmio buses with decreasing base addresses. 729 * 730 * When this code was originally written, that arrangement ensured that the 731 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 732 * the first -device on the command line. (The end-to-end order is a 733 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 734 * guest kernel's name-to-address assignment strategy.) 735 * 736 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 737 * the message, if not necessarily the code, of commit 70161ff336. 738 * Therefore the loop now establishes the inverse of the original intent. 739 * 740 * Unfortunately, we can't counteract the kernel change by reversing the 741 * loop; it would break existing command lines. 742 * 743 * In any case, the kernel makes no guarantee about the stability of 744 * enumeration order of virtio devices (as demonstrated by it changing 745 * between kernel versions). For reliable and stable identification 746 * of disks users must use UUIDs or similar mechanisms. 747 */ 748 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 749 int irq = vms->irqmap[VIRT_MMIO] + i; 750 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 751 752 sysbus_create_simple("virtio-mmio", base, pic[irq]); 753 } 754 755 /* We add dtb nodes in reverse order so that they appear in the finished 756 * device tree lowest address first. 757 * 758 * Note that this mapping is independent of the loop above. The previous 759 * loop influences virtio device to virtio transport assignment, whereas 760 * this loop controls how virtio transports are laid out in the dtb. 761 */ 762 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 763 char *nodename; 764 int irq = vms->irqmap[VIRT_MMIO] + i; 765 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 766 767 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 768 qemu_fdt_add_subnode(vms->fdt, nodename); 769 qemu_fdt_setprop_string(vms->fdt, nodename, 770 "compatible", "virtio,mmio"); 771 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 772 2, base, 2, size); 773 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 774 GIC_FDT_IRQ_TYPE_SPI, irq, 775 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 776 g_free(nodename); 777 } 778 } 779 780 static void create_one_flash(const char *name, hwaddr flashbase, 781 hwaddr flashsize, const char *file, 782 MemoryRegion *sysmem) 783 { 784 /* Create and map a single flash device. We use the same 785 * parameters as the flash devices on the Versatile Express board. 786 */ 787 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 788 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 789 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 790 const uint64_t sectorlength = 256 * 1024; 791 792 if (dinfo) { 793 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 794 &error_abort); 795 } 796 797 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 798 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 799 qdev_prop_set_uint8(dev, "width", 4); 800 qdev_prop_set_uint8(dev, "device-width", 2); 801 qdev_prop_set_bit(dev, "big-endian", false); 802 qdev_prop_set_uint16(dev, "id0", 0x89); 803 qdev_prop_set_uint16(dev, "id1", 0x18); 804 qdev_prop_set_uint16(dev, "id2", 0x00); 805 qdev_prop_set_uint16(dev, "id3", 0x00); 806 qdev_prop_set_string(dev, "name", name); 807 qdev_init_nofail(dev); 808 809 memory_region_add_subregion(sysmem, flashbase, 810 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 811 812 if (file) { 813 char *fn; 814 int image_size; 815 816 if (drive_get(IF_PFLASH, 0, 0)) { 817 error_report("The contents of the first flash device may be " 818 "specified with -bios or with -drive if=pflash... " 819 "but you cannot use both options at once"); 820 exit(1); 821 } 822 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 823 if (!fn) { 824 error_report("Could not find ROM image '%s'", file); 825 exit(1); 826 } 827 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 828 g_free(fn); 829 if (image_size < 0) { 830 error_report("Could not load ROM image '%s'", file); 831 exit(1); 832 } 833 } 834 } 835 836 static void create_flash(const VirtMachineState *vms, 837 MemoryRegion *sysmem, 838 MemoryRegion *secure_sysmem) 839 { 840 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 841 * Any file passed via -bios goes in the first of these. 842 * sysmem is the system memory space. secure_sysmem is the secure view 843 * of the system, and the first flash device should be made visible only 844 * there. The second flash device is visible to both secure and nonsecure. 845 * If sysmem == secure_sysmem this means there is no separate Secure 846 * address space and both flash devices are generally visible. 847 */ 848 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 849 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 850 char *nodename; 851 852 create_one_flash("virt.flash0", flashbase, flashsize, 853 bios_name, secure_sysmem); 854 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 855 NULL, sysmem); 856 857 if (sysmem == secure_sysmem) { 858 /* Report both flash devices as a single node in the DT */ 859 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 860 qemu_fdt_add_subnode(vms->fdt, nodename); 861 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 862 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 863 2, flashbase, 2, flashsize, 864 2, flashbase + flashsize, 2, flashsize); 865 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 866 g_free(nodename); 867 } else { 868 /* Report the devices as separate nodes so we can mark one as 869 * only visible to the secure world. 870 */ 871 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 872 qemu_fdt_add_subnode(vms->fdt, nodename); 873 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 874 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 875 2, flashbase, 2, flashsize); 876 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 877 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 878 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 879 g_free(nodename); 880 881 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 882 qemu_fdt_add_subnode(vms->fdt, nodename); 883 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 884 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 885 2, flashbase + flashsize, 2, flashsize); 886 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 887 g_free(nodename); 888 } 889 } 890 891 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 892 { 893 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 894 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 895 FWCfgState *fw_cfg; 896 char *nodename; 897 898 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 899 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 900 901 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 902 qemu_fdt_add_subnode(vms->fdt, nodename); 903 qemu_fdt_setprop_string(vms->fdt, nodename, 904 "compatible", "qemu,fw-cfg-mmio"); 905 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 906 2, base, 2, size); 907 g_free(nodename); 908 return fw_cfg; 909 } 910 911 static void create_pcie_irq_map(const VirtMachineState *vms, 912 uint32_t gic_phandle, 913 int first_irq, const char *nodename) 914 { 915 int devfn, pin; 916 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 917 uint32_t *irq_map = full_irq_map; 918 919 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 920 for (pin = 0; pin < 4; pin++) { 921 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 922 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 923 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 924 int i; 925 926 uint32_t map[] = { 927 devfn << 8, 0, 0, /* devfn */ 928 pin + 1, /* PCI pin */ 929 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 930 931 /* Convert map to big endian */ 932 for (i = 0; i < 10; i++) { 933 irq_map[i] = cpu_to_be32(map[i]); 934 } 935 irq_map += 10; 936 } 937 } 938 939 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 940 full_irq_map, sizeof(full_irq_map)); 941 942 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 943 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 944 0x7 /* PCI irq */); 945 } 946 947 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 948 { 949 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 950 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 951 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 952 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 953 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 954 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 955 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 956 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 957 hwaddr base = base_mmio; 958 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 959 int irq = vms->irqmap[VIRT_PCIE]; 960 MemoryRegion *mmio_alias; 961 MemoryRegion *mmio_reg; 962 MemoryRegion *ecam_alias; 963 MemoryRegion *ecam_reg; 964 DeviceState *dev; 965 char *nodename; 966 int i; 967 PCIHostState *pci; 968 969 dev = qdev_create(NULL, TYPE_GPEX_HOST); 970 qdev_init_nofail(dev); 971 972 /* Map only the first size_ecam bytes of ECAM space */ 973 ecam_alias = g_new0(MemoryRegion, 1); 974 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 975 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 976 ecam_reg, 0, size_ecam); 977 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 978 979 /* Map the MMIO window into system address space so as to expose 980 * the section of PCI MMIO space which starts at the same base address 981 * (ie 1:1 mapping for that part of PCI MMIO space visible through 982 * the window). 983 */ 984 mmio_alias = g_new0(MemoryRegion, 1); 985 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 986 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 987 mmio_reg, base_mmio, size_mmio); 988 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 989 990 if (vms->highmem) { 991 /* Map high MMIO space */ 992 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 993 994 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 995 mmio_reg, base_mmio_high, size_mmio_high); 996 memory_region_add_subregion(get_system_memory(), base_mmio_high, 997 high_mmio_alias); 998 } 999 1000 /* Map IO port space */ 1001 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1002 1003 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1004 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1005 } 1006 1007 pci = PCI_HOST_BRIDGE(dev); 1008 if (pci->bus) { 1009 for (i = 0; i < nb_nics; i++) { 1010 NICInfo *nd = &nd_table[i]; 1011 1012 if (!nd->model) { 1013 nd->model = g_strdup("virtio"); 1014 } 1015 1016 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1017 } 1018 } 1019 1020 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1021 qemu_fdt_add_subnode(vms->fdt, nodename); 1022 qemu_fdt_setprop_string(vms->fdt, nodename, 1023 "compatible", "pci-host-ecam-generic"); 1024 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1025 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1026 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1027 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1028 nr_pcie_buses - 1); 1029 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1030 1031 if (vms->msi_phandle) { 1032 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1033 vms->msi_phandle); 1034 } 1035 1036 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1037 2, base_ecam, 2, size_ecam); 1038 1039 if (vms->highmem) { 1040 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1041 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1042 2, base_pio, 2, size_pio, 1043 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1044 2, base_mmio, 2, size_mmio, 1045 1, FDT_PCI_RANGE_MMIO_64BIT, 1046 2, base_mmio_high, 1047 2, base_mmio_high, 2, size_mmio_high); 1048 } else { 1049 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1050 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1051 2, base_pio, 2, size_pio, 1052 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1053 2, base_mmio, 2, size_mmio); 1054 } 1055 1056 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1057 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1058 1059 g_free(nodename); 1060 } 1061 1062 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1063 { 1064 DeviceState *dev; 1065 SysBusDevice *s; 1066 int i; 1067 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1068 MemoryRegion *sysmem = get_system_memory(); 1069 1070 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1071 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1072 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1073 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1074 1075 fdt_params->system_params = &platform_bus_params; 1076 fdt_params->binfo = &vms->bootinfo; 1077 fdt_params->intc = "/intc"; 1078 /* 1079 * register a machine init done notifier that creates the device tree 1080 * nodes of the platform bus and its children dynamic sysbus devices 1081 */ 1082 arm_register_platform_bus_fdt_creator(fdt_params); 1083 1084 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1085 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1086 qdev_prop_set_uint32(dev, "num_irqs", 1087 platform_bus_params.platform_bus_num_irqs); 1088 qdev_prop_set_uint32(dev, "mmio_size", 1089 platform_bus_params.platform_bus_size); 1090 qdev_init_nofail(dev); 1091 s = SYS_BUS_DEVICE(dev); 1092 1093 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1094 int irqn = platform_bus_params.platform_bus_first_irq + i; 1095 sysbus_connect_irq(s, i, pic[irqn]); 1096 } 1097 1098 memory_region_add_subregion(sysmem, 1099 platform_bus_params.platform_bus_base, 1100 sysbus_mmio_get_region(s, 0)); 1101 } 1102 1103 static void create_secure_ram(VirtMachineState *vms, 1104 MemoryRegion *secure_sysmem) 1105 { 1106 MemoryRegion *secram = g_new(MemoryRegion, 1); 1107 char *nodename; 1108 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1109 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1110 1111 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1112 vmstate_register_ram_global(secram); 1113 memory_region_add_subregion(secure_sysmem, base, secram); 1114 1115 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1116 qemu_fdt_add_subnode(vms->fdt, nodename); 1117 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1118 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1119 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1120 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1121 1122 g_free(nodename); 1123 } 1124 1125 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1126 { 1127 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1128 bootinfo); 1129 1130 *fdt_size = board->fdt_size; 1131 return board->fdt; 1132 } 1133 1134 static void virt_build_smbios(VirtMachineState *vms) 1135 { 1136 uint8_t *smbios_tables, *smbios_anchor; 1137 size_t smbios_tables_len, smbios_anchor_len; 1138 const char *product = "QEMU Virtual Machine"; 1139 1140 if (!vms->fw_cfg) { 1141 return; 1142 } 1143 1144 if (kvm_enabled()) { 1145 product = "KVM Virtual Machine"; 1146 } 1147 1148 smbios_set_defaults("QEMU", product, 1149 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1150 1151 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1152 &smbios_anchor, &smbios_anchor_len); 1153 1154 if (smbios_anchor) { 1155 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1156 smbios_tables, smbios_tables_len); 1157 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1158 smbios_anchor, smbios_anchor_len); 1159 } 1160 } 1161 1162 static 1163 void virt_machine_done(Notifier *notifier, void *data) 1164 { 1165 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1166 machine_done); 1167 1168 virt_acpi_setup(vms); 1169 virt_build_smbios(vms); 1170 } 1171 1172 static void machvirt_init(MachineState *machine) 1173 { 1174 VirtMachineState *vms = VIRT_MACHINE(machine); 1175 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1176 qemu_irq pic[NUM_IRQS]; 1177 MemoryRegion *sysmem = get_system_memory(); 1178 MemoryRegion *secure_sysmem = NULL; 1179 int n, virt_max_cpus; 1180 MemoryRegion *ram = g_new(MemoryRegion, 1); 1181 const char *cpu_model = machine->cpu_model; 1182 char **cpustr; 1183 ObjectClass *oc; 1184 const char *typename; 1185 CPUClass *cc; 1186 Error *err = NULL; 1187 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1188 uint8_t clustersz; 1189 1190 if (!cpu_model) { 1191 cpu_model = "cortex-a15"; 1192 } 1193 1194 /* We can probe only here because during property set 1195 * KVM is not available yet 1196 */ 1197 if (!vms->gic_version) { 1198 if (!kvm_enabled()) { 1199 error_report("gic-version=host requires KVM"); 1200 exit(1); 1201 } 1202 1203 vms->gic_version = kvm_arm_vgic_probe(); 1204 if (!vms->gic_version) { 1205 error_report("Unable to determine GIC version supported by host"); 1206 exit(1); 1207 } 1208 } 1209 1210 /* Separate the actual CPU model name from any appended features */ 1211 cpustr = g_strsplit(cpu_model, ",", 2); 1212 1213 if (!cpuname_valid(cpustr[0])) { 1214 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1215 exit(1); 1216 } 1217 1218 /* If we have an EL3 boot ROM then the assumption is that it will 1219 * implement PSCI itself, so disable QEMU's internal implementation 1220 * so it doesn't get in the way. Instead of starting secondary 1221 * CPUs in PSCI powerdown state we will start them all running and 1222 * let the boot ROM sort them out. 1223 * The usual case is that we do use QEMU's PSCI implementation. 1224 */ 1225 vms->using_psci = !(vms->secure && firmware_loaded); 1226 1227 /* The maximum number of CPUs depends on the GIC version, or on how 1228 * many redistributors we can fit into the memory map. 1229 */ 1230 if (vms->gic_version == 3) { 1231 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1232 clustersz = GICV3_TARGETLIST_BITS; 1233 } else { 1234 virt_max_cpus = GIC_NCPU; 1235 clustersz = GIC_TARGETLIST_BITS; 1236 } 1237 1238 if (max_cpus > virt_max_cpus) { 1239 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1240 "supported by machine 'mach-virt' (%d)", 1241 max_cpus, virt_max_cpus); 1242 exit(1); 1243 } 1244 1245 vms->smp_cpus = smp_cpus; 1246 1247 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1248 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1249 exit(1); 1250 } 1251 1252 if (vms->secure) { 1253 if (kvm_enabled()) { 1254 error_report("mach-virt: KVM does not support Security extensions"); 1255 exit(1); 1256 } 1257 1258 /* The Secure view of the world is the same as the NonSecure, 1259 * but with a few extra devices. Create it as a container region 1260 * containing the system memory at low priority; any secure-only 1261 * devices go in at higher priority and take precedence. 1262 */ 1263 secure_sysmem = g_new(MemoryRegion, 1); 1264 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1265 UINT64_MAX); 1266 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1267 } 1268 1269 create_fdt(vms); 1270 1271 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1272 if (!oc) { 1273 error_report("Unable to find CPU definition"); 1274 exit(1); 1275 } 1276 typename = object_class_get_name(oc); 1277 1278 /* convert -smp CPU options specified by the user into global props */ 1279 cc = CPU_CLASS(oc); 1280 cc->parse_features(typename, cpustr[1], &err); 1281 g_strfreev(cpustr); 1282 if (err) { 1283 error_report_err(err); 1284 exit(1); 1285 } 1286 1287 for (n = 0; n < smp_cpus; n++) { 1288 Object *cpuobj = object_new(typename); 1289 if (!vmc->disallow_affinity_adjustment) { 1290 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1291 * GIC's target-list limitations. 32-bit KVM hosts currently 1292 * always create clusters of 4 CPUs, but that is expected to 1293 * change when they gain support for gicv3. When KVM is enabled 1294 * it will override the changes we make here, therefore our 1295 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1296 * and to improve SGI efficiency. 1297 */ 1298 uint8_t aff1 = n / clustersz; 1299 uint8_t aff0 = n % clustersz; 1300 object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0, 1301 "mp-affinity", NULL); 1302 } 1303 1304 if (!vms->secure) { 1305 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1306 } 1307 1308 if (vms->using_psci) { 1309 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, 1310 "psci-conduit", NULL); 1311 1312 /* Secondary CPUs start in PSCI powered-down state */ 1313 if (n > 0) { 1314 object_property_set_bool(cpuobj, true, 1315 "start-powered-off", NULL); 1316 } 1317 } 1318 1319 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1320 object_property_set_bool(cpuobj, false, "pmu", NULL); 1321 } 1322 1323 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1324 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1325 "reset-cbar", &error_abort); 1326 } 1327 1328 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1329 &error_abort); 1330 if (vms->secure) { 1331 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1332 "secure-memory", &error_abort); 1333 } 1334 1335 object_property_set_bool(cpuobj, true, "realized", NULL); 1336 } 1337 fdt_add_timer_nodes(vms); 1338 fdt_add_cpu_nodes(vms); 1339 fdt_add_psci_node(vms); 1340 1341 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1342 machine->ram_size); 1343 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1344 1345 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1346 1347 create_gic(vms, pic); 1348 1349 fdt_add_pmu_nodes(vms); 1350 1351 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1352 1353 if (vms->secure) { 1354 create_secure_ram(vms, secure_sysmem); 1355 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1356 } 1357 1358 create_rtc(vms, pic); 1359 1360 create_pcie(vms, pic); 1361 1362 create_gpio(vms, pic); 1363 1364 /* Create mmio transports, so the user can create virtio backends 1365 * (which will be automatically plugged in to the transports). If 1366 * no backend is created the transport will just sit harmlessly idle. 1367 */ 1368 create_virtio_devices(vms, pic); 1369 1370 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1371 rom_set_fw(vms->fw_cfg); 1372 1373 vms->machine_done.notify = virt_machine_done; 1374 qemu_add_machine_init_done_notifier(&vms->machine_done); 1375 1376 vms->bootinfo.ram_size = machine->ram_size; 1377 vms->bootinfo.kernel_filename = machine->kernel_filename; 1378 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1379 vms->bootinfo.initrd_filename = machine->initrd_filename; 1380 vms->bootinfo.nb_cpus = smp_cpus; 1381 vms->bootinfo.board_id = -1; 1382 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1383 vms->bootinfo.get_dtb = machvirt_dtb; 1384 vms->bootinfo.firmware_loaded = firmware_loaded; 1385 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1386 1387 /* 1388 * arm_load_kernel machine init done notifier registration must 1389 * happen before the platform_bus_create call. In this latter, 1390 * another notifier is registered which adds platform bus nodes. 1391 * Notifiers are executed in registration reverse order. 1392 */ 1393 create_platform_bus(vms, pic); 1394 } 1395 1396 static bool virt_get_secure(Object *obj, Error **errp) 1397 { 1398 VirtMachineState *vms = VIRT_MACHINE(obj); 1399 1400 return vms->secure; 1401 } 1402 1403 static void virt_set_secure(Object *obj, bool value, Error **errp) 1404 { 1405 VirtMachineState *vms = VIRT_MACHINE(obj); 1406 1407 vms->secure = value; 1408 } 1409 1410 static bool virt_get_highmem(Object *obj, Error **errp) 1411 { 1412 VirtMachineState *vms = VIRT_MACHINE(obj); 1413 1414 return vms->highmem; 1415 } 1416 1417 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1418 { 1419 VirtMachineState *vms = VIRT_MACHINE(obj); 1420 1421 vms->highmem = value; 1422 } 1423 1424 static char *virt_get_gic_version(Object *obj, Error **errp) 1425 { 1426 VirtMachineState *vms = VIRT_MACHINE(obj); 1427 const char *val = vms->gic_version == 3 ? "3" : "2"; 1428 1429 return g_strdup(val); 1430 } 1431 1432 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1433 { 1434 VirtMachineState *vms = VIRT_MACHINE(obj); 1435 1436 if (!strcmp(value, "3")) { 1437 vms->gic_version = 3; 1438 } else if (!strcmp(value, "2")) { 1439 vms->gic_version = 2; 1440 } else if (!strcmp(value, "host")) { 1441 vms->gic_version = 0; /* Will probe later */ 1442 } else { 1443 error_setg(errp, "Invalid gic-version value"); 1444 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1445 } 1446 } 1447 1448 static void virt_machine_class_init(ObjectClass *oc, void *data) 1449 { 1450 MachineClass *mc = MACHINE_CLASS(oc); 1451 1452 mc->init = machvirt_init; 1453 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1454 * it later in machvirt_init, where we have more information about the 1455 * configuration of the particular instance. 1456 */ 1457 mc->max_cpus = 255; 1458 mc->has_dynamic_sysbus = true; 1459 mc->block_default_type = IF_VIRTIO; 1460 mc->no_cdrom = 1; 1461 mc->pci_allow_0_address = true; 1462 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1463 mc->minimum_page_bits = 12; 1464 } 1465 1466 static const TypeInfo virt_machine_info = { 1467 .name = TYPE_VIRT_MACHINE, 1468 .parent = TYPE_MACHINE, 1469 .abstract = true, 1470 .instance_size = sizeof(VirtMachineState), 1471 .class_size = sizeof(VirtMachineClass), 1472 .class_init = virt_machine_class_init, 1473 }; 1474 1475 static void machvirt_machine_init(void) 1476 { 1477 type_register_static(&virt_machine_info); 1478 } 1479 type_init(machvirt_machine_init); 1480 1481 static void virt_2_9_instance_init(Object *obj) 1482 { 1483 VirtMachineState *vms = VIRT_MACHINE(obj); 1484 1485 /* EL3 is disabled by default on virt: this makes us consistent 1486 * between KVM and TCG for this board, and it also allows us to 1487 * boot UEFI blobs which assume no TrustZone support. 1488 */ 1489 vms->secure = false; 1490 object_property_add_bool(obj, "secure", virt_get_secure, 1491 virt_set_secure, NULL); 1492 object_property_set_description(obj, "secure", 1493 "Set on/off to enable/disable the ARM " 1494 "Security Extensions (TrustZone)", 1495 NULL); 1496 1497 /* High memory is enabled by default */ 1498 vms->highmem = true; 1499 object_property_add_bool(obj, "highmem", virt_get_highmem, 1500 virt_set_highmem, NULL); 1501 object_property_set_description(obj, "highmem", 1502 "Set on/off to enable/disable using " 1503 "physical address space above 32 bits", 1504 NULL); 1505 /* Default GIC type is v2 */ 1506 vms->gic_version = 2; 1507 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1508 virt_set_gic_version, NULL); 1509 object_property_set_description(obj, "gic-version", 1510 "Set GIC version. " 1511 "Valid values are 2, 3 and host", NULL); 1512 1513 vms->memmap = a15memmap; 1514 vms->irqmap = a15irqmap; 1515 } 1516 1517 static void virt_machine_2_9_options(MachineClass *mc) 1518 { 1519 } 1520 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) 1521 1522 #define VIRT_COMPAT_2_8 \ 1523 HW_COMPAT_2_8 1524 1525 static void virt_2_8_instance_init(Object *obj) 1526 { 1527 virt_2_9_instance_init(obj); 1528 } 1529 1530 static void virt_machine_2_8_options(MachineClass *mc) 1531 { 1532 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1533 1534 virt_machine_2_9_options(mc); 1535 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1536 /* For 2.8 and earlier we falsely claimed in the DT that 1537 * our timers were edge-triggered, not level-triggered. 1538 */ 1539 vmc->claim_edge_triggered_timers = true; 1540 } 1541 DEFINE_VIRT_MACHINE(2, 8) 1542 1543 #define VIRT_COMPAT_2_7 \ 1544 HW_COMPAT_2_7 1545 1546 static void virt_2_7_instance_init(Object *obj) 1547 { 1548 virt_2_8_instance_init(obj); 1549 } 1550 1551 static void virt_machine_2_7_options(MachineClass *mc) 1552 { 1553 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1554 1555 virt_machine_2_8_options(mc); 1556 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1557 /* ITS was introduced with 2.8 */ 1558 vmc->no_its = true; 1559 /* Stick with 1K pages for migration compatibility */ 1560 mc->minimum_page_bits = 0; 1561 } 1562 DEFINE_VIRT_MACHINE(2, 7) 1563 1564 #define VIRT_COMPAT_2_6 \ 1565 HW_COMPAT_2_6 1566 1567 static void virt_2_6_instance_init(Object *obj) 1568 { 1569 virt_2_7_instance_init(obj); 1570 } 1571 1572 static void virt_machine_2_6_options(MachineClass *mc) 1573 { 1574 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1575 1576 virt_machine_2_7_options(mc); 1577 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1578 vmc->disallow_affinity_adjustment = true; 1579 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1580 vmc->no_pmu = true; 1581 } 1582 DEFINE_VIRT_MACHINE(2, 6) 1583